Organic Reactant Patents (Class 438/790)
  • Patent number: 6797643
    Abstract: A method of depositing a low dielectric constant film on a substrate. In one embodiment, the method includes the steps of positioning the substrate in a deposition chamber, providing a gas mixture to the deposition chamber, in which the gas mixture is comprised of one or more cyclic organosilicon compounds, one or more aliphatic compounds and one or more oxidizing gases. The method further includes reacting the gas mixture in the presence of an electric field to form the low dielectric constant film on the semiconductor substrate. The electric field is generated using a very high frequency power having a frequency in a range of about 20 MHz to about 100 MHz.
    Type: Grant
    Filed: October 23, 2002
    Date of Patent: September 28, 2004
    Assignee: Applied Materials Inc.
    Inventors: Juan Carlos Rocha-Alvarez, Maosheng Zhao, Ying Yu, Shankar Venkataraman, Srinivas D. Nemani, Li-Qun Xia
  • Publication number: 20040180557
    Abstract: A method is provided for forming a silicon dioxide film using atomic layer deposition (ALD), wherein a halogen- or NCO-substituted siloxane is used as a Si source. The method includes feeding a substituted siloxane as a first reactant onto a substrate to form a chemisorbed layer of the first reactant, and thereafter feeding a compound consisting of oxygen and hydrogen as a second reactant onto the chemisorbed layer to form the desired silicon dioxide film.
    Type: Application
    Filed: February 19, 2004
    Publication date: September 16, 2004
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jae-eun Park, Kang-soo Chu, Joo-won Lee, Jong-ho Yang
  • Patent number: 6790749
    Abstract: An object of this invention is to provide a semiconductor device manufacturing method in which a semiconductor film is formed over a substrate, the semiconductor film is crystallized by irradiating a laser light, a silicon oxide film is formed in contact with the crystalline semiconductor film by using organic silane, a gate electrode is formed in contact with the silicon oxide film, an impurity element is introduced into the crystalline semiconductor film, the impurity element is activated, an interlayer insulating film is formed over the gate electrode, and then a wiring comprising aluminum is formed over the interlayer insulating film.
    Type: Grant
    Filed: September 12, 2002
    Date of Patent: September 14, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasuhiko Takemura, Hongyong Zhang, Satoshi Teramoto
  • Patent number: 6790792
    Abstract: A cured polyphenylene polymer having a glass transition temperature no greater than 465° C. An integrated circuit article having a fracture toughness as determined by the modified edge liftoff test of at least 0.3 MPa-m1/2.
    Type: Grant
    Filed: April 29, 2002
    Date of Patent: September 14, 2004
    Assignee: Dow Global Technologies Inc.
    Inventors: Edward O. Shaffer, II, Kevin E. Howard, James P. Godschalx, Paul H. Townsend, III
  • Patent number: 6787445
    Abstract: A fluorine-containing organic film is deposited on a semiconductor substrate using a material gas containing fluorocarbon as a main component in a reactor chamber of a plasma processing apparatus. The fluorine-containing organic film is then exposed to plasma of a rare gas in the same reactor chamber to densify the fluorine-containing organic film.
    Type: Grant
    Filed: November 8, 2000
    Date of Patent: September 7, 2004
    Assignee: Matsushita Electric Industry Co., Ltd.
    Inventors: Nobuhiro Jiwari, Shinichi Imai
  • Patent number: 6784122
    Abstract: A method for depositing highly conformal silicate glass layers via chemical vapor deposition through the reaction of TEOS and O3 comprises placing an in-process semiconductor wafer having multiple surface constituents in a plasma-enhanced chemical vapor deposition chamber.
    Type: Grant
    Filed: February 21, 2003
    Date of Patent: August 31, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Ravi Iyer
  • Patent number: 6784121
    Abstract: A xerogel aging system includes an aging chamber (190) with inlets and outlet and flows a gel catalyst in gas phase over a xerogel precursor film on a semiconductor wafer. Preferred embodiments use an ammonia and water vapor gas mixture catalyst.
    Type: Grant
    Filed: October 23, 1998
    Date of Patent: August 31, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Changming Jin, Richard Scott List, Joseph D. Luttmer
  • Patent number: 6784118
    Abstract: In order to vaporize an organic monomer at a high temperature and a high saturated vapor pressure in good efficiency and to grow an organic polymer film at a high rate in high vacuum by a plasma polymerization reaction of the resulting organic monomer gas, a liquid divinylsiloxanebisbenzocyclobutene (DVS-BCB) monomer is mixed with a carrier gas, and the mixture is then sprayed on a vaporization vacuum chamber held at a high temperature to form an aerosol made of liquid fine particles of the organic monomer, and a BCB monomer (organic monomer) is instantaneously vaporized via the aerosol to generate a BCB monomer gas (organic monomer gas). Consequently, the aerosol having a large specific surface area has a large vaporization area, and vaporization occurs by heating at a high temperature before a polymerization reaction occurs. Thus, 0.1 g/min or more of the BCB monomer gas can be formed at 200° C.
    Type: Grant
    Filed: April 20, 2001
    Date of Patent: August 31, 2004
    Assignee: NEC Corporation
    Inventors: Yoshihiro Hayashi, Jun Kawahara, Hirofumi Ono
  • Patent number: 6784092
    Abstract: Disclosed is a method for forming an insulating layer, including coating a substrate with an insulating film material to form a coated film, the insulating film material containing at least first and second polymers differing from each other in average molecular weight, and heating the coated film while irradiating the coated film with an electron beam.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: August 31, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideshi Miyajima, Miyoko Shimada, Rempei Nakata
  • Patent number: 6780704
    Abstract: Method and structures are provided for conformal capacitor dielectrics over textured silicon electrodes for integrated memory cells. Capacitor structures and first electrodes or plates are formed above or within semiconductor substrates. The first electrodes include hemispherical grain (HSG) silicon for increasing the capacitor plate surface area. The HSG topography is then exposed to alternating chemistries to form monolayers of a desired dielectric material. Exemplary process flows include alternately pulsed metal organic and oxygen source gases injected into a constant carrier flow. Self-terminated metal layers are thus reacted with oxygen. Near perfect step coverage allows minimal thickness for a capacitor dielectric, given leakage concerns for particular materials, thereby maximizing the capacitance for the memory cell and increasing cell reliability for a given memory cell design.
    Type: Grant
    Filed: December 3, 1999
    Date of Patent: August 24, 2004
    Assignee: ASM International NV
    Inventors: Ivo Raaijmakers, Suvi P. Haukka, Ernst H. A. Granneman
  • Patent number: 6777347
    Abstract: A method for forming porous silicon oxide film, comprising the following steps. A CVD chamber having inner walls and a wafer chuck/heater is provided. At least a portion of the CVD chamber inner walls is pre-coated with a layer of first PECVD silicon oxide film having a first thermal CVD oxide deposition rate thereupon. A semiconductor wafer is placed on the wafer chuck/heater within pre-coated CVD chamber. The semiconductor wafer including an upper second PECVD silicon oxide film having a second thermal CVD oxide deposition rate thereupon that is less than the first thermal CVD oxide deposition rate upon the first PECVD silicon oxide film coating the CVD chamber inner walls. A porous silicon oxide film is deposited upon the upper second PECVD silicon oxide film overlying the semiconductor wafer. The porous silicon oxide film being different from the first PECVD silicon oxide film coating the CVD chamber inner walls.
    Type: Grant
    Filed: January 19, 2001
    Date of Patent: August 17, 2004
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chyi-Tsong Ni, Eric Su
  • Patent number: 6774058
    Abstract: A method is disclosed for removing liquids from a semiconductor substrate by contacting the liquid on the substrate with a liquid which attracts the liquid on the substrate, separating the liquids from the substrate, and inducing a phase transition in a layer on the substrate. In particular, the method is applicable to removing water from a water-containing layer on the substrate by contacting the layer with a hygroscopic liquid. Trenches on a substrate can be isolated by filling the trenches with a water-containing gel formed by reacting silane and hydrogen peroxide. The gel is contacted with sulfuric acid to remove a portion of the water from the gel before annealing to form silica in the trenches. Unlike filled trenches formed by conventional technology, there are no voids in the bottom of the trenches. The method is also applicable to forming dielectric layers which cover metal lines, low-dielectric layers, and interlayer dielectric layers.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: August 10, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Li Li
  • Publication number: 20040152342
    Abstract: Methods of forming an oxide layer such as high aspect ratio trench isolations, and treating the oxide substrate to remove carbon, structures formed by the method, and devices and systems incorporating the oxide material are provided.
    Type: Application
    Filed: February 4, 2003
    Publication date: August 5, 2004
    Applicant: Micron Technology, Inc.
    Inventors: Li Li, Weimin Li
  • Patent number: 6764957
    Abstract: A method for forming a contact or via plug is described. A dielectric layer and a patterned photoresist layer are sequentially formed on a substrate. A portion of the exposed dielectric layer is removed to form a first opening. A first liner is formed on the surfaces of the photoresist layer. An anisotropic etching process is conducted using the first liner and the photoresist layer as a mask to remove a portion of the dielectric layer under the first opening to form a second opening incorporating the first opening. A second liner is formed on the photoresist layer covering the first liner. Then, the above etching step is repeated to form a third opening that incorporates the second opening and exposes the substrate. The second liner, the first liner and the photoresist layer are removed, and then a conductive material is filled into the third opening to form a contact or via plug.
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: July 20, 2004
    Assignee: Macronix International Co., Ltd.
    Inventor: Cheng-Ta Yu
  • Patent number: 6764965
    Abstract: A method for improving the coating capability of low dielectric layer is disclosed. The method includes steps of an etching stop layer is deposited a semiconductor substrate, an adhesion promoter layer is spun-on the etching stop layer. The pre-wetting process being performed on the adhesion promoter layer to enhance the coating capability of the low-k dielectric layer, and thus improve the coating quality through the pre-wetting process of baked adhesion promoter layer before the low-k dielectric layer is applied.
    Type: Grant
    Filed: August 17, 2001
    Date of Patent: July 20, 2004
    Assignee: United Microelectronics Corp.
    Inventors: Tsung-Tang Hsieh, Cheng-Yuan Tsai, Chih-An Huang
  • Patent number: 6753270
    Abstract: The present invention relates to a method for providing a dielectric film having a low dielectric constant that is particularly useful as an intermetal dielectric layer. The method of the present invention deposits a porous oxide gap fill layer from a process gas of ozone and TEOS. The gap fill layer is deposited over a surface sensitive lining layer (as opposed to a non-surface sensitive layer as is commonly done in the industry) using deposition conditions that maximize the amount of carbon that is incorporated into the gap fill layer and result in a porous silicon oxide film. A typical SACVD ozone/TEOS gap fill layer has a carbon content of about 2-3 atomic percent (at. %). An SACVD ozone/TEOS gap fill layer deposited according to the present, however, has a carbon content of at least 5 at. % and preferably has a carbon content of between about 7-8 at. %.
    Type: Grant
    Filed: August 4, 2000
    Date of Patent: June 22, 2004
    Assignee: Applied Materials Inc.
    Inventors: Fabrice Geiger, Frederic Gaillard
  • Publication number: 20040115955
    Abstract: A process for easily and efficiently forming a silica-based coating film having a film thickness of from 0.5 to 5 &mgr;m on a substrate, such a coating film, a coating fluid to be used for forming such a coating film, and a process for producing such a coating fluid, are presented.
    Type: Application
    Filed: October 22, 2003
    Publication date: June 17, 2004
    Inventors: Kenichi Motoyama, Takakazu Nakada, Hitoshi Furusho, Hiroyoshi Fukuro
  • Patent number: 6746969
    Abstract: A method of manufacturing a semiconductor device comprises preparing a substrate to be treated, and forming an insulation film above the substrate, which includes applying an insulation film raw material above the substrate, the insulation film raw material including a substance or a precursor of the substance, the insulation film comprising the substance, curing the insulation film raw material by irradiating an electron beam on the substrate while heating the substrate in a reactor chamber, changing at least one of parameter selected from the group consisting of pressure in the reactor chamber, temperature of the substrate, type of gas having the substrate exposed thereto, flow rate of gas introduced into the reactor chamber, position of the substrate, and quantity of electrons incident to the substrate per unit time when the electron beam is being irradiated on the substrate.
    Type: Grant
    Filed: October 19, 2001
    Date of Patent: June 8, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Miyoko Shimada, Hideshi Miyajima, Rempei Nakata, Hideto Matsuyama, Katsuya Okumura, Masahiko Hasunuma, Nobuo Hayasaka
  • Patent number: 6746970
    Abstract: A passivation layer is deposited onto the surface of a substrate followed by deposition of a polymer layer, through the application of a plasma enhanced chemical vapor deposition process, in which the substrate is placed on a chuck within a reaction chamber and fluorocarbon gas is introduced into the reaction chamber under the influence of at least one plasma source. The fluorocarbon gas can be a CFX gas. The at least one plasma source can include a first plasma source that ionizes the fluorocarbon gas by applying RF plasma energy, and a second plasma source that applies a near-zero self-bias to the substrate at an RF frequency during deposition of the passivation layer and a greater bias during deposition of the polymer layer. The passivation layer is deposited prior to the polymer layer to protect the surface of the substrate from damage during the deposition of the polymer layer.
    Type: Grant
    Filed: June 24, 2002
    Date of Patent: June 8, 2004
    Assignee: Macronix International Co., Ltd.
    Inventors: Ming-Chung Liang, Chung Tai Chen, Hsin-Yi Tsai
  • Patent number: 6746931
    Abstract: Disclosed are a capacitor for semiconductor devices capable of increasing storage capacitance and preventing leakage current, and method of manufacturing the same. The capacitor for semiconductor memory devices according to the present invention includes: a lower electrode; a dielectric layer formed on the lower electrode; and an upper electrode formed on the upper portion of the dielectric layer, wherein the dielectric layer is a crystalline TaxOyNz layer, and the total of x, y, and z in the crystalline TaxOyNz layer is 1, and y is 0.3 to 0.5, and z is 0.1 to 0.3.
    Type: Grant
    Filed: April 28, 2003
    Date of Patent: June 8, 2004
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Kee Jeung Lee, Dong Jun Kim
  • Patent number: 6743737
    Abstract: A method and apparatus for depositing a low dielectric constant film includes depositing a silicon oxide based film, preferably by reaction of an organosilicon compound and an oxidizing gas at a low RF power level from about 10 W to about 500 W, exposing the silicon oxide based film to water or a hydrophobic-imparting surfactant such as hexamethyldisilazane, and curing the silicon oxide based film at an elevated temperature. Dissociation of the oxidizing gas can be increased in a separate microwave chamber to assist in controlling the carbon content of the deposited film. The moisture resistance of the silicon oxide based films is enhanced.
    Type: Grant
    Filed: August 22, 2002
    Date of Patent: June 1, 2004
    Assignee: Applied Materials, Inc.
    Inventors: Wai-Fan Yau, David Cheung, Nasreen Gazala Chopra, Yung-Cheng Lu, Robert Mandal, Farhad Moghadam
  • Patent number: 6737363
    Abstract: A method of manufacturing a semiconductor device according to an aspect of the present invention comprises forming a low dielectric constant insulating film having a siloxane bond as main skeleton on a semiconductor substrate, causing a surfactant to permeate the low dielectric constant insulating film, and conducting a predetermined step on the low dielectric constant insulating film permeated with the surfactant in a state adapted to be exposed to water.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: May 18, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideshi Miyajima, Nobuhide Yamada, Nobuo Hayasaka, Nobuyuki Kurashima
  • Patent number: 6730593
    Abstract: A method and apparatus for depositing a low dielectric constant film by reaction of an organo silane compound and an oxidizing gas. The oxidized organo silane film has excellent barrier properties for use as a liner or cap layer adjacent other dielectric layers. The oxidized organo silane film can also be used as an etch stop or an intermetal dielectric layer for fabricating dual damascene structures. The oxidized organo silane films also provide excellent adhesion between different dielectric layers. A preferred oxidized organo silane film is produced by reaction of methyl silane, CH3SiH3, and N2O.
    Type: Grant
    Filed: November 15, 2001
    Date of Patent: May 4, 2004
    Assignee: Applied Materials Inc.
    Inventors: Wai-Fan Yau, David Cheung, Shin-Puu Jeng, Kuowei Liu, Yung-Cheng Yu
  • Patent number: 6727190
    Abstract: In one aspect, the invention includes a method of forming an insulating material comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising a Si, F and ozone within the reaction chamber; and c) depositing an insulating material comprising fluorine, silicon and oxygen onto the substrate from the reactants. In another aspect, the invention includes a method of forming a boron-doped silicon oxide having Si—F bonds, comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising Triethoxy fluorosilane, a boron-containing precursor, and ozone within the reaction chamber; and c) depositing a boron-doped silicon oxide having Si—F bonds onto the substrate from the reactants.
    Type: Grant
    Filed: September 3, 1998
    Date of Patent: April 27, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Anand Srinivasan, Gurtej Sandhu, Ravi Iyer
  • Patent number: 6723641
    Abstract: After forming a phosphor-doped amorphous silicon film and before forming a bottom silicon oxide film, a heat treatment is performed while exhausting a gas from the vicinity of the silicon substrate. The heat treatment is performed at a temperature equal to or higher than that for forming the bottom silicon oxide film and at a pressure equal to or lower than that for forming the bottom silicon oxide film. Alternatively, after forming the phosphor-doped amorphous silicon film and before forming the bottom silicon oxide film, a TEOS oxide film and a phosphor-doped amorphous silicon film deposited on the back surface of the silicon substrate are removed. Further alternatively, these films deposited on the back surface of the silicon substrate are covered with a film which prevents gas desorption under the film formation condition for the bottom silicon oxide film.
    Type: Grant
    Filed: June 4, 2002
    Date of Patent: April 20, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Kojiro Yuzuriha
  • Publication number: 20040072392
    Abstract: The present invention provides a method of forming a low temperature polysilicon thin film transistor (LTPS TFT). A polysilicon layer including a channel region is formed first. A first and a second plasma enhanced chemical vapor deposition processes are sequentially performed to form a composite gate insulating layer composed of a TEOS-based silicon oxide layer and a silicon nitride layer on the channel region. Finally a gate electrode and a source/drain of the low temperature polysilicon thin film transistor are formed.
    Type: Application
    Filed: February 16, 2003
    Publication date: April 15, 2004
    Inventor: Hui-Chu Lin
  • Patent number: 6720251
    Abstract: A nitrogen-free anti-reflective layer for use in semiconductor photolithography is fabricated in a chemical vapor deposition process, optionally plasma-enhanced, using a gaseous mixture of carbon, silicon, and oxygen sources. By varying the process parameters, acceptable values of the refractive index n and extinction coefficient k can be obtained. The nitrogen-free anti-reflective layer produced by this technique eliminates the mushrooming and footing problems found with conventional anti-reflective layers.
    Type: Grant
    Filed: November 21, 2001
    Date of Patent: April 13, 2004
    Assignee: Novellus Systems, Inc.
    Inventors: Bart van Schravendijk, Ming Li, Jason Tian, Tom Mountsier, M. Zlaul Karim
  • Patent number: 6716647
    Abstract: Methods and apparatuses are disclosed that can introduce deliberate semiconductor film variation during semiconductor manufacturing to compensate for radial processing differences, to determine optimal device characteristics, or produce small production runs. The present invention radially varies the thickness and/or composition of a semiconductor film to compensate for a known radial variation in the semiconductor film that is caused by performing a subsequent semiconductor processing step on the semiconductor film. Additionally, methods and apparatuses are disclosed that can introduce deliberate semiconductor film variations to determine optimal device characteristics or produce small production runs. Introducing semiconductor film variations, such as thickness variations and/or composition variations, allow different devices to be made. A number of devices may be made having variations in semiconductor film.
    Type: Grant
    Filed: December 7, 2001
    Date of Patent: April 6, 2004
    Assignee: International Business Machines Corporation
    Inventors: Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David C. Horak
  • Patent number: 6716773
    Abstract: A process for producing semiconductor substrates with a coating film having excellent chemical resistance with high yield and excellent production reliability without any development of cracks and any generation or collection of foreign matter resulting from a projected portion of the coating film, which includes the steps of: (a) forming a coating film by coating an insulating film-forming coating liquid on a substrate mounted on a rotating disc of a spin coater according to a spin coating method; and (b) removing the projected portion of the coating film formed at a periphery of the substrate by ejecting a solvent through a nozzle moving from any point on a line drawn between the periphery edge and a center of the substrate toward the periphery edge while rotating the substrate.
    Type: Grant
    Filed: September 19, 2002
    Date of Patent: April 6, 2004
    Assignee: Catalysts & Chemicals Industries Co., Ltd.
    Inventors: Miki Egami, Ryo Muraguchi
  • Patent number: 6713364
    Abstract: A method for fabricating an insulator on a semiconductor substrate such that the insulator has a low dielectric constant. A first interconnect and a second interconnect are configured on a semiconductor substrate. A conductive silicon is formed between the first interconnect and the second interconnect. The conductive silicon is anodically etched in a hydrofluoric-acid-containing electrolyte to convert the conductive silicon into porous silicon. The porous silicon is subsequently oxidized to form porous silicon oxide. With a dielectric constant of between 1.1 and 4, the porous silicon oxide has a lower dielectric constant than customary silicon oxide with 4.
    Type: Grant
    Filed: July 27, 2001
    Date of Patent: March 30, 2004
    Assignee: Infineon Technologies AG
    Inventor: Markus Kirchhoff
  • Patent number: 6709990
    Abstract: A method for fabricating a silicon dioxide/silicon nitride/silicon dioxide (ONO) stacked composite having a thin silicon nitride layer for providing a high capacitance interpoly dielectric structure. In the formation of the ONO composite, a bottom silicon dioxide layer is formed on a substrate such as polysilicon. A silicon nitride layer is formed on the silicon dioxide layer and is thinned by oxidation. The oxidation of the silicon nitride film consumes some of the silicon nitride by a reaction that produces a silicon dioxide layer. This silicon dioxide layer is removed with a hydrofluoric acid dilution. The silicon nitride layer is again thinned by re-oxidization as a top silicon dioxide layer is formed on the silicon nitride layer. A second layer of polysilicon is deposited over the silicon nitride, forming an interpoly dielectric.
    Type: Grant
    Filed: October 9, 2002
    Date of Patent: March 23, 2004
    Assignee: Atmel Corporation
    Inventors: Mark A. Good, Amit S. Kelkar
  • Patent number: 6709968
    Abstract: A microelectronic device package and method for manufacture. In one embodiment, the device package can include a microelectronic substrate having first and second device features, a conductive link that includes a conductive material extending between the first and second device features, and an external cover attached to the substrate and at least partially enclosing the first and second device features and the conductive link. The external cover can have a composition substantially identical to the composition of the conductive links and the external cover can be formed simultaneously with formation of the conductive link to reduce the number of process steps required to form the microelectronic device package. A sacrificial material can temporarily support the conductive link during manufacture and can subsequently be removed to suspend at least a portion of the conductive link between two points.
    Type: Grant
    Filed: August 16, 2000
    Date of Patent: March 23, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Jerome M. Eldridge, Paul A. Farrar
  • Patent number: 6706646
    Abstract: A spin-on glass (SOG) composition and a method of forming a silicon oxide layer utilizing the SOG composition are disclosed. The method includes coating on a semiconductor substrate having a surface discontinuity, an SOG composition containing perhydropolysilazane having a compound of the formula —(SiH2NH)n— wherein n represents a positive integer, a weight average molecular weight within the range of about 4,000 to 8,000, and a molecular weight dispersion within the range of about 3.0 to 4.0, to form a planar SOG layer. The SOG layer is converted to a silicon oxide layer with a planar surface by curing the SOG layer. Also disclosed is a semiconductor device made by the method.
    Type: Grant
    Filed: October 12, 2000
    Date of Patent: March 16, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Ho Lee, Jung-Sik Choi, Hong-Ki Kim, Dong-Jun Lee, Dae-Won Kang, Sang-Mun Chon
  • Patent number: 6706648
    Abstract: In forming various types of insulating films in manufacture of a semiconductor device, carbon is gasified into CHx, COH etc. during film formation by adding active hydrogen and nitrogen oxide to reduce the carbon content during the film formation, and the effect of blocking impurities such as alkali metals is improved.
    Type: Grant
    Filed: October 24, 2001
    Date of Patent: March 16, 2004
    Assignee: Semiconductor Energy Laboratory Co., LTD
    Inventors: Shunpei Yamazaki, Mitsunori Sakama, Takeshi Fukada
  • Patent number: 6703324
    Abstract: A porous medium, such as a low dielectric constant film, can be made into an aggregate material to provide increased mechanical strength on a temporary basis. This can be achieved by, for example, a permeable modification treatment of the porous medium. By introduction of a secondary component into the void fraction of the porous medium, the mechanical properties are temporarily improved such that a porous film has mechanical characteristics similar to those of a much stiffer film. Methods in accordance with the present invention permit effective processing of highly porous interlayer dielectric (ILD) materials in a Cu damascene interconnect technology. Once a process operation such as a Cu chemical mechanical polishing (CMP) process, which requires greater mechanical strength than that provided by the porous film alone, is completed, the secondary component can be removed by methods such as displacement or dissolution.
    Type: Grant
    Filed: December 21, 2000
    Date of Patent: March 9, 2004
    Assignee: Intel Corporation
    Inventor: Lawrence D. Wong
  • Publication number: 20040033703
    Abstract: A method for forming an amino-free low k material. The method includes steps of introducing an amino-free gas into a chemical vapor deposition reactor; and decomposing the gas to form a layer of low k material. The amino-free gas is comprised of silane-based gas and CO2. O2 is also applicable as the process gas.
    Type: Application
    Filed: August 19, 2002
    Publication date: February 19, 2004
    Inventor: Shyh-Dar Lee
  • Publication number: 20040029402
    Abstract: A process for enhanced selective deposition of a silicon oxide onto a substrate by pulsing delivery of the reactants through a linear injector is disclosed. The silicon oxide layer is formed by the ozone decomposition of TEOS at relatively low temperatures and relatively high pressures. The ozone delivery is pulsed on and off. Optionally, the delivery of the ozone and the delivery of the TEOS are pulsed on and off alternately.
    Type: Application
    Filed: August 5, 2003
    Publication date: February 12, 2004
    Inventors: William Budge, Gurtej S. Sandhu, Christopher W. Hill
  • Patent number: 6689690
    Abstract: A method of manufacturing a semiconductor device is provided. The method including the steps of forming an insulating interlayer film on a substrate, forming a Cu interconnection pattern in the insulating interlayer film, forming a first insulating film on the insulating interlayer film at a first temperature lower than 400° C. in a nonoxide situation so that the first insulating film covers the Cu interconnection pattern, and forming a second insulating film on the first insulating film at a second temperature higher than the first temperature.
    Type: Grant
    Filed: January 28, 2002
    Date of Patent: February 10, 2004
    Assignee: Fujitsu Limited
    Inventor: Masanobu Ikeda
  • Publication number: 20040018717
    Abstract: An electrical interconnect structure on a substrate, includes a first porous dielectric layer with surface region from which a porogen has been removed; and an etch stop layer disposed upon the first porous dielectric layer so that the etch stop layer extends to partially fill pores in the surface region of the first porous dielectric layer from which the porogen has been removed, thus improving adhesion during subsequent processing. The porogen may be removed from the surface region by heating, and in particular by hot plate baking. A second porous dielectric layer, which may have the same composition as the first porous dielectric layer, may be formed over the etch stop layer. Electrical vias and lines may be formed in the first and second porous dielectric layer, respectively. The layers may be part of a multilayer stack, wherein all of the layers are cured simultaneously in a spin application tool porous dielectric layer.
    Type: Application
    Filed: June 23, 2003
    Publication date: January 29, 2004
    Applicant: International Business Machines Corporation
    Inventors: Ann R. Fornof, Jeffrey C. Hedrick, Kang-Wook Lee, Christy S. Tyberg
  • Patent number: 6677231
    Abstract: A first dielectric layer 310 is formed on a substrate, wherein the first dielectric layer is a low-K material of an organic polymer. An adhesion promoter is then deposited on the first dielectric layer by chemical vapor deposition to form a first interlayer, wherein the first adhesion promoter is an organic material that comprises a C—H group and a siloxane (Si—O), such as methyltriacetoxysilane (MTAS). Next, an inorganic layer is formed on the first interlayer. Then the adhesion promoter mentioned previously is deposited on the inorganic layer by chemical vapor deposition to form a second interlayer. Next, a second dielectric layer is formed on the second interlayer 340, wherein the second interlayer is a low-K material of an organic polymer. Finally, a baking process is performed.
    Type: Grant
    Filed: November 17, 2000
    Date of Patent: January 13, 2004
    Assignee: United Microelectronics Corp.
    Inventors: Cheng-Yuan Tsai, Chin-Hsiang Lin, Ming-Sheng Yang
  • Patent number: 6673725
    Abstract: The present invention relates to a semiconductor device manufacturing method for forming an interlayer insulating film having a low dielectric constant by coating a copper wiring. The low dielectric constant insulating film is formed by reaction of a plasma of a film-forming gas containing an oxygen-containing gas of N2O, H2O, or CO2, ammonia (NH3), and at least one of an alkyl compound having a siloxane bond and methylsilane (SiHn(CH3)4−n: n=0, 1, 2, 3).
    Type: Grant
    Filed: April 30, 2001
    Date of Patent: January 6, 2004
    Assignees: Canon Sales Co., Inc., Semiconductor Process Laboratory Co., Ltd.
    Inventors: Yoshimi Shioya, Kouichi Ohira, Kazuo Maeda
  • Patent number: 6670285
    Abstract: Dielectric compositions comprised of porous polymeric matrices are prepared using nitrogen-containing polymers as pore-generating agents. The compositions are useful in the manufacture of electronic devices such as integrated circuit devices and integrated circuit packaging devices. The dielectric compositions are prepared by admixing a polymeric nitrogenous porogen with a high temperature, thermosetting host polymer in a suitable solvent, heating the admixture to cure the polymer and provide a vitrified matrix, and then decomposing the porogen using heat, radiation, or a chemical reagent effective to degrade the porogen. The highly porous dielectric materials so prepared have an exceptionally low dielectric constant on the order of 2.5 or less, preferably less than about 2.0. Integrated circuit devices and integrated circuit packaging devices manufactured so as to contain the dielectric material of the invention are provided as well.
    Type: Grant
    Filed: March 14, 2001
    Date of Patent: December 30, 2003
    Assignee: International Business Machines Corporation
    Inventors: Craig Jon Hawker, James Lupton Hedrick, Elbert Emin Huang, Victor Yee-Way Lee, Teddie Magbitang, Robert Dennis Miller, Willi Volksen
  • Patent number: 6667147
    Abstract: Disclosed are methods of manufacturing electronic devices, particularly integrated circuits. Such methods include the use of low dielectric constant material prepared by using a removable porogen material.
    Type: Grant
    Filed: November 7, 2002
    Date of Patent: December 23, 2003
    Assignee: Shipley Company, L.L.C.
    Inventors: Michael K. Gallagher, Yujian You
  • Publication number: 20030232495
    Abstract: One embodiment of the present invention is a method for fabricating a low-k dielectric film that includes steps of: (a) chemical vapor depositing a lower-k dielectric film; and (b) e-beam treating the lower-k dielectric film.
    Type: Application
    Filed: May 1, 2003
    Publication date: December 18, 2003
    Inventors: Farhad Moghadam, Jun Zhao, Timothy Weidman, Rick J. Roberts, Li-Qun Xia, Alexandros T. Demos
  • Patent number: 6664201
    Abstract: An anti-reflection layer and method of manufacture. A silicon substrate has a conductive layer formed thereon. Plasma-enhanced chemical vapor deposition is performed to form a graded silicon oxynitride layer over the conductive layer. During silicon oxynitride deposition, concentration of one of the reactive gases nitrous oxide is gradually reduced so that the graded silicon oxynitride layer is oxygen-rich near bottom but nitrogen-rich near the top.
    Type: Grant
    Filed: December 5, 2001
    Date of Patent: December 16, 2003
    Assignee: United Microelectronics Corp.
    Inventors: Jing-Horng Gau, Shuenn-Jeng Chen
  • Patent number: 6664199
    Abstract: A coating liquid for forming a silica group coating film having a dielectric constant equal to or less than 3.2, comprises a condensation product which is obtained through hydrolysis of trialkoxysilane within an organic solvent under an acid catalysis; and at least one of polyalkylene glycol and the end alkylation product thereof. The addition amount of the at least one of polyalkylene glycol and the end alkylation product thereof is 10-500 weight % with respect to the solid component of the coating liquid, and the weight-average molecular weight of the polyalkylene glycol and the end alkylation product thereof is 100-10,000.
    Type: Grant
    Filed: August 12, 2002
    Date of Patent: December 16, 2003
    Assignee: Tokyo Ohka Kogyo Co., Ltd.
    Inventors: Yasushi Fujii, Atsushi Matsushita
  • Patent number: 6660663
    Abstract: A method and apparatus for depositing a low dielectric constant film by reaction of an organosilane or organosiloxane compound and an oxidizing gas at a low RF power level from 10-250 W. The oxidized organosilane or organosiloxane film has good barrier properties for use as a liner or cap layer adjacent other dielectric layers. The oxidized organosilane or organosiloxane film may also be used as an etch stop or an intermetal dielectric layer for fabricating dual damascene structures. The oxidized organosilane or organosiloxane films also provide excellent adhesion between different dielectric layers. A preferred oxidized organosilane film is produced by reaction of methylsilane, CH3SiH3, or dimethylsilane, (CH3)2SiH2, and nitrous oxide, N2O, at an RF power level from about 10 to 200 W or a pulsed RF power level from about 20 to 250 W during 10-30% of the duty cycle.
    Type: Grant
    Filed: May 25, 2000
    Date of Patent: December 9, 2003
    Assignee: Applied Materials Inc.
    Inventors: David Cheung, Wai-Fan Yau, Robert R. Mandal
  • Patent number: 6656854
    Abstract: In a method for manufacturing a semiconductor device, a semiconductor substrate is provided. On the substrate, conductors spaced apart from one another are formed. Then, an insulating layer is formed on the conductors and the substrate. The insulating layer is formed by a chemical vapor deposition using tetramethylcyclotetrasiloxane as a source gas and oxygen as an adjunction gas. The chemical vapor deposition is performed while the substrate is irradiated by vacuum ultraviolet light. Finally, a part of the insulating layer is removed in a substantial uniform way to form a contact hole through the insulating film.
    Type: Grant
    Filed: January 23, 2002
    Date of Patent: December 2, 2003
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Junichi Miyano, Kiyohiko Toshikawa, Yoshikazu Motoyama
  • Patent number: 6656284
    Abstract: Disclosed is a semiconductor device manufacturing apparatus provided with a rotational gas injector for supplying source gases at an upper portion of a reaction chamber. According to the invention, source gases are injected from the upside of the wafers through the rotational type gas injector, and non-reacted gases are exhausted into the downside space of the wafers, so that lowering in the thickness uniformity of a thin film due to the horizontal flow of source gases provided in the conventional art decrease remarkably. Accordingly, although multiple wafers are loaded in a single reaction chamber, a thin film having very high thickness uniformity can be deposited with respect to all the wafers, thereby capable of enhancing the productivity.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: December 2, 2003
    Assignee: Jusung Engineering Co., Ltd.
    Inventors: Chul Ju Hwang, Kyung Sik Shim, Chang Soo Park
  • Patent number: 6653719
    Abstract: A siloxan polymer insulation film has a dielectric constant of 3.3 or lower and has —SiR2O— repeating structural units. The siloxan polymer has dielectric constant, high thermal stability and high humidity-resistance on a semiconductor substrate. The siloxan polymer is formed by directly vaporizing a silicon-containing hydrocarbon compound expressed by the general formula Si&agr;O&bgr;CxHy (&agr;, &bgr;, x, and y are integers) and then introducing the vaporized compound to the reaction chamber of the plasma CVD apparatus. The residence time of the source gas is lengthened by reducing the total flow of the reaction gas, in such a way as to form a siloxan polymer film having a micropore porous structure with low dielectric constant.
    Type: Grant
    Filed: September 24, 2002
    Date of Patent: November 25, 2003
    Assignee: ASM Japan K.K.
    Inventor: Nobuo Matsuki