Organic Reactant Patents (Class 438/790)
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Patent number: 6649219Abstract: The invention provides a process for forming a low k fluorine and carbon-containing silicon oxide dielectric material by reacting with an oxidizing agent one or more silanes containing one or more organofluoro silanes having the formula SiR1R2R3R4, where: (a) R1 is selected from H, a 3 to 10 carbon alkyl, and an alkoxy; (b) R2 contains at least one C atom bonded to at least one F atom, and no aliphatic C—H bonds; and (c) R3 and R4 are selected from H, alkyl, alkoxy, a moiety containing at least one C atom bonded to at least one F atom, and ((L)Si(R5)(R6))n(R7); where n ranges from 1 to 10; L is O or CFR8; each n R5 and R6 is selected from H, alkyl, alkoxy, and a moiety containing at least one C atom bonded to at least one F atom; R7 is selected from H, alkyl, alkoxy, and a moiety containing at least one C atom bonded to at least one F atom; and each R8 is selected from H, alkyl, alkoxy, and a moiety containing at least one C atom bonded to at least one F atom.Type: GrantFiled: February 23, 2001Date of Patent: November 18, 2003Assignee: LSI Logic CorporationInventors: Sheldon Aronowitz, Vladimir Zubkov
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Patent number: 6642142Abstract: In a water rinsing process performed after the surface of a substrate has been cleaned using a cleaning solution, a first spinning process, in which water is supplied to the surface of the substrate while the substrate is rotated at a first rotation speed, and a second spinning process, in which the substrate is rotated at a second rotation speed that is higher than the first rotation speed, are repeatedly performed alternately.Type: GrantFiled: January 3, 2002Date of Patent: November 4, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toshihiko Nagai, Hiroshi Tanaka, Naoki Yokoi, Yasuhiro Asaoka, Seiji Muranaka
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Publication number: 20030203655Abstract: A material containing, as a main component, an organic silicon compound represented by the following general formula:Type: ApplicationFiled: March 28, 2003Publication date: October 30, 2003Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Gaku Sugahara, Nobuo Aoi, Koji Arai, Kazuyuki Sawada
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Publication number: 20030203652Abstract: A method for forming a dielectric insulating layer with a reduced dielectric constant and increased hardness for semiconductor device manufacturing including providing a semiconductor wafer having a process surface for forming a dielectric insulting layer thereover; depositing according to a CVD process a carbon doped oxide layer the CVD process including an organo-silane precursor having Si—O groups and Si—Ry groups, where R is an alkyl or cyclo-alkyl group and y the number of R groups bonded to Si; and, exposing the carbon doped oxide layer to a hydrogen plasma treatment for a period of time thereby reducing the carbon doped oxide layer thickness including reducing the carbon doped oxide layer dielectric constant and increasing the carbon doped oxide layer hardness.Type: ApplicationFiled: April 25, 2002Publication date: October 30, 2003Inventors: Tien-I Bao, Chung-Chi Ko, Lih-Ping Li, Syun-Ming Jang
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Publication number: 20030203654Abstract: A method for depositing highly conformal silicate glass layers via chemical vapor deposition through the reaction of TEOS and O3 comprises placing an in-process semiconductor wafer having multiple surface constituents in a plasma-enhanced chemical vapor deposition chamber.Type: ApplicationFiled: June 9, 2003Publication date: October 30, 2003Inventor: Ravi Iyer
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Patent number: 6632478Abstract: An embodiment of the present invention provides methods for forming a carbon-containing layer having a low dielectric constant and good gap-fill capabilities. A method includes depositing a carbon-containing layer on a substrate and transforming the carbon-containing layer to remove at least some of the carbon. The transforming step may include annealing the carbon-containing layer in a furnace containing a hydrogen atmosphere, for example. The carbon-containing layer may be a carbon-doped silicon oxide material, where the transforming step changes the carbon-doped silicon oxide. Additionally, the method may include subjecting the annealed layer to a hydrogen and/or low oxygen plasma treatment to further remove carbon from the layer. Additionally, a step of adding a capping layer to the annealed, plasma treated material is provided.Type: GrantFiled: February 22, 2001Date of Patent: October 14, 2003Assignee: Applied Materials, Inc.Inventors: Frederic Gaillard, Li-Qun Xia, Jen Shu, Ellie Yieh, Tian-Hoe Lim
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Publication number: 20030190821Abstract: The present invention discloses a method for forming a layer of nitrogen and silicon containing material on a substrate by first providing a heated substrate and then flowing a gas which has silicon and nitrogen atoms but no carbon atoms in the same molecule over said heated substrate at a pressure of not higher than 500 Torr, such that a layer of nitrogen and silicon containing material is formed on the surface. The present invention is further directed to a composite structure that includes a substrate and a layer of material containing nitrogen and silicon but not carbon overlying the substrate for stopping chemical species from reaching the substrate. The present invention is further directed to a structure that includes a semiconducting substrate, a gate insulator on the substrate, a nitrogen-rich layer on top of the gate insulator, and a gate electrode on the nitrogen-rich layer, wherein the nitrogen-rich layer blocks diffusion of contaminating species from the gate electrode to the gate insulator.Type: ApplicationFiled: May 2, 2003Publication date: October 9, 2003Applicant: International Business Machines CorporationInventors: Douglas Andrew Buchanan, Matthew Warren Copel, Fenton Read McFeely, Patrick Ronald Varekamp, Mark Monroe Banaszak Holl, Kyle Erik Litz
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Patent number: 6630413Abstract: Low hydrogen-content silicon nitride materials are deposited by a variety of CVD techniques, preferably thermal CVD and PECVD, using chemical precursors that contain silicon atoms, nitrogen atoms, or both. A preferred chemical precursor contains one or more N—Si bonds. Another preferred chemical precursor is a mixture of a N-containing chemical precursor with a Si-containing chemical precursor that contains less than 9.5 weight % hydrogen atoms. A preferred embodiment uses a hydrogen source to minimize the halogen content of silicon nitride materials deposited by PECVD.Type: GrantFiled: April 26, 2001Date of Patent: October 7, 2003Assignee: ASM Japan K.K.Inventor: Michael A. Todd
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Patent number: 6627559Abstract: The present invention provides a coating film, which is not likely to cause cracks on the coated surface and is also capable of improving the resistance of the coated surface, especially oxidation resistance, corrosion resistance, and gas permeation resistance, a member provided with the coating film, and a method for producing the coating film. In the coating film of the present invention, a dense layer containing silicon dioxide as a principal component, which is obtained by heat-treating a solution containing perhydropolysilazane and polyorganosilazane, a ratio of the content of perhydropolysilazane to the total amount of polysilazane including perhydropolysilazane and polyorganosilazane being from 0.65 to 0.95, in air or air containing water vapor, was formed on the surface of a stainless steel plate.Type: GrantFiled: July 23, 2001Date of Patent: September 30, 2003Assignee: Contamination Control ServicesInventor: Toyohiko Shindo
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Patent number: 6627533Abstract: A method of manufacturing an insulating film in a semiconductor device is disclosed. The method comprises the steps of forming a SOD film on the entire structure to fill any distance between conductive layer patterns and after performing a curing process, forming a hard mask film on the SOD film, wherein the silicon oxide film is deposited by plasma deposition method using SiH4 and N2O as a reaction gas at a low-temperature and at a low-pressure and wherein in a stabilization step, the supply amount of SiH4 is greater than that of N2O and in a deposition step, the supply amount of N2O is greater than that of SiH4.Type: GrantFiled: June 13, 2001Date of Patent: September 30, 2003Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Sang Tae Ahn, Jung Gyu Song
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Patent number: 6624088Abstract: A method of depositing a silicon oxynitride spacer film on a gate stack in a semiconductor device involves contacting the gate stack with bistertiarybutylaminosilane (BTBAS), at least one nitrogen containing compound and oxygen (O2). The deposition is controlled to provide a wet etch rate for the deposited spacer film that is within the range of about 25 Angstroms per minute to less than or equal to about 1 Angstrom.Type: GrantFiled: April 10, 2002Date of Patent: September 23, 2003Assignee: Micron Technology, Inc.Inventor: John T. Moore
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Patent number: 6620741Abstract: A method for controlling etch bias of carbon doped oxide films comprising performing the etch in a cyclic two step process i.e., a carbon doped oxide (CDO) removal process, said CDO removal process comprises a first gas to etch a trench in the CDO layer. The CDO removal process is followed by a polymer deposition process. The polymer deposition process comprises introducing a second gas in the reactor to deposit a polymer in the trench of the CDO layer. The first gas comprises a first molecule having a first ratio of carbon atoms to fluorine atoms, and the second gas comprises a second molecule having a second ratio of carbon atoms to fluorine atoms, such that the second ratio of carbon atoms to fluorine atoms is greater than the first ratio of carbon atoms to fluorine atoms. The above process may be repeated to etch the final structure.Type: GrantFiled: June 10, 2002Date of Patent: September 16, 2003Assignee: Intel CorporationInventors: David H. Gracias, Hyun-Mog Park, Vijayakumar S. Ramachandrarao
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Publication number: 20030166342Abstract: Disclosed herein is a method of improving the adhesion of a hydrophobic self-assembled monolayer (SAM) coating to a surface of a MEMS structure, for the purpose of preventing stiction. The method comprises pretreating surfaces of the MEMS structure with a plasma generated from a source gas comprising oxygen and, optionally, hydrogen. The treatment oxidizes the surfaces, which are then reacted with hydrogen to form bonded OH groups on the surfaces. The hydrogen source may be present as part of the plasma source gas, so that the bonded OH groups are created during treatment of the surfaces with the plasma. Also disclosed herein is an integrated method for release and passivation of MEMS structures.Type: ApplicationFiled: November 20, 2002Publication date: September 4, 2003Applicant: APPLIED MATERIALS, INC.Inventors: Jeffrey D. Chinn, Rolf A. Guenther, Michael B. Rattner, James A. Cooper, Toi Yue Becky Leung
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Patent number: 6613697Abstract: Disclosed is a method for making low metallic impurity SiO-based dielectric thin films on semiconductor substrates using a room temperature wet chemical growth (RTWCG) process for electronic and photonic (optoelectronic) device applications. The process comprises soaking the semiconductor substrate into the growth solution. The process utilizes a mixture of aqueous inorganic or organic based silicon source solution, an inorganic reduction oxidation (redox) aqueous solution, non-invasive inorganic or organic based liquid additives for adjusting the growth rate and reducing the metallic impurity concentration within the SiO-based film, with or without an electron exchange pyridine based component, and an inorganic homogeneous catalyst for enhancing the growth of the SiO-based film.Type: GrantFiled: June 26, 2001Date of Patent: September 2, 2003Assignee: Special Materials Research and Technology, Inc.Inventors: Maria Faur, Horia M. Faur, Mircea Faur
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Patent number: 6596654Abstract: Chemical vapor deposition processes are employed to fill high aspect ratio (typically at least 3:1), narrow width (typically 1.5 microns or less and even sub 0.15 micron) gaps with significantly reduced incidence of voids or weak spots. This deposition process involves the use of hydrogen as a process gas in the reactive mixture of a plasma containing CVD reactor. The process gas also includes dielectric forming precursor molecules such as silicon and oxygen containing molecules.Type: GrantFiled: November 28, 2001Date of Patent: July 22, 2003Assignee: Novellus Systems, Inc.Inventors: Atiye Bayman, Md Sazzadur Rahman, Weijie Zhang, Bart van Schravendijk, Vishal Gauri, George D. Papasoulitotis, Vikram Singh
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Patent number: 6596627Abstract: The present invention provides a method for depositing nano-porous low dielectric constant films by reacting an oxidizable silicon containing compound or mixture comprising an oxidizable silicon component and an oxidizable non-silicon component having thermally liable groups with nitrous oxide, oxygen, ozone, or other source of reactive oxygen in gas-phase plasma-enhanced reaction. The deposited silicon oxide based film is annealed to form dispersed microscopic voids that remain in a nano-porous silicon oxide based film having a low-density structure. The nano-porous silicon oxide based films are useful for forming layers between metal lines with or without liner or cap layers. The nano-porous silicon oxide based films may also be used as an intermetal dielectric layer for fabricating dual damascene structures.Type: GrantFiled: June 28, 2002Date of Patent: July 22, 2003Assignee: Applied Materials Inc.Inventor: Robert P. Mandal
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Patent number: 6596467Abstract: Disclosed are methods of manufacturing electronic devices, particularly integrated circuits. Such methods include the use of low dielectric constant material prepared by using a removable porogen material.Type: GrantFiled: September 8, 2001Date of Patent: July 22, 2003Assignee: Shipley Company, L.L.C.Inventors: Michael K. Gallagher, Yujian You
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Patent number: 6596655Abstract: A method and apparatus for depositing a low dielectric constant film by reaction of an organosilicon compound and an oxidizing gas at a constant RF power level from about 10W to about 200W or a pulsed RF power level from about 20W to about 500W. Dissociation of the oxidizing gas can be increased prior to mixing with the organosilicon compound, preferably within a separate microwave chamber, to assist in controlling the carbon content of the deposited film. The oxidized organosilane or organosiloxane film has good barrier properties for use as a liner or cap layer adjacent other dielectric layers. The oxidized organosilane or organosiloxane film may also be used as an etch stop and an intermetal dielectric layer for fabricating dual damascene structures. The oxidized organosilane or organosiloxane films also provide excellent adhesion between different dielectric layers.Type: GrantFiled: September 19, 2001Date of Patent: July 22, 2003Assignee: Applied Materials Inc.Inventors: David Cheung, Wai-Fan Yau, Robert P. Mandal, Shin-Puu Jeng, Kuo-Wei Liu, Yung-Cheng Lu, Michael Barnes, Ralf B. Willecke, Farhad Moghadam, Tetsuya Ishikawa, Tze Wing Poon
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Patent number: 6593250Abstract: In a semiconductor device fabrication method, a first low dielectric constant film having a specific dielectric constant of k less than 3 (k<3) is formed over a wafer so that an edge position of the first low dielectric constant film aligns with a first position along the circumference of the wafer. Then, a first protection layer having a gas permeability lower than that of the first low dielectric constant film is formed over the first low dielectric constant film and the wafer so that an edge of the first protection layer aligns with a second position that is located outside the first position. Then, a second low dielectric constant film having a specific dielectric constant of k less than 3 (k<3) is formed over the first protection layer so that an edge of the second low dielectric constant film is located at the first position.Type: GrantFiled: March 19, 2002Date of Patent: July 15, 2003Assignee: Kabushiki Kaisha ToshibaInventor: Kazuyuki Higashi
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Patent number: 6589889Abstract: A process for forming a substantially planarized nanoporous dielectric silica coating on a substrate suitable for preparing a semiconductor device, and semiconductor devices produced by the methods of the invention. The process includes the steps of applying a composition that includes at least one silicon-based dielectric precursor to a substrate, and then, (a) gelling or aging the applied coating, (b) contacting the coating with a planarization object with sufficient pressure to transfer a planar impression to the coating without substantially impairing formation of desired nanometer-scale pore structure, (c) separating the planarized coating from the planarization object, (d) curing said planarized coating; wherein steps (a)-(d) are conducted in any one of the following sequences: (a), (b), (c) and (d); (a), (d), (b) and (c); (b), (a), (d) and (c); and (b), (c), (a) and (d).Type: GrantFiled: September 9, 1999Date of Patent: July 8, 2003Assignee: AlliedSignal Inc.Inventors: Denis H. Endisch, James S. Drage
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Patent number: 6586345Abstract: In forming a conduction film in a semiconductor device, after an uneven natural oxide film on a silicon film has been once removed, an even and clean silicon oxide film is formed by an oxidizing chemical solution treatment. After that, a silicide film is formed, thus forming a stable conduction film consisting of a two-layered structure of a polysilicon/silicide film.Type: GrantFiled: August 13, 1998Date of Patent: July 1, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Toshiaki Ohmori
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Patent number: 6583070Abstract: A semiconductor device having a reduced resistance-capacitance time constant is formed by treating a dielectric layer to reduce its dielectric constant. Embodiments include exposing a deposited dielectric layer to ionic radiation, as with Helium ion implantation, to form voids within the layer, thereby reducing its dielectric constant.Type: GrantFiled: February 8, 2001Date of Patent: June 24, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Ting Y. Tsui, Ercan Adem
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Patent number: 6579808Abstract: A method for fabricating a semiconductor device capable of maintaining contact hole of fine size when the contact hole for bit line formation is defined.Type: GrantFiled: February 5, 2002Date of Patent: June 17, 2003Assignee: Hynix Semiconductor Inc.Inventors: Sung Yoon Cho, Jae Heon Kim
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Patent number: 6576569Abstract: This invention includes: a plasma-making step of making into plasma a film-forming gas including a compound of carbon and fluorine and an etching gas which can etch a film of fluorine-added carbon; and a film-forming step of forming a film of fluorine-added carbon onto an object to be processed by means of the plasma made in the plasma-making step. For example, the film-forming gas including a compound of carbon and fluorine includes a gas of a compound having a benzene ring. For example, the etching gas which can etch a film of fluorine-added carbon is a gas including fluorine. According to the invention, a concave portion can be satisfactory filled up with the CF film.Type: GrantFiled: September 7, 2000Date of Patent: June 10, 2003Assignee: Tokyo Electron LimitedInventor: Noriaki Fukiage
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Patent number: 6576528Abstract: Disclosed are a capacitor for semiconductor devices capable of increasing storage capacitance and preventing leakage current, and method of manufacturing the same. The capacitor for semiconductor memory devices according to the present invention includes: a lower electrode; a dielectric layer formed on the lower electrode; and an upper electrode formed on the upper portion of the dielectric layer, wherein the dielectric layer is a crystalline TaxOyNz layer, and the total of x, y, and z in the crystalline TaxOyNz layer is 1, and y is 0.3 to 0.5, and z is 0.1 to 0.3.Type: GrantFiled: June 28, 2000Date of Patent: June 10, 2003Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Kee Jeung Lee, Dong Jun Kim
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Patent number: 6576570Abstract: A method for depositing highly conformal silicate glass layers via chemical vapor deposition through the reaction of TEOS and O3 comprises placing an in-process semiconductor wafer having multiple surface constituents in a plasma-enhanced chemical vapor deposition chamber.Type: GrantFiled: July 22, 2002Date of Patent: June 10, 2003Assignee: Micron Technology, Inc.Inventor: Ravi Iyer
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Patent number: 6573196Abstract: A method of forming an organosilicate layer is disclosed. The organosilicate layer is formed by applying an electric field to a gas mixture comprising a phenyl-based silane compound. The gas mixture may optionally include an oxidizing gas. The organosilicate layer is compatible with integrated circuit fabrication processes. In one integrated circuit fabrication process, the organosilicate layer is used as an anti-reflective coating (ARC). In another integrated circuit fabrication process, the organosilicate layer is incorporated into a damascene structure.Type: GrantFiled: August 12, 2000Date of Patent: June 3, 2003Assignee: Applied Materials Inc.Inventors: Frederick Gaillard, Li-Qun Xia, Tian-Hoe Lim, Ellie Yieh
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Patent number: 6566278Abstract: Carbon-doped silicon oxide films (SiCxOy) produced by CVD of an organosilane gas containing at least one silicon carbon bond, are rapidly densified by exposure to ultraviolet radiation. UV radiation exposure disrupts undesirable chemical bonds (such as Si—OH) present in the carbon-doped silicon oxide following deposition, replacing these bonds with more desirable chemical bonds characteristic of an ordered silicon oxide lattice. As a result of radiation exposure and the chemical bond replacement, gases such as water vapor are evolved and removed, producing a densified and stable carbon-doped silicon oxide film. Densification utilizing ultraviolet radiation is particularly useful because softness and fragility of freshly-deposited (SiCxOy) films may preclude insertion and removal of coated substrates from conventional batch loaded thermal annealing chambers.Type: GrantFiled: August 24, 2000Date of Patent: May 20, 2003Assignee: Applied Materials Inc.Inventors: Keith R. Harvey, Tian-Hoe Lim, Li-Qun Xia
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Patent number: 6562732Abstract: The invention relates to a method of manufacturing a semiconductor device, comprising the provision of a dual damascene structure (20). This dual damascene structure (20) comprises a metal layer (1) with thereon a first dielectric layer (2) provided with a via (3). A second dielectric layer (5) is applied on the first dielectric layer (2) and is provided with an interconnect groove (6). The via (3) and the interconnect groove (6) are filled with a metal which forms a metal lead (9) with a top (10). The method further comprises the following steps: removing the second dielectric layer (5), applying a disposable layer (12) to the first dielectric layer (2) and the metal lead (9), planarizing the disposable layer (12) down to the top (10) of the metal lead (9), applying a porous dielectric layer (13) on the disposable layer (12), removing the disposable layer (12) through the porous dielectric layer (13) so as to form air gaps (14).Type: GrantFiled: August 30, 2001Date of Patent: May 13, 2003Assignee: Koninklijke Philips Electronics N.V.Inventors: Willem Frederik Adrianus Besling, Cornelis Adrianus Henricus Antonius Mutsaers, Dirk Jan Gravesteijn
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Patent number: 6562735Abstract: Control of a reaction between a peroxide oxidizing agent and a carbon-substituted silane to form a low k carbon-containing silicon oxide dielectric material is achieved, in a first embodiment, by adding, to the carbon-substituted silane reactant, silane (SiH4), to accelerate the process for forming a low k carbon-containing silicon oxide dielectric material by reaction of the carbon-substituted silane/silane mixture with hydrogen peroxide. Also, control of a reaction between a peroxide oxidizing agent and a carbon-substituted silane to form a low k carbon-containing silicon oxide dielectric material is achieved by controlling the ratio of the flow of the hydrogen peroxide reactant and the flow of the reactant mixture of carbon-substituted silane and unsubstituted silane into the reaction chamber though structural modification of the faceplate (showerhead) through which the reactants flow into the chamber.Type: GrantFiled: December 11, 2001Date of Patent: May 13, 2003Assignee: LSI Logic CorporationInventors: Derryl D. J. Allman, Ponce Saopraseuth
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Patent number: 6559071Abstract: A process for forming a nanoporous silica dielectric coating on a substrate. A substrate containing a deposited film is suspended within a sealable hotplate, while remaining free of contact with the hotplate. The hotplate is sealed and an inert gas is flowed across the substrate. The hotplate is heated to a temperature of from about 350° C. or higher, and the substrate is forced to contact the heated hotplate. The substrate is heated for a time that sufficiently removes outgassing remnants from the resultant nanoporous dielectric coating.Type: GrantFiled: October 26, 2001Date of Patent: May 6, 2003Assignee: AlliedSignal Inc.Inventors: Teresa Ramos, Douglas M. Smith, James Drage, Rick Roberts
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Patent number: 6559520Abstract: A siloxan polymer insulation film has a dielectric constant of 3.1 or lower and has —SiR2O— repeating structural units with a C atom concentration of 20% or less. The siloxan polymer also has high thermal stability and high humidity-resistance. The siloxan polymer is formed by directly vaporizing a silicon-containing hydrocarbon compound of the formula Si&agr;O&agr;−1R2&agr;−&bgr;+2(OCnH2n+1)&bgr; wherein &agr; is an integer of 1-3, &bgr; is 2, n is an integer of 1-3, and R is C1-6 hydrocarbon attached to Si, and then introducing the vaporized compound with an oxidizing agent to the reaction chamber of the plasma CVD apparatus. The residence time of the source gas is lengthened by reducing the total flow of the reaction gas, in such a way as to form a siloxan polymer film having a micropore porous structure with low dielectric constant.Type: GrantFiled: April 25, 2002Date of Patent: May 6, 2003Assignee: ASM Japan K.K.Inventors: Nobuo Matsuki, Lee Jea Sik, Yoshinori Morisada, Satoshi Takahashi
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Publication number: 20030077921Abstract: Carbon doped oxide (CDO) deposition. One method of deposition includes providing a substrate and introducing oxygen to a carbon doped oxide precursor in the presence of the substrate. A carbon doped oxide film is formed on the substrate. In another method the substrate is placed on a susceptor of a chemical vapor deposition apparatus. A background gas is introduced along with the carbon doped oxide precursor and oxygen to form the carbon doped oxide film on the substrate.Type: ApplicationFiled: October 5, 2001Publication date: April 24, 2003Inventors: Ebrahim Andideh, Kevin L. Peterson, Jeffery D. Bielefeld
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Publication number: 20030064610Abstract: A method and apparatus for depositing a low dielectric constant film by reaction of an organosilicon compound and an oxidizing gas comprising carbon at a constant RF power level. Dissociation of the oxidizing gas can be increased prior to mixing with the organosilicon compound, preferably within a separate microwave chamber, to assist in controlling the carbon content of the deposited film. The oxidized organosilane or organosiloxane film has good barrier properties for use as a liner or cap layer adjacent other dielectric layers. The oxidized organosilane or organosiloxane film may also be used as an etch stop and an intermetal dielectric layer for fabricating dual damascene structures. The oxidized organosilane or organosiloxane films also provide excellent adhesion between different dielectric layers.Type: ApplicationFiled: August 27, 2002Publication date: April 3, 2003Applicant: Applied Materials, Inc.Inventors: David Cheung, Wai-Fan Yau, Robert P. Mandal, Shin-Puu Jeng, Kuo-Wei Liu, Yung-Cheng Lu, Michael Barnes, Ralf B. Willecke, Farhad Moghadam, Tetsuya Ishikawa, Tze Wing Poon
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Patent number: 6541367Abstract: The present invention provides a method for depositing nano-porous low dielectric constant films by reacting an oxidizable silicon containing compound or mixture comprising an oxidizable silicon component and an oxidizable non-silicon component having thermally labile groups with nitrous oxide, oxygen, ozone, or other source of reactive oxygen in gas-phase plasma-enhanced reaction. The deposited silicon oxide based film is annealed to form dispersed microscopic voids that remain in a nano-porous silicon oxide based film having a low-density structure. The nano-porous silicon oxide based films are useful for forming layers between metal lines with or without liner or cap layers. The nano-porous silicon oxide based films may also be used as an intermetal dielectric layer for fabricating dual damascene structures.Type: GrantFiled: January 18, 2000Date of Patent: April 1, 2003Assignee: Applied Materials, Inc.Inventor: Robert P. Mandal
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Patent number: 6541397Abstract: A method is provided for processing a substrate including removing amorphous carbon material disposed on a low k dielectric material with minimal or reduced defect formation and minimal dielectric constant change of the low k dielectric material. In one aspect, the invention provides a method for processing a substrate including depositing at least one dielectric layer on a substrate surface, wherein the dielectric layer comprises silicon, oxygen, and carbon and has a dielectric constant of about 3 or less, forming amorphous carbon material on the at least one dielectric layer, and removing the one or more amorphous carbon layers by exposing the one or more amorphous carbon layers to a plasma of a hydrogen-containing gas.Type: GrantFiled: March 29, 2002Date of Patent: April 1, 2003Assignee: Applied Materials, Inc.Inventor: Christopher Dennis Bencher
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Patent number: 6537929Abstract: A method and apparatus for depositing a low dielectric constant film by reaction of an organosilane or organosiloxane compound and an oxidizing gas at a low RF power level from 10-250 W. The oxidized organosilane or organosiloxane film has good barrier properties for use as a liner or cap layer adjacent other dielectric layers. The oxidized organosilane or organosiloxane film may also be used as an etch stop or an intermetal dielectric layer for fabricating dual damascene structures. The oxidized organosilane or organosiloxane films also provide excellent adhesion between different dielectric layers. A preferred oxidized organosilane film is produced by reaction of methylsilane, CH3SiH3, or dimethylsilane, (CH3)2SiH2, and nitrous oxide, N2O, at an RF power level from about 10 to 200 W or a pulsed RF power level from about 20 to 250 W during 10-30% of the duty cycle.Type: GrantFiled: May 25, 2000Date of Patent: March 25, 2003Assignee: Applied Materials, Inc.Inventors: David Cheung, Wai-Fan Yau, Robert R. Mandal
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Publication number: 20030040196Abstract: The present invention relates to a method of forming an insulating film in a semiconductor device by which the composition and the doping concentration of oxide are controlled using an atomic layer deposition method. In case of silicon oxide, a thermal oxidization process and a deposition process are sequentially performed to form an oxide film having a good interface characteristic and the deposition speed. On the other hand, in case of depositing an oxide film, an oxynitride film and a metal oxide film, the pulse construction and the supply time of a source and radical are adjusted to form an optimum oxide film having a good interface characteristic.Type: ApplicationFiled: October 29, 2001Publication date: February 27, 2003Inventors: Jung Wook Lim, Young Joo Song, Kyu Hwan Shim, Jin Yeong Kang
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Publication number: 20030040194Abstract: A spin-on glass (SOG) composition and a method of forming a silicon oxide layer utilizing the SOG composition are disclosed. The method includes coating on a semiconductor substrate having a surface discontinuity, an SOG composition containing perhydropolysilazane having a compound of the formula —(SiH2NH)n— wherein n represents a positive integer, a weight average molecular weight within the range of about 4,000 to 8,000, and a molecular weight dispersion within the range of about 3.0 to 4.0, to form a planar SOG layer. The SOG layer is converted to a silicon oxide layer with a planar surface by curing the SOG layer. Also disclosed is a semiconductor device made by the method.Type: ApplicationFiled: October 24, 2002Publication date: February 27, 2003Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-Ho Lee, Jung-Sik Choi, Hong-Ki Kim, Dong-Jun Lee, Dae-Won Kang, Sang-Mun Chon
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Patent number: 6524972Abstract: A method for forming an interlayer insulating film is disclosed. This method comprises the steps of: forming an underlying insulating film on an object to be formed; and forming a porous SiO2 film on said underlying insulating film by a Chemical Vapor Deposition that employs a source gas containing TEOS (tetraethoxy silane) and O3 where the O3 is contained in the source gas with first concentration that is lower than concentration necessary for oxidizing the TEOS. Alternative method for forming an interlayer insulating film is also disclosed. This method comprises the step of: forming an underlying insulating film on an object to be formed; performing Cl (chlorine) plasma treatment for the underlying insulating film; and forming a porous SiO2 film on the underlying insulating film by a Chemical Vapor Deposition that employs a source gas containing TEOS (tetraethoxy silane) and O3.Type: GrantFiled: March 9, 2000Date of Patent: February 25, 2003Assignees: Canon Sales Co., Inc., Semiconductor Process Laboratory Co., Ltd.Inventor: Kazuo Maeda
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Patent number: 6524974Abstract: An improvement in the formation of low dielectric constant carbon-containing silicon oxide dielectric material by reacting a carbon-substituted silane with an oxidizing agent is described, wherein the process is carried out in the presence of a reaction retardant. The reaction retardant reduces the sensitivity of the reaction to changes in pressure, temperature, and flow rates, and reduces the problem of pressure spiking, resulting in the formation of a deposited film of more uniform thickness across the substrate as well as a film with a smooth surface, and a reduction of the amount of carbon lost during the reaction.Type: GrantFiled: March 22, 1999Date of Patent: February 25, 2003Assignee: LSI Logic CorporationInventor: Valeriy Sukharev
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Patent number: 6521546Abstract: A method of forming an integrated circuit using a fluoro-organosilicate layer is disclosed. The fluoro-organosilicate layer is formed by applying an electric field to a gas mixture comprising a fluoro-organosilane compound and an oxidizing gas. The fluoro-organosilicate layer is compatible with integrated circuit fabrication processes. In one integrated circuit fabrication process, the fluoro-organosilicate layer is used as a hardmask. In another integrated circuit fabrication process, the fluoro-organosilicate layer is incorporated into a damascene structure.Type: GrantFiled: June 14, 2000Date of Patent: February 18, 2003Assignee: Applied Materials, Inc.Inventors: Michael Barnes, Hichem M'Saad, Huong Thanh Nguyen, Farhad Moghadam
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Publication number: 20030032305Abstract: A method of forming a carbon-doped silicon oxide layer is disclosed. The carbon-doped silicon oxide layer is formed by applying an electric field to a gas mixture comprising an organosilane compound and an oxidizing gas. The carbon-doped silicon oxide layer is compatible with integrated circuit fabrication processes. In one integrated circuit fabrication process, the carbon-doped silicon oxide layer is used as an intermetal dielectric layer. In another integrated circuit fabrication process, the carbon-doped silicon oxide layer is incorporated into a damascene structure.Type: ApplicationFiled: August 7, 2001Publication date: February 13, 2003Applicant: Applied Materials, Inc.Inventors: Wai-Fan Yau, Ju-Hyung Lee, Nasreen Gazala Chopra, Tzu-Fang Huang, David Cheung, Farhad Moghadam, Kuo-Wei Liu, Yung-Cheng Lu, Ralf B. Willecke, Paul Matthews, Dian Sugiarto
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Publication number: 20030031789Abstract: The present invention provides an organosiloxane comprising at least 80 weight percent of Formula I: [Y0.01-1.0SiO1.5-2]a[Z0.01-1.0SiO1.5-2]b[H0.01-1.0SiO1.5-2]c where Y is aryl; Z is alkenyl; a is from 15 percent to 70 percent of Formula I; b is from 2 percent to 50 percent of Formula I; and c is from 20 percent to 80 percent of Formula I.Type: ApplicationFiled: June 3, 2002Publication date: February 13, 2003Inventors: William B. Bedwell, Nigel P. Hacker, Roger Y. Leung, Nancy Iwamoto, Jan Nedbal, Songyuan Xie, Lorenza Moro, Shyama P. Mukherjee
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Patent number: 6518170Abstract: A semiconductor device has an interlayer insulation film formed on a first metal wiring and formed of an organic compound having a lower dielectric constant than that of SiO2, a second metal wiring formed on the interlayer insulation film, and an interlayer adhesion layer to improve adherence between the interlayer insulation film and the second metal wiring. The semiconductor device is provided with a stress buffer layer of which the elastic modulus is higher than that of the interlayer insulation film and is lower than that of the interlayer adhesion layer between the interlayer insulation film and the interlayer adhesion layer.Type: GrantFiled: June 20, 2001Date of Patent: February 11, 2003Assignee: NEC CorporationInventor: Hirosada Koganei
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Patent number: 6518169Abstract: A plurality of metal interconnections are formed on a semiconductor substrate. The semiconductor substrate is held on a sample stage in a reactor chamber of a plasma processing apparatus and a material gas containing C5F8, C3F6, or C4F6 as a main component is introduced into the reactor chamber, so that a first fluorine-containing organic film having cavities at positions between the metal interconnections is deposited between the metal interconnections and on the top surfaces of the metal interconnections.Type: GrantFiled: November 8, 2000Date of Patent: February 11, 2003Assignee: Matsushita Electric Industrial co., Ltd.Inventors: Nobuhiro Jiwari, Shinichi Imai
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Method and system for providing inorganic vapor surface treatment for photoresist adhesion promotion
Patent number: 6515342Abstract: A system and method for forming a plurality of structures in a low dielectric constant layer is disclosed. The low dielectric constant layer is disposed on a semiconductor. The method and system include exposing the low dielectric constant layer to an agent that improves adhesion of a photoresist, providing a layer of the photoresist on the low dielectric constant layer, patterning the photoresist, and etching the low dielectric constant layer to form the plurality of structures.Type: GrantFiled: April 25, 2000Date of Patent: February 4, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Subhash Gupta, Bhanwar Singh, Carmen Morales -
Patent number: 6514881Abstract: An organically modified dielectric network structure (208) and solid halide-containing material (206) are co-deposited using a chemical vapor deposition process. The solid halide-containing material (206) is then sublimated leaving a porous dielectric (212). An encapsulating layer (210) is formed over the porous dielectric (212) to seal any remaining halide-containing material Within the porous dielectric (212).Type: GrantFiled: April 20, 2001Date of Patent: February 4, 2003Assignee: Texas Instruments IncorporatedInventor: Phillip R. Coffman
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Patent number: 6511924Abstract: A method for forming a silicon oxide layer for use in integrated circuit fabrication is provided. The silicon oxide layer is formed by reacting a first gas mixture and a second gas mixture. The first gas mixture comprises tetra-ethyl-ortho-silicate (TEOS), helium (He) and nitrogen (N2). The second gas mixture comprises ozone (O3) and optionally, oxygen (O2).Type: GrantFiled: April 20, 2001Date of Patent: January 28, 2003Assignee: Applied Materials, Inc.Inventors: Kevin Mukai, Srinivas Nemani
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Patent number: 6511909Abstract: A method and apparatus for depositing a low dielectric constant film by reaction of an organo silane compound and an oxidizing gas. The oxidized organo silane film has excellent barrier properties for use as a liner or cap layer adjacent other dielectric layers. The oxidized organo silane film can also be used as an etch stop or an intermetal dielectric layer for fabricating dual damascene structures. The oxidized organo silane films also provide excellent adhesion between different dielectric layers. A preferred oxidized organo silane film is produced by reaction of methyl silane, CH3SiH3, and N2O.Type: GrantFiled: August 9, 1999Date of Patent: January 28, 2003Assignee: Applied Materials, Inc.Inventors: Wai-Fan Yau, David Cheung, Shin-Puu Jeng, Kuowei Liu, Yung-Cheng Yu