Abstract: Methods of exposing conductive vias of semiconductor devices may involve positioning a barrier material over conductive vias extending from a backside surface of a substrate to at least substantially conform to the conductive vias. A self-planarizing isolation material may be positioned on a side of the barrier material opposing the substrate. An exposed surface of the self-planarizing isolation material may be at least substantially planar. A portion of the self-planarizing isolation material, a portion of the barrier material, and a portion of at least some of the conductive vias may be removed to expose each of the conductive vias. Removal may be stopped after exposing at least one laterally extending portion of the barrier material proximate the substrate.

Abstract: An organic EL panel with less variation in an emission luminance thereof and a method for manufacturing a light-emitting device using the same are provided. The organic EL panel of the present invention includes: a substrate; a light-emitting section of the organic EL panel provided on the substrate; a current supply terminal provided on the substrate for supplying a current to the light-emitting section; and a current density adjusting section electrically connected to the current supply terminal in parallel to the light-emitting section and provided on the substrate. A current density of the light-emitting section is adjusted by processing of the current density adjusting section. Moreover, in the method for manufacturing a light-emitting device according to the present invention, after a light-emitting characteristic is adjusted by processing a post-processing region of the above-described organic EL panel, a light-emitting device including the processed organic EL panel is manufactured.

Abstract: According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a p-side electrode, an n-side electrode, a fluorescent material layer and a scattering layer. The semiconductor layer has a first surface and a second surface on an opposite side to the first surface and includes a light emitting layer. The p-side electrode and the n-side electrode are provided on the semiconductor layer on a side of the second surface. The fluorescent material layer is provided on a side of the first surface and includes a plurality of fluorescent materials and a first bonding material. The first bonding material integrates the fluorescent materials. The scattering layer is provided on the fluorescent material layer and includes scattering materials and a second bonding material. The scattering materials are configured to scatter radiated light of the light emitting layer. The second bonding material integrates the scattering materials.

Abstract: An integrated system operation method is disclosed that includes the following steps: the film of a substrate is measured by a metrology apparatus to obtain a film information. The substrate is moved from the metrology apparatus to a process apparatus adjacent to the transfer apparatus. The film information is sent to the process apparatus. A film treatment is applied to the substrate in accordance with the film information.

Abstract: Techniques herein include systems and methods that provide a spatially-controlled or pixel-based projection of light onto a substrate to tune various substrate properties. A given pixel-based image projected on to a substrate surface can be based on a substrate signature. The substrate signature can spatially represent non-uniformities across the surface of the substrate. Such non-uniformities can include energy, heat, critical dimensions, photolithographic exposure dosages, etc. Such pixel-based light projection can be used to tune various properties of substrates, including tuning of critical dimensions, heating uniformity, evaporative cooling, and generation of photo-sensitive agents. Combining such pixel-based light projection with photolithographic patterning processes and/or heating processes improves processing uniformity and decreases defectivity. Embodiments can include using a digital light processing (DLP) chip, grating light valve (GLV), or other grid-based micro projection technology.

Abstract: Sacrificial optical test structures are constructed upon a wafer of pre-cleaved optical chips for testing the optical functions of the pre-cleaved optical chips. The sacrificial optical structures are disabled upon the cleaving the optical chips from the wafer and the cleaved optical chips can be used for their desired end functions. The test structures may remain on the cleaved optical chips or they may be discarded.

Abstract: A translucent member 41 that has been trial-coated with a resin 8 for measurement of a light emission characteristic is placed on a translucent member placement portion 53, an excitation light that excites a phosphor is emitted from a light source unit 42 disposed above, the resin 8 coated on the translucent member 41 is irradiated with the excitation light from above, a deviation between a measurement result obtained by measuring the light emission characteristic of the light emitted from the resin 8, and a light emission characteristic specified in advance is obtained, and an appropriate resin coating amount of the resin to be coated on the LED element for actual production is derived on the basis of the deviation.

Abstract: Some embodiments of the present disclosure relate to a tool configuration and method for EUV patterning with a deformable reflective surface comprising a mirror or reticle. A radiation source provides EUV radiation which is reflected off the deformable reflective surface to transfer a reticle pattern to a semiconductor workpiece. A metrology tool measures a residual vector formed between a first shape of the semiconductor workpiece and a second shape of the reticle pattern. And, a topology of the deformable reflective surface is changed based upon the residual vector to minimize a total magnitude of the residual vector.

Abstract: A method for manufacturing an electroluminescent element including: a first manufacturing step of layering on a substrate, in the following order, a first electroconductive layer, a dielectric layer in which plural contact holes are formed which pass therethrough in a direction orthogonal to the substrate, a second electroconductive layer which is electrically connected to the first electroconductive layer inside the contact holes and which fills the contact holes, a light-emitting layer, and a third electroconductive layer; a temperature distribution measurement step of applying a voltage to the first electroconductive layer and the third electroconductive layer, causing the light-emitting layer to emit light, and measuring the temperature distribution of the electroluminescent element to obtain temperature unevenness information for the electroluminescent element; and a second manufacturing step of adjusting, on the basis of the temperature unevenness information, the density of the plural contact holes tha

Abstract: A semiconductor substrate is secured by suction to a rear face of a supporting face of a substrate supporting table. In this event, the thickness of the semiconductor substrate is made fixed by planarization on the rear face, and the rear face is forcibly brought into a state free from undulation by the suction to the supporting face, so that the rear face becomes a reference face for planarization of a front face. In this state, a tool is used to cut surface layers of Au projections and a resist mask on the front face, thereby planarizing the Au projections and the resist mask so that their surfaces become continuously flat. This can planarize the surfaces of fine bumps formed on the substrate at a low cost and a high speed in place of CMP.

Abstract: A method for improving imaging properties of an optical system and an optical system of this type having improved imaging properties are described. The optical system can have a plurality of optical elements. In some embodiments, an optical element is positioned and/or deformed by mechanical force action and by thermal action. In certain embodiments, one optical element is positioned and/or deformed by mechanical force action and another optical element is deformed by thermal action.

Abstract: An apparatus and method of manufacturing a light emitting diode (LED) device, and more particularly, an apparatus and method of manufacturing an LED device by dispensing a fluorescent solution prepared by mixing a fluorescent material with a liquid synthetic resin, onto an LED chip. An apparatus and method of manufacturing an LED device, whereby an appropriate amount of fluorescent solution simultaneously in consideration of several factors, such as characteristics of an LED chip and viscosity of the fluorescent solution may be dispensed onto the LED chip, is provided. An apparatus and method of manufacturing an LED device, whereby an appropriate amount of fluorescent solution may be calculated actively in consideration of viscosity of the fluorescent solution, a change in characteristics of an LED chip, or the like, and the appropriate amount of fluorescent solution may be dispensed onto the LED chip, is provided.

Abstract: An efficient method of detecting defects in metal patterns on the surface of wafers. Embodiments include forming a metal pattern on each of a plurality of wafers, polishing each wafer, and analyzing the surface of the metal pattern on each polished wafer for the presence of defects in the metal pattern by analyzing an optical across-wafer endpoint signal, generated at the endpoint of polishing. Embodiments include determining the location of defects in the metal pattern by determining the position of non-uniformities in the optical-across-wafer endpoint signal.

Abstract: Provided are a high-quality LED and LED member, and a method and a device with which it is possible to manufacture the same in large quantities and at minimal manufacturing cost. The present invention comprises a detachment/attachment unit for the LED or the LED member, a coating unit for performing automatic coating, and a drying unit. A coating is applied using the coating unit, and provisional drying is performed or hardening is accelerated using the drying device. Alternatively, coating and drying are repeated multiple times, after which drying or hardening is finally performed.

Abstract: Provided are a deposition data processing apparatus, an apparatus and a method for manufacturing an organic EL device, which make it possible to check deposition states of constituent layers of each of organic EL elements that are continuously formed on a substrate being conveyed. The deposition data processing apparatus includes a scanning section configured to scan at least two of a plurality of constituent layers that constitute each of the organic EL elements; and a processor configured to accumulate data of the constituent layers scanned by the scanning section at a specific position in a longitudinal direction of the substrate as data of a specific one of the organic EL elements.

Abstract: The present disclosure relates to a method to form a plurality of openings within a substrate with a single photo exposure and a single etch process. A photoresist layer is disposed over a substrate and aligned with a photomask, wherein the photomask comprises a transparent area, a grayscale area, and an opaque area. The photomask and substrate are exposed to radiation comprising a single illumination step to form a first 3-dimensional pattern within the photoresist layer. The 3-dimensional pattern comprises a first opening comprising a first thickness formed by transmitting the radiation through the transparent area with full intensity, and a second opening comprising a second thickness formed by transmitting the radiation through the grayscale area with partial intensity. The 3-dimensional pattern is transferred to form a plurality of openings of varying depths within the substrate through a single etch step.

Abstract: A semiconductor device arrangement comprising a functional circuit comprising a plurality of timing components and a reference module comprising a plurality of reference components is described. Each reference component comprises a reference timing component corresponding to a timing component of the plurality of timing components and a controllable timing component. The controllable timing component is arranged to provide a delay in dependence on an applied light stimulus. A method of analysing a performance of a functional circuit on a semiconductor device is also described. A device analysis system for analysing a functional circuit comprising a plurality of timing components is also described.

Abstract: A laser annealing apparatus reduces laser annealing time and has a simple configuration. A laser annealing method is used to manufacture a display apparatus. The laser annealing apparatus includes a mounting unit, a substrate mounted on the mounting unit, first and second driving modules installed on the mounting unit and adjusting locations of first and second mark masks to be placed on a part of the substrate, first and second image modules that may obtain image data regarding the first and second mark masks to be location-adjusted by first and second driving modules, and a laser module that radiates a laser beam to the substrate and changes at least a part of an amorphous silicon layer of the substrate to crystalline silicon.

Abstract: A method for producing a plurality of optoelectronic components may include measuring at least one measurement parameter for a first optoelectronic component and a second optoelectronic component, and processing the first optoelectronic component and the second optoelectronic component taking account of the measured measurement parameter value of the first optoelectronic component and the measured measurement parameter value of the second optoelectronic component, such that the optoelectronic properties of the first optoelectronic component and the optoelectronic properties of the second optoelectronic component are changed in a different way toward at least one common predefined optoelectronic target property. The processing of at least one value of a measurement parameter of the optoelectronic properties of the first optoelectronic component or of the optoelectronic properties of the second optoelectronic component toward the optoelectronic target property is formed by means of a compensation element.

Abstract: A manufacturing method for a solar cell, wherein after a texture is formed on a principal surface of a substrate, infrared light in a predetermined wave number range is applied to a portion, on which the texture is formed, of the principal surface, a wave number at a specified transmission detection rate of the infrared light transmitted through the substrate and detected is acquired, the Tx size of the substrate is calculated on the basis of the acquired wave number using a previously obtained relationship between the wave number at the specified transmission detection rate and the Tx size, and when the calculated Tx size is within a reference value range, a collecting electrode is formed on the principal surface.

Abstract: An organic light emitting diode (OLED) display includes a substrate where a plurality of pixels are formed, a first pixel defining layer on the substrate, the first pixel defining layer dividing the plurality of pixels, a connection wire on the first pixel defining layer, the connection wire electrically connecting two adjacent pixels, and a second pixel defining layer on the first pixel defining layer, the second pixel defining layer covering the connection wire.

Abstract: A multi-patterning method of manufacturing a patterned wafer provides test structures designed to enhance overlay error measurement sensitivity for monitoring and process control. One or more patterns are overlaid on a first pattern, each of a given pitch, with the elements interleaved. Test structure is formed with elements of the overlaid patterns spaced away from respective mid-positions more closely toward elements of the first pattern. In some embodiments, test structure elements of the second pattern are overlaid midway between mid-positions of elements of the first pattern and measured by scatterometry. In other embodiments, test structure elements of the second pattern are overlaid at a slightly different pitch than the elements of the first pattern and measured by reflectivity. Measurements are compared with library measurements to identify the error, which may be fed back to control the patterning process. The multi-patterning may be formed by LELE, LLE, LFLE, or other methods.

Abstract: A lithography apparatus which performs writing on a substrate using a charged particle beam is provided. The apparatus comprises a plurality of column units each of which comprises a charged particle optical system, a plurality of stages each of which is movable while holding the substrate, and a controller. The controller moves the stages in synchronization with each other in a positional relationship corresponding to an arrangement of the column units, and performs writing on substrates held in the stages simultaneously.

Abstract: A test structure and method are provided to facilitate developing or optimizing a fabrication process by determining values of one or more lithography process parameters for use in semiconductor device fabrication. The test structure is configured to facilitate determining values of the one or more fabrication process parameters, and includes a plurality of test structure components arranged on a substrate according to a test pattern. The test pattern may be based on: varying distances between the test structure components according to a first rule; varying distances between centers of the test structure components according to a second rule; and/or varying at least one dimension of the test structure components according to a third rule. The method may further include determining dimensions of one or more components of the test structure using, for example, scatterometry, and using the dimensions of the components to ascertain one or more fabrication process parameters.

Abstract: A system and method of providing a deformed FAC Lens to a multi-emitter diode bar laser system comprised of a lens holder and FAC lens wherein the FAC Lens is deformed so as to offset or compensate for the inherent smile properties present in a multi-emitter diode bar.

Abstract: In some embodiments, a method of controlling a photoresist trimming process in a semiconductor manufacturing process may include forming a photoresist layer atop a first surface of a substrate, wherein the photoresist layer comprises a lower layer having a first pattern to be etched into the first surface of the substrate, and an upper layer having a second pattern that is not etched into the first surface of the substrate; trimming the photoresist layer in a direction parallel to the first surface of the substrate; measuring a trim rate of the second pattern using an optical measuring tool during the trimming process; and correlating the trim rate of the second pattern to a trim rate of the first pattern to control the trim rate of the first pattern during the trimming process.

Abstract: A manufacturing method for an electroluminescent element including a first manufacturing step of layering on a substrate, a first electroconductive layer, a dielectric layer in which plural contact holes are formed which penetrate therethrough, a second electroconductive layer electrically connected to the first electroconductive layer inside the contact holes and which fills the contact holes, a light-emitting layer, and a third electroconductive layer; a luminance distribution measurement step of applying a voltage to the first electroconductive layer and the third electroconductive layer of the electroluminescent element manufactured, causing the light-emitting layer to emit light, and the luminance distribution of the electroluminescent element is measured to obtain luminance unevenness information; and a second manufacturing step in which, on the basis of the luminance unevenness information, the density of the plural contact holes that penetrate the dielectric layer is adjusted to manufacture a second e

Abstract: A substrate treatment apparatus configured such that substrates in a same lot are distributed by a delivery mechanism into a plurality of unit blocks, each unit block including a solution treatment module, an ultraviolet irradiation module, and a substrate carrying mechanism, the apparatus includes: an illuminance detection part that detects an illuminance of a light source of the ultraviolet irradiation module; and a control part that controls, when an illuminance detection value of the ultraviolet irradiation module in one unit block among the plurality of unit blocks becomes a set value or less, the delivery mechanism to stop delivery of a substrate to the one unit block and deliver subsequent substrates to another unit block, and the ultraviolet irradiation module to perform irradiation on substrates which have already been delivered to the one unit block with an irradiation time adjusted to a length according to the illuminance detection value.

Abstract: A method of manufacturing an organic electroluminescent element including: a first manufacturing process of stacking at least a first electrode layer, a dielectric layer, and a second electrode layer on a substrate in this order, the organic electroluminescent element having a light-emitting portion that is in contact with an inner surface of a concave portion formed to penetrate the dielectric layer; measuring a brightness distribution of the organic electroluminescent element while causing the light-emitting portion to emit light by applying a voltage to the first electrode layer and the second electrode layer of the organic electroluminescent element manufactured in the first manufacturing process, and obtaining uneven brightness information of the organic electroluminescent element; and a second manufacturing process of adjusting concave portion density on the basis of the uneven brightness information obtained in the brightness distribution measurement process, and reducing uneven brightness of the organ

Abstract: The invention is directed towards methods and compositions for identifying the amount of hydrofluoric acid in a buffered oxide etching composition. In buffered oxide etching compositions it is very difficult to measure the amount of hydrofluoric acid because it has varying equilibriums and it is toxic so it hard to handle and sample. When used to manufacture microchips however, incorrect amounts of hydrofluoric acid will ruin those chips. The invention utilizes a unique method of spectrographically measuring the hydrofluoric acid when in contact with added chromogenic agents to obtain exact measurements that are accurate, immediate, and safe.

Abstract: There is provided an inspection method for inspecting a substrate supporting portion configured to support a substrate during an exposure performed by an exposure apparatus, the method including: irradiating a surface of the exposed substrate with an illumination light beam; detecting reflected light from a pattern in the irradiated surface; determining a focusing state at the time of exposing the pattern of the substrate based on the detected reflected light; and inspecting a state of the substrate supporting portion based on the focusing state.

Abstract: This invention discloses methods and apparatus to form organic semiconductor transistors upon three-dimensionally formed insert devices. In some embodiments, the present invention includes incorporating the three-dimensional surfaces with organic semiconductor-based thin film transistors, electrical interconnects, and energization elements into an insert for incorporation into ophthalmic lenses. In some embodiments, the formed insert may be directly used as an ophthalmic device or incorporated into an ophthalmic device.

Abstract: The present invention provides a method for monitoring a contact hole etching process of a TFT substrate, which includes: (1) providing a substrate having a first metal layer and a monitoring machine; (2) providing a target value of reflection rate of the substrate having the first metal layer; (3) applying a masking operation to patternize the first metal layer for forming a gate terminal; (4) forming a gate insulation layer on the gate terminal; and (5) forming a contact hole in the gate insulation layer through etching and simultaneously operating the monitoring machine to measure the reflection rate of a bottom of the contact hole, whereby when the reflection rate of the bottom of the contact hole is substantially equal to the target value, the etching operation is stopped. The variation of reflection rate of the metal layer is monitored to identify if the insulation layer is completely etched away.

Abstract: Methods are disclosed including applying a layer of binder material onto an LED structure. A luminescent solution including an optical material suspended in a solution is atomized using a flow of pressurized gas, and the atomized luminescent solution is sprayed onto the LED structure including the layer of binder material using the flow of pressurized gas.

Abstract: When an etchant for metal (e.g., HF) reaches an underlying silicon oxide layer, it may form silanol bonds or other hydrogen bonds that resist rinsing, so that some etchant remains to be trapped under the next deposited layer. Trapped etchant can create voids that eventually degrade the performance of the oxide layer. Exposing the surface to a liquid solution or gaseous precursor containing silane seals the defects without causing an overall thickness change. The silane reacts at sites with silanol (or other hydrogen) bonds, breaking the bonds and replacing the hydrogen with silicon, but does not react in the absence of a hydrogen bond.

Abstract: Light emitting semiconductor junctions are disclosed. An exemplary light emitting junction has a first electrical contact coupled to a first side of the junction. The exemplary junction also has a second electrical contact coupled to a second side of the junction. The exemplary junction also has a region of set straining material that exerts a strain on the junction and alters both: (i) an optical polarization, and (ii) an emission wavelength of the junction. The region of set straining material is not on a current path between said first electrical contact and said second electrical contact. The region of set straining material covers a third side and a fourth side of the light emitting junction along a cross section of the light emitting junction. The light emitting semiconductor junction device comprises a three-five alloy.

Abstract: The invention is directed towards methods and compositions for identifying the amount of ammonium acid in a buffered oxide etching composition. In buffered oxide etching compositions it is very difficult to measure the amount of ammonium acid because it has varying equilibriums and it is toxic so it hard to handle and sample. When used to manufacture microchips however, incorrect amounts of ammonium acid will ruin those chips. The invention utilizes a unique method of spectrographically measuring the ammonium acid when in contact with added chromogenic agents to obtain exact measurements that are accurate, immediate, and safe.

Abstract: The present invention relates to a method of measuring surface properties of a polishing pad which measures surface properties such as surface topography or surface condition of a polishing pad used for polishing a substrate such as a semiconductor wafer. The method of measuring surface properties of a polishing pad includes applying a laser beam to the polishing pad, detecting scattered light that is reflected and scattered by the polishing pad with a photodetector and performing an optical Fourier transform on the detected scattered light to produce an intensity distribution corresponding to a spatial wavelength spectrum based on surface topography of the polishing pad, and calculating a numerical value representing surface properties of the polishing pad based on the intensity distribution corresponding to two different prescribed spatial wavelength ranges.

Abstract: A method for manufacturing an optoelectronic semiconductor component, comprising: providing a semiconductor chip in a composite wafer, comprising an active side for emitting a primary radiation and a contact terminal which is arranged on the active side; depositing a coupling element on the active side; attaching a luminescence conversion element, for converting part of the primary radiation into a secondary radiation, to the coupling element.

Abstract: A method of measuring an overlay of an object is provided. In the method, first information of a first structure may be obtained. A preliminary structure may be formed on the first structure. Second information of the preliminary structure may be obtained. The first information and the second information may be processed to obtain virtual information of a second structure that would be formed on the first structure if a process is performed on the preliminary structure. A virtual overlay between the first structure and the second structure may be measured using the virtual information.

Abstract: A device and method for dispensing liquid spin-on glass (SOG) onto semiconductor wafers. The method includes dispensing liquid SOG through a dispenser nozzle, detecting liquid SOG outside of the dispenser nozzle, indicating the presence of liquid SOG in an abnormal length relative to the dispenser nozzle and adjusting a suck back (SB) valve to withdraw liquid SOG from the abnormal length.

Abstract: Sacrificial optical test structures are constructed upon a wafer of pre-cleaved optical chips for testing the optical functions of the pre-cleaved optical chips. The sacrificial optical structures are disabled upon the cleaving the optical chips from the wafer and the cleaved optical chips can be used for their desired end functions. The test structures may remain on the cleaved optical chips or they may be discarded.

Abstract: Methods of optimizing the diameters of nanowire photodiode light sensors. The method includes comparing the response of nanowire photodiode pixels having predetermined diameters with standard spectral response curves and determining the difference between the spectral response of the photodiode pixels and the standard spectral response curves. Also included are nanowire photodiode light sensors with optimized nanowire diameters and methods of scene reconstruction.

Abstract: A method of doping a non-planar surface or a surface of a substrate subject to poor view factors is provided. The processing chamber comprises a window, walls, and a bottom of the processing chamber with oxygen-containing material, the processing chamber configured to supply oxygen radicals as an additive to doping materials. One or more quartz pieces are placed inside the processing chamber, where a magnet proximate to the processing chamber is configured to create a local magnetron plasma inside the processing chamber. Process gas containing an inert gas, sublimated doping materials, and optionally oxygen gas is flowed into the processing chamber; energy is applied to the process gas, generating a doping plasma used to expose a portion of the substrate surface while controlling operating variables to achieve target uniformity of dopant concentration, sheet resistance, degree of dopant clustering, and erosion of features on the substrate.

Abstract: A method generally for improving wafer-to-wafer bonding alignment. Planar distortions of the bonding surface of a host wafer are determined. The bonding surface of a donor wafer is distorted such that the distortions of the donor wafer bonding surface correspond to the determined planar distortions of the host wafer bonding surface. Also, a method to separate bonded wafers. A bonded wafer pair is mounted between first and second bonding chucks having flat chuck faces, the first bonding chuck face including adjustable zones capable of movement relative to each other, at least a component of the relative movement is along an axis that is perpendicular to the flat first bonding chuck face. The adjustable zones of the first face are moved relative to each other in a coordinated manner such that a widening gap is formed between the bonding faces of the wafer pair.

Abstract: A method for wafer bonding includes measuring grid distortion for a mated pairing of wafers to be bonded to determine if misalignment exists between the wafers. During processing of subsequent wafers, magnification of one or more lithographic patterns is adjusted to account for the misalignment. The subsequent wafers are bonded with reduced misalignment.

Abstract: A method for etching a polysilicon gate is disclosed, wherein the polysilicon gate includes an undoped polysilicon portion and a doped polysilicon portion that is situated on the undoped polysilicon portion. The method includes: obtaining a thickness of the undoped polysilicon portion and a thickness of the doped polysilicon portion by using an optical linewidth measurement device; and etching the undoped polysilicon portion and the doped polysilicon portion by using two respective steps with different parameters, respective etching time for the undoped polysilicon portion and the doped polysilicon portion of every wafer being adjusted in real time by using an advanced process control system. This method enables the doped and undoped polysilicon portions of each polysilicon gate on every wafer to have substantially consistent profiles between each other.

Abstract: A method of semiconductor processing comprises providing a semiconductor wafer in a processing chamber; feeding at least one tungsten-containing precursor in a gas state into the processing chamber for atomic layer deposition (ALD) of tungsten; feeding at least one reducing chemical in a gas state into the processing chamber; and monitoring a concentration of at least one gaseous byproduct in the chamber; and providing a signal indicating concentration of the at least one gaseous byproduct in the chamber. The byproduct is produced by a reaction between the at least one tungsten-containing precursor and the at least one reducing chemical during the ALD.

Abstract: A method of controlling polishing includes storing a library having a plurality of reference spectra, polishing a substrate, measuring a sequence of spectra of light from the substrate during polishing, for each measured spectrum of the sequence of spectra, finding a best matching reference spectrum using a matching technique other than sum of squared differences to generate a sequence of best matching reference spectra, and determining at least one of a polishing endpoint or an adjustment for a polishing rate based on the sequence of best matching reference spectra. Finding a best matching reference spectrum may include performing a cross-correlation of the measured spectrum with each of two or more of the plurality of reference spectra from the library and selecting a reference spectrum with the greatest correlation to the measured spectrum as a best matching reference spectrum.

Abstract: A method includes performing a semiconductor fabrication process on a plurality of substrates. The plurality of substrates are divided into a first subset and a second subset. A rework process is performed on the second subset of the plurality of substrates but not on the first subset. A respective mean value of at least one exposure parameter for a lithography process is computed for each respective one of the first and second subsets of the plurality of substrates. A scanner overlay correction and a mean correction are applied to expose a second plurality of substrates on which the rework process has been performed. The mean correction is based on the computed mean values.