Abstract: A method for forming ultra-high density integrated circuitry, such as for a 6T SRAM, for example, is provided. The method involves applying double patterning litho-etch litho-etch (LELE) and using a spacer process to shrink the critical dimension of features. To improve process margins, the method implements a double-patterning technique by modifying the layout and splitting cross-coupling straps into two colors (e.g., each color corresponds to a mask-etch process). In addition, a spacer process is implemented to shrink feature size and increase the metal-to-metal spacing between the two cross-coupling straps, in order to improve process margin and electrical performance. This is achieved by depositing a spacer layer over an opening in a hardmask, followed by spacer etch back. The opening is thus shrunk by the amount of spacer thickness. The strap-to-strap spacing may then be increased by twice the amount of spacer thickness.

Abstract: Disclosed embodiments apply electron beams to substrates for microelectronic workpieces to improve plasma etch and deposition processes. The electron beams are generated and directed to substrate surfaces using DC (direct current) biasing, RF (radio frequency) plasma sources, and/or other electron beam generation and control techniques. For certain embodiments, DC-biased RF plasma sources, such as DC superposition (DCS) or hybrid DC-RF sources, are used to provide controllable electron beams on surfaces opposite a DC-biased electrode. For certain further embodiments, the DC-biased electrode is pulsed. Further, electron beams can also be generated through electron beam extraction from external and/or non-ambipolar sources. The disclosed techniques can also be used with additional electron beam sources and/or additional etch or deposition processes.

Abstract: A substrate processing apparatus includes: a placing table having a placement surface and provided with a heater in each divided region obtained by dividing the placement surface; a calculation unit that calculates a target temperature of the heater in each divided region in which a critical dimension at a predetermined measurement point satisfies a predetermined condition, using a prediction model that predicts the critical dimension of the measurement point by using a temperature of the heater in each divided region as a parameter and taking into consideration an influence of a temperature of a heater in a divided region other than a divided region including the measurement point in accordance with a distance between the measurement point and the other divided region; and a heater controller that controls the heater in each divided region to reach the target temperature when the substrate processing is performed on the substrate.

Abstract: Provided is a plasma processing apparatus including a microwave radiating mechanism configured to radiate microwaves output from a microwave output unit into a processing container. The microwave radiating mechanism includes: an antenna configured to radiate the microwaves; a dielectric member configured to transmit the microwaves radiated from the antenna, and form an electric field for generating surface wave plasma by the microwaves; a sensor provided in the microwave radiating mechanism or adjacent to the microwave radiating mechanism, and configured to monitor electron temperature of the generated plasma; and a controller configured to determine a plasma ignition state based on the electron temperature of the plasma monitored by the sensor.

Abstract: According to one embodiment, a method includes forming a first insulative layer above a bottom surface of a groove and along inner sidewalls thereof, forming a source line layer within the groove of the substrate, forming a first dielectric layer on outer sides of a middle portion of the source line layer, forming a buffer layer on outer sides of the first dielectric layer, forming a gate terminal above the source line layer, forming a gate dielectric layer between the source line layer and the gate terminal and on outer sides of the lower portion of the gate terminal, forming a drain terminal including strained Si on outer sides of the first dielectric layer, and forming a relaxed buffer layer on outer sides of the upper portion of the source line layer and outer sides of the drain terminal, with the gate terminal extending beyond the relaxed buffer layer thickness.

Abstract: The plasma processing apparatus includes a plasma processing unit that performs plasma processing of a sample and a control unit that controls the plasma processing. The control unit selects one of a plurality of the prediction models for predicting a result of the plasma processing based on a state of the plasma processing unit, and predicts the result of the plasma processing by using a selected prediction model.

Abstract: The present invention provides a method and apparatus for etching a photomask substrate with enhanced process monitoring, for example, by providing for optical monitoring at certain regions of the photomask to obtain dual endpoints, e.g., etch rate or thickness loss of both a photoresist layer and an absorber layer. By monitoring transmissity of an optical beam transmitted through areas having photoresist layer and etched absorber layer at two different predetermined wavelength, dual process endpoints may be obtained by a signal optical detection.

Abstract: A method and system are for monitoring and controlling deformation of a wafer substrate during a plasma etching of the wafer substrate. The method includes disposing a wafer substrate on a platen assembly within a process chamber so that an entire upper surface of the wafer is exposed, passing a process gas into the process chamber, applying a radio frequency bias voltage to the platen assembly, generating a plasma within the process chamber, monitoring a voltage difference between the platen assembly and the process chamber, during the etch process, and attenuating or extinguishing the plasma to prevent further etching once a threshold monitored voltage is reached.

Abstract: A method of cleaning a substrate processing apparatus that etches a film including a metal, the method include a first cleaning step of providing a gas containing a hydrogen-containing gas, and removing a carbon-containing deposition by plasma generated from the gas containing the hydrogen-containing gas; a second cleaning step of, after the first cleaning step, providing an inert gas, and removing a metal-containing deposition by plasma generated from the inert gas; and a third cleaning step of, after the second cleaning step, providing a gas containing a fluorine-containing gas and an oxygen-containing gas, and removing a silicon-containing deposition by plasma generated from the gas containing the fluorine-containing gas and the oxygen-containing gas.

Abstract: Disclosed are methods of generating a proximity-corrected design layout for photoresist to be used in an etch operation. The methods may include identifying a feature in an initial design layout, and estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature during the etch operation. The methods may further include estimating a quantity characteristic of an edge placement error (EPE) of the feature by comparing the one or more quantities characteristic of the IFPF to those in a look-up table (LUT, and/or through application of a multivariate model trained on the LUT, e.g., constructed through machine learning methods (MLM)) which associates values of the quantity characteristic of EPE with values of the one or more quantities characteristics of the IFPF. Thereafter, the initial design layout may be modified based on at the determined quantity characteristic of EPE.

Abstract: A method and apparatus for determining a stability of plasma in a plasma processing apparatus for performing a plasma processing by converting into plasma a processing gas supplied into a processing container. The method includes: detecting a light emission intensity of the plasma in the processing container while the plasma is generated in the processing container; generating a first function representing a relationship between time and the light emission intensity from a detection result of the light emission intensity; differentiating the first function with time to calculate a differential value, and generating a second function from a relationship between an absolute value of the differential value and time; and integrating the second function with time to calculate an integral value, and determining a stability of the plasma based on the calculated integral value. A related apparatus is also provided.

Abstract: Monitoring a geometric parameter value for one or more features produced on a substrate during an etch process may involve: (a) measuring optical signals produced by optical energy interacting with features being etched on the substrate; (b) providing a subset of the measured optical signals, wherein the subset is defined by a range where optical signals were determined to correlate with target geometric parameter values for features; (c) applying the subset of optical signals to a model configured to predict the target geometric parameter values from the measured optical signals; (d) determining, from the model, a current value of the target geometric parameter of the features being etched; (e) comparing the current value of the target geometric parameter of the features being etched to an etch process endpoint value for the target geometric parameter; and (f) repeating (a)-(e) until the comparing in (e) indicates that the current value of the target geometric parameter of the features being etched has reach

Abstract: Transport and surface chemistry of certain deposition techniques is modeled. Methods provide a model of the transport inside nanostructures as a single-particle discrete Markov chain process. This approach decouples the complexity of the surface chemistry from the transport model, thus allowing its application under general surface chemistry conditions, including atomic layer deposition (ALD) and chemical vapor deposition (CVD). Methods provide for determination of determine statistical information of the trajectory of individual molecules, such as the average interaction time or the number of wall collisions for molecules entering the nanostructures as well as to track the relative contributions to thin-film growth of different independent reaction pathways at each point of the feature.

Abstract: Systems, chambers, and processes are provided for controlling process defects caused by moisture contamination. The systems may provide configurations for chambers to perform multiple operations in a vacuum or controlled environment. The chambers may include configurations to provide additional processing capabilities in combination chamber designs. The methods may provide for the limiting, prevention, and correction of aging defects that may be caused as a result of etching processes performed by system tools.

Abstract: Methods of and carriers for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a carrier for supporting a wafer or substrate in an etch process includes a frame having a perimeter surrounding an inner opening. The carrier also includes a tape coupled to the frame and disposed below the inner opening of the frame, the tape comprising an etch stop layer disposed above a support layer.

Abstract: An apparatus for inspecting static electricity of a substrate includes a probe having substantially a same shape as a substrate to be inspected, the probe including a contact surface made of a conductive material, a wiring connected to the contact surface of the probe and delivering static electricity collected by the probe, and a measurement unit connected to the wiring, the measurement unit receiving the static electricity from the wiring and analyzing an intensity of the static electricity.

Abstract: An etching method can improve etching accuracy as well as secure selectivity when forming a dummy gate of a fin-type field effect transistor. In the etching method, the dummy gate of a fin-type field effect transistor is formed with a target object. In the etching method, a gate material deposited between multiple fins is etched by using surface wave plasma. A pressure in the etching method is 50 mTorr (6.67 Pa) or more, a frequency of a power to be applied to a mounting table configured to mount thereon the target object is in a range of 10 Hz or more to 200 Hz or less, and the power is pulse-modulated such that a duty ratio as a ratio of an ON-time to a pulse cycle is 50% or less.

Abstract: A method is described for improving the uniformity over a predetermined substrate area of a spectral response of photonic devices fabricated in a thin device layer. The method includes (i) establishing an initial device layer thickness map for the predetermined area, (ii) establishing a linewidth map for the predetermined area, and (iii) establishing an etch depth map for the predetermined area. The method further includes, based on the initial device layer thickness map, the linewidth map and the etch depth map, calculating an optimal device layer thickness map and a corresponding thickness correction map for the predetermined substrate area taking into account photonic device design data. Still further, the method includes performing a location specific corrective etch process in accordance with the thickness correction map.

Abstract: A method and apparatus for etching a photomask substrate with enhanced process monitoring is provided. In one embodiment, a method of determining an etching endpoint includes performing an etching process on a first tantalum containing layer through a patterned mask layer, directing a radiation source having a first wavelength from about 200 nm and about 800 nm to an area uncovered by the patterned mask layer, collecting an optical signal reflected from the area covered by the patterned mask layer, analyzing a waveform obtained the reflected optical signal reflected from the substrate from a first time point to a second time point, and determining a first endpoint of the etching process when a slope of the waveform is changed about 5 percent from the first time point to the second time point.

Abstract: Aspects of the present invention relate to method for reducing lateral extrusion formed in semiconductor structures and semiconductor structures formed thereof. Various embodiments include a method for reducing lateral extrusion formed in semiconductor structures. The method can include removing a portion of a first lateral extrusion in an aluminum layer of the semiconductor structure, and determining a post-removal thickness of a dielectric layer positioned adjacent the aluminum layer. The post-removal thickness may be determined subsequent to the removing of the portion of the first lateral extrusion. The method can also include determining a difference between the post-removal thickness of the dielectric layer and a pre-removal thickness of the dielectric layer.

Abstract: An article having alternating oxide layers and nitride layers is etched by an etch process. The etch process includes providing a first gas comprising C4F6H2 in a chamber of an etch reactor, ionizing the C4F6H2 containing gas to produce a plasma comprising a plurality of ions, and etching the article using the plurality of ions.

Abstract: Etch rate distribution non-uniformities are predicted for a succession of hardware tilt angles of the RF source applicator relative to the workpiece, and the behavior is modeled as a non-uniformity function for each one of at least two plasma reactors. An offset ?? in tilt angle ? between the non-uniformity functions of the two plasma reactors is detected. The two reactors are then matched by performing a hardware tilt in one of them through a tilt angle equal to the offset ??.

Abstract: Provided is a chamber cleaning method capable of efficiently removing a CF-based shoulder deposit containing Si and Al deposited on an outer periphery of an ESC. A mixed gas of an O2 gas and a F containing gas is supplied toward an outer periphery 24a of an ESC 24 at a pressure ranging from about 400 mTorr to about 800 mTorr; plasma generated from the mixed gas is irradiated onto the outer periphery 24a of the ESC 24; an O2 single gas as a mask gas is supplied to the top surface of ESC 24 except the outer periphery 24a; and the shoulder deposit 50 adhered to the outer periphery 24a is decomposed and removed while preventing the top surface of ESC 24 except the outer periphery 24a from being exposed to a F radical.

Abstract: There is provided a method of analyzing data obtained from an etching apparatus for micromachining a wafer using plasma. This method includes the following steps: acquiring the plasma light-emission data indicating light-emission intensities at a plurality of different wavelengths and times, the plasma light-emission data being measured under a plurality of different etching processing conditions, and being obtained at the time of the etching processing, evaluating the relationship between changes in the etching processing conditions and changes in the light-emission intensities at the plurality of different wavelengths and times with respect to the wavelengths and times of the plasma light-emission data, and identifying the wavelength and the time of the plasma light-emission data based on the evaluation result, the wavelength and the time being to be used for the adjustment of the etching processing condition.

Abstract: A method for automatically detecting fault conditions and classifying the fault conditions during substrate processing is provided. The method includes collecting processing data by a set of sensors during the substrate processing. The method also includes sending the processing data to a fault detection/classification component. The method further includes performing data manipulation of the processing data by the fault detection/classification component. The method yet also includes executing a comparison between the processing data and a plurality of fault models stored within a fault library. Each fault model of the plurality of fault models represents a set of data characterizing a specific fault condition. Each fault model includes at least a fault signature, a fault boundary, and a set of principal component analysis (PCA) parameters.

Abstract: A method and system to map density and temperature of a chip, in situ, is disclosed. The method includes measuring a propagation time that a mechanical propagation wave travels along at least one predefined path in a substrate. The method further includes calculating an average substrate density and temperature along the at least one predefined path as a function of the propagation time and distance. The method further includes determining a defect or unauthorized modification in the substrate based on the average substrate density being different than a baseline substrate density.

Abstract: An embodiment low contamination chamber includes a gas inlet, an adjustable top electrode, an adjustable bottom electrode, and an outlet. The chamber is configured to adjust a distance between the adjustable top and bottom electrodes in accordance with a desired density of plasma disposed between the top electrode and the bottom electrode.

Abstract: In accordance with an embodiment, an evaluation sample includes a substrate and a polycrystalline film on the substrate. The polycrystalline film has crystal grains. A specific orientation plane is exposed on the surface of each crystal grain. The orientation planes exhibit random angles to the surface of the substrate.

Abstract: The invention is directed towards methods and compositions for identifying the amount of hydrofluoric acid in a buffered oxide etching composition. In buffered oxide etching compositions it is very difficult to measure the amount of hydrofluoric acid because it has varying equilibriums and it is toxic so it hard to handle and sample. When used to manufacture microchips however, incorrect amounts of hydrofluoric acid will ruin those chips. The invention utilizes a unique method of spectrographically measuring the hydrofluoric acid when in contact with added chromogenic agents to obtain exact measurements that are accurate, immediate, and safe.

Abstract: A plasma etch tool includes a wafer chuck with a chuck base and at least one functional component layer attached to the chuck base. A perimeter of the functional component layer has a polymer material permanently attached to it that extends to within 2 millimeters of a top surface of the chuck. The top surface of the wafer chuck contacts a bottom surface of a semiconductor wafer during an etch process for forming an integrated circuit. The polymer material is protected from an etch ambient by a plasma etcher chuck band installed around the perimeter of the functional component layer, extending over a portion of the chuck base. An integrated circuit may be formed by installing the plasma etcher chuck band on the chuck of the plasma etch tool, and subsequently performing an etch process in the plasma etch tool on a semiconductor wafer containing the partially formed integrated circuit.

Abstract: The invention is directed towards methods and compositions for identifying the amount of ammonium acid in a buffered oxide etching composition. In buffered oxide etching compositions it is very difficult to measure the amount of ammonium acid because it has varying equilibriums and it is toxic so it hard to handle and sample. When used to manufacture microchips however, incorrect amounts of ammonium acid will ruin those chips. The invention utilizes a unique method of spectrographically measuring the ammonium acid when in contact with added chromogenic agents to obtain exact measurements that are accurate, immediate, and safe.

Abstract: An OES measuring unit outputs a spectroscopically measured value for each step at the end of or immediately after each step. A CD estimating unit obtains an estimated CD value for each step using a CD estimation model and a spectroscopically measured value received from an estimation model storage unit.

Abstract: A method of etching including providing a plurality of nanostructures extending away from a support, the support comprising a dielectric layer located between the plurality of nanowires, forming a patterned mask over a first portion of the plurality of nanostructures, such that a second portion of the plurality of nanostructures are exposed and are not located under the patterned mask, etching the second portion of the plurality of nanostructures to remove at least a portion of the patterned mask and the second portion of the plurality of nanostructures, monitoring at least one gaseous byproduct of the etching of the plurality of nanostructures during the etching of the plurality of nanostructures and stopping the etching on detecting that the dielectric layer is substantially removed.

Abstract: A method for etching a layer is provided. A substrate is provided in a chamber. An etch plasma for etching a layer on the substrate is generated. Light from a first region of the chamber is measured to provide a first signal. Light from a second region of the chamber is measured to provide a second signal. The first signal with the second signal are compared to determine an etch endpoint.

Abstract: Novel processing methods for production of high-refractive index contrast and low loss optical waveguides are disclosed. In one embodiment, a “channel” waveguide is produced by first depositing a lower cladding material layer with a low refractive index on a base substrate, a refractory metal layer, and a top diffusion barrier layer. Then, a trench is formed with an open surface to the refractory metal layer. The open surface is subsequently oxidized to form an oxidized refractory metal region, and the top diffusion barrier layer and the non-oxidized refractory metal region are removed. Then, a low-refractive-index top cladding layer is deposited on this waveguide structure to encapsulate the oxidized refractory metal region. In another embodiment, a “ridge” waveguide is produced by using similar process steps with an added step of depositing a high-refractive-index material layer and an optional optically-transparent layer.

Abstract: A plasma processing apparatus includes a stock unit, a processing unit, and an alignment chamber. The stock unit supplies and collects a conveyable tray formed with a plurality of housing holes in each of which a wafer is housed. In the processing chamber, plasma processing is executed on the wafers housed in the tray supplied from the stock unit. The alignment chamber is provided with a rotating table on which the tray before being subjected to the plasma processing is set to perform positioning of the wafers on the rotating table. A housing state determination unit of a control device determines whether or not the wafer is misaligned with respect the housing hole of the tray based on a height detected by height detecting sensors.

Abstract: A method of processing a plurality of packaged electronic chips being connected to one another in a common substrate is provided, wherein the method comprises etching the electronic chips, detecting information indicative of an at least partial removal of an indicator structure following an exposure of the indicator structure embedded within at least a part of the electronic chips and being exposed after the etching has removed chip material above the indicator structure, and adjusting the processing upon detecting the information indicative of the at least partial removal of the indicator structure.

Abstract: The present invention relates to a method of manufacturing a semiconductor device wherein etching is performed on films on a wafer using a plasma treatment apparatus. In the manufacturing method according to the present invention, a change in the difference between the emission intensities of a first wavelength component and a second wavelength component in plasma is monitored during etching. If the amount of change in the difference per unit time exceeds a predetermined threshold a given number of times in a row, then the flow rate of oxygen introduced to the plasma treatment apparatus is increased or, if the amount of change exceeding the predetermined threshold has not been seen, then the oxygen flow rate is set back to the original value thereof. This series of actions is repeated all the time during a set period of time.

Abstract: Exemplary embodiments are directed to controlling CD uniformity of a wafer by controlling trim time on temperature in a plasma processing system. The plasma processing system has a wafer support assembly including a plurality of independently controllable temperature control zones across a chuck and a controller that controls each temperature control zone. The controller receives process control and temperature data associated with at least one wafer previously processed in a plasma chamber of the plasma processing system, and critical device parameters of a current wafer to be processed in the plasma chamber. The controller calculates a target trim time and a target temperature profile of the current wafer based on the process control and temperature data, and the critical device parameters. The current wafer is trimmed during the target trim time while the temperature of each device die location is controlled based on the target temperature profile.

Abstract: A plasma etching method is provided for etching a substrate corresponding to an etching object within an etching apparatus that includes a supply condition adjustment unit for adjusting a supply condition for supplying etching gas to the substrate, a temperature adjustment unit for adjusting a temperature of the substrate placed on a stage along a radial direction, and a plasma generating unit for generating plasma within a space between the supply condition adjustment unit and the stage. The plasma etching method includes a control step in which the temperature adjustment unit controls the temperature of the substrate to be uniform within a substrate plane of the substrate, and an adjustment step in which the supply condition adjustment unit adjusts a concentration distribution of active species contained in the plasma generated by the plasma generation unit within the space above the substrate.

Abstract: A capping layer may be deposited over the active channel of a thin film transistor (TFT) in order to protect the active channel from contamination. The capping layer may affect the performance of the TFT. If the capping layer contains too much hydrogen, nitrogen, or oxygen, the threshold voltage, sub threshold slope, and mobility of the TFT may be negatively impacted. By controlling the ratio of the flow rates of the nitrogen, oxygen, and hydrogen containing gases, the performance of the TFT may be optimized. Additionally, the power density, capping layer deposition pressure, and the temperature may also be controlled to optimize the TFT performance.

Abstract: A method and apparatus for monitoring a target layer in a plasma process having a photoresist layer is provided. The method is useful in removing noise associated with the photoresist layer, and is particularly useful when signals associated with the target layer is weak, such as when detecting an endpoint for a photomask etching process.

Abstract: When forming high-k metal gate electrode structures in a semiconductor device on the basis of a basic transistor design, undue exposure of sensitive materials at end portions of the gate electrode structures of N-channel transistors may be avoided, for instance, prior to and upon incorporating a strain-inducing semiconductor material into the active region of P-channel transistors, thereby contributing to superior production yield for predefined transistor characteristics and performance.

Abstract: The invention is directed towards methods and compositions for identifying the amount of hydrofluoric acid in a buffered oxide etching composition. In buffered oxide etching compositions it is very difficult to measure the amount of hydrofluoric acid because it has varying equilibriums and it is toxic so it hard to handle and sample. When used to manufacture microchips however, incorrect amounts of hydrofluoric acid will ruin those chips. The invention utilizes a unique method of spectrographically measuring the hydrofluoric acid when in contact with added chromogenic agents to obtain exact measurements that are accurate, immediate, and safe.

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having a gate structure. An atomic layer deposition (ALD) process is performed to deposit a spacer around the gate structure. The ALD process includes alternating flowing ionized radicals of a first precursor across the semiconductor substrate and flowing a chlorosilane precursor across the semiconductor substrate to deposit the spacer.

Abstract: A method for etching a layer is provided. A substrate is provided in a chamber. An etch plasma for etching a layer on the substrate is generated. Light from a first region of the chamber is measured to provide a first signal. Light from a second region of the chamber is measured to provide a second signal. The first signal with the second signal are compared to determine an etch endpoint.

Abstract: Disclosed is a method for determining an endpoint of an etch process using optical emission spectroscopy (OES) data as an input. Optical emission spectroscopy (OES) data are acquired by a spectrometer attached to a plasma etch processing tool. The acquired time-evolving spectral data are first filtered and demeaned, and thereafter transformed into transformed spectral data, or trends, using multivariate analysis such as principal components analysis, in which previously calculated principal component weights are used to accomplish the transform. A functional form incorporating multiple trends may be used to more precisely determine the endpoint of an etch process. A method for calculating principal component weights prior to actual etching, based on OES data collected from previous etch processing, is disclosed, which method facilitates rapid calculation of trends and functional forms involving multiple trends, for efficient and accurate in-line determination of etch process endpoint.

Abstract: A method of manufacturing a plasmon generator includes the steps of: forming an etching mask on a dielectric layer; forming an accommodation part by etching the dielectric layer using the etching mask; and forming the plasmon generator to be accommodated in the accommodation part. The step of forming the etching mask includes the steps of: forming a patterned layer on an etching mask material layer, the patterned layer having a first opening that has a sidewall; forming a structure by forming an adhesion film on the sidewall, the structure having a second opening smaller than the first opening; and etching a portion of the etching mask material layer exposed from the second opening.

Abstract: An etching apparatus includes a process unit and a control unit. Emission intensity of plasma inside the process unit is obtained by an OES detector, a nonlinear regression analysis is performed by an etching control device to determine a regression formula. The nonlinear regression analysis is performed by using the emission intensity of the plasma obtained until a first time when the emission intensity of the plasma passes a peak, and a second time to be an etching end point is calculated by using the regression formula. The etching end point is calculated as a time when the emission intensity decreases for a predetermined value from the first time. The etching apparatus finishes an etching when the process reaches the etching end point. It is thereby possible to control the etching end point with high-accuracy.

Abstract: The method includes a step of forming a mask having an opening, for forming an opening in multiple insulating films, above a semiconductor substrate on which a member becoming a first insulating film, a member becoming a second insulating film being different from the member becoming the first insulating film, a member becoming a third insulating film, and a member becoming a fourth insulating film being different from the member becoming the third insulating film are stacked in this order; a first step of continuously removing the member becoming the fourth insulating film and the member becoming the third insulating film at a portion corresponding to the opening of the mask; and a second step of removing the member becoming the second insulating film, after the first step, at a portion corresponding to the opening of the mask.