Plasma Etching Patents (Class 438/9)
  • Publication number: 20080227225
    Abstract: The present invention relates to a method of manufacturing a semiconductor device wherein etching is performed on films on a wafer using a plasma treatment apparatus. In the manufacturing method according to the present invention, a change in the difference between the emission intensities of a first wavelength component and a second wavelength component in plasma is monitored during etching. If the amount of change in the difference per unit time exceeds a predetermined threshold a given number of times in a row, then the flow rate of oxygen introduced to the plasma treatment apparatus is increased or, if the amount of change exceeding the predetermined threshold has not been seen, then the oxygen flow rate is set back to the original value thereof. This series of actions is repeated all the time during a set period of time.
    Type: Application
    Filed: February 29, 2008
    Publication date: September 18, 2008
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Yasuhiko Ueda
  • Publication number: 20080206901
    Abstract: A pulsed plasma system with pulsed reaction gas replenish for etching semiconductor structures is described. In an embodiment, a portion of a sample is removed by applying a pulsed plasma etch process. The pulsed plasma etch process comprises a plurality of duty cycles, wherein each duty cycle represents the combination of an ON state and an OFF state of a plasma. The plasma is generated from a reaction gas, wherein the reaction gas is replenished during the OFF state of the plasma, but not during the ON state. In another embodiment, a first portion of a sample is removed by applying a continuous plasma etch process. The continuous plasma etch process is then terminated and a second portion of the sample is removed by applying a pulsed plasma etch process having pulsed reaction gas replenish.
    Type: Application
    Filed: February 22, 2007
    Publication date: August 28, 2008
    Inventors: TAE WON KIM, Kyeong-Tae Lee, Alexander Paterson, Valentin N. Todorow, Shashank C. Deshmukh
  • Publication number: 20080206900
    Abstract: A pulsed plasma system for etching semiconductor structures is described. In one embodiment, a portion of a sample is removed by applying a pulsed plasma process, wherein the pulsed plasma process comprises a plurality of duty cycles. The ON state of a duty cycle is of a duration sufficiently short to substantially inhibit micro-loading in a reaction region adjacent to the sample, while the OFF state of the duty cycle is of a duration sufficiently long to substantially enable removal of a set of etch by-products from the reaction region. In another embodiment, a first portion of a sample is removed by applying a continuous plasma process. The continuous plasma process is then terminated and a second portion of the sample is removed by applying a pulsed plasma process.
    Type: Application
    Filed: February 22, 2007
    Publication date: August 28, 2008
    Inventors: TAE WON KIM, Kyeong-Tae Lee, Alexander Paterson, Valentin N. Todorow, Shashank C. Deshmukh
  • Publication number: 20080179005
    Abstract: There is provided a plasma processing apparatus includes a lower electrode in a processing chamber on which a object to be processed is mounted; an upper electrode confronting the lower electrode; a first and a second high-frequency power supply for applying high-frequency powers respectively to the upper and the lower electrode; and an output controller for raising each of outputs from the high-frequency power supplies at least three times in a stepwise manner up to each of set levels for processing the object to be processed. The output controller adjusts each of rising times of the outputs from the high-frequency power supplies so that an output of the second high-frequency power supply is raised earlier than an output of the first high-frequency power supply while the outputs from the high-frequency power supplies are raised up to the set levels in a stepwise manner.
    Type: Application
    Filed: March 26, 2008
    Publication date: July 31, 2008
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Naoto SAGAE, Hiroshi Tsuchiya, Tsutomu Higashiura, Hideo Kato, Ryuji Ohtani
  • Patent number: 7399711
    Abstract: A method of controlling a recess etch process for a multilayered substrate having a trench therein and a column of material deposited in the trench includes determining a first dimension from a surface of the substrate to a reference point in the substrate by obtaining a measured net reflectance of at least a portion of the substrate including the trench, computing a modeled net reflectance of the portion of the substrate as a weighted incoherent sum of reflectances from n?1 different regions constituting the portion of the substrate, determining a set of parameters that provides a close match between the measured net reflectance and the modeled net reflectance, and extracting the first dimension from the set of parameters; computing an endpoint of the process as a function of the first dimension and a desired recess depth measured from the reference point; and etching down from a surface of the column of material until the endpoint is reached.
    Type: Grant
    Filed: November 1, 2002
    Date of Patent: July 15, 2008
    Assignee: Lam Research Corporation
    Inventors: Andrew J. Perry, Vijayakumar C. Venugopal
  • Publication number: 20080160652
    Abstract: A two-step method for etching a fuse window on a semiconductor substrate is provided. A semiconductor substrate having thereon a fuse interconnect-wire is formed in a dielectric film stack. The dielectric film stack includes a target dielectric layer overlying said fuse interconnect-wire, an intermediate dielectric layer and a passivation layer. A photoresist layer is formed on the passivation layer with an opening that defines said fuse window. A first dry etching process is performed to non-selectively etch the passivation layer and the intermediate dielectric layer through the opening thereby exposing the target dielectric layer. The thickness of the target dielectric layer after the first dry etching process is then measured. An APC-controlled second dry etching process is performed to etch a portion of the exposed target dielectric layer, thereby reliably forming the fuse window.
    Type: Application
    Filed: December 27, 2006
    Publication date: July 3, 2008
    Inventors: Shi-Jie Bai, Hong Ma
  • Patent number: 7393700
    Abstract: Methods of etching a semiconductor substrate may include providing a first gas that is chemically reactive with respect to the semiconductor substrate, and while providing the first gas, providing a second gas different than the first gas. More particularly, a molecule of the second gas may include a hydrogen atom, and the second gas may lower a temperature at which the first gas chemically reacts with the semiconductor substrate. The mixture of the first and second gases may be provided adjacent the semiconductor substrate to etch the semiconductor substrate.
    Type: Grant
    Filed: August 22, 2005
    Date of Patent: July 1, 2008
    Assignee: Samsung Electronic Co., Ltd.
    Inventors: Sun-Ghil Lee, Yu-Gyun Shin, Jong-Wook Lee, Deok-Hyung Lee, In-Soo Jung, Young-Eun Lee
  • Patent number: 7377992
    Abstract: A mask layer and a to-be-processed layer are irradiated with light to measure interference light formed of reflected lights from the mask layer and reflected lights from the to-be-processed layer. Thereafter, an interference component brought by the mask layer is removed from the waveform of the measured interference light, thereby calculating the waveform of the interference light brought by the to-be-processed layer. The thickness of the remaining to-be-processed layer is determined on the basis of the calculated waveform of the interference light and the thickness of the remaining to-be-processed layer is compared with a desired thickness thereof. In this way, an end point of processing on the to-be-processed layer is detected.
    Type: Grant
    Filed: January 27, 2006
    Date of Patent: May 27, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takeshi Yamashita, Takao Yamaguchi
  • Patent number: 7376479
    Abstract: A plasma processing method for processing a sample by using plasma on a lot unit basis, including: detecting plural kinds of information as monitor data relating to a processing state of the sample, using a plurality of sensors; selecting a detection time range of the monitor data thus detected; converting the monitor data within the selected detection time range into a converted signal; predicting a pattern shape of the sample based on the converted signal; calculating a correction quantity of a processing parameter, for decreasing a deviation between the predicted pattern shape and a standard value; and converting the correction quantity of a processing parameter obtained by the calculating operation when a kind of a next sample of a next lot is different from the sample, thereby to use a converted correction quantity of the processing parameter for a processing of the next sample.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: May 20, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Junichi Tanaka, Hiroyuki Kitsunai, Hideyuki Yamamoto, Shoji Ikuhara, Kazue Takahashi
  • Publication number: 20080090310
    Abstract: A substrate processing apparatus capable of completely removing an oxide layer that can cause defects in electronic devices, without lowering throughput of the apparatus. A process ship of the substrate processing apparatus includes a process module in which COR processing is performed on a wafer and another process module in which PHT processing is performed on a wafer. The latter process module includes a process module exhaust system through which volatile gases and other gases in a chamber are exhausted. This exhaust system includes an analysis unit communicated with a main exhaust pipe between the chamber and an APC valve and adapted to measure concentrations of the volatile gases in the exhausted gases and detect a termination of the PHT processing.
    Type: Application
    Filed: September 12, 2007
    Publication date: April 17, 2008
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Susumu SAITO
  • Patent number: 7354778
    Abstract: A method is provided for determining the end point during cleaning etching of processing chambers by means of plasma etching, which is used for carrying out coating or etching processes during the manufacture of semiconductor components. The invention provides a method for effectively and reliably determining the end point during cleaning etching of processing chambers. The end point is determined by monitoring the DC bias voltage on the plasma generator which is used for the plasma cleaning etching in the processing chamber in an evaluation unit. The plasma cleaning etching process is terminated by stopping the supply of the process gases in the gas supply unit and by switching off the plasma generator upon reaching a predetermined DC bias voltage value which corresponds to completion of the cleaning etching process.
    Type: Grant
    Filed: September 5, 2003
    Date of Patent: April 8, 2008
    Assignee: Infineon Technologies AG
    Inventors: Percy Heger, Tobias Hoerning, Ralf Otto
  • Publication number: 20080070328
    Abstract: A method of fabricating a semiconductor device according to an embodiment of the present invention includes: forming a film to be processed having a first film thickness on a semiconductor substrate; forming a region, within the film to be processed, having a second film thickness thinner than the first film thickness by processing a part of the film to be processed; processing the film to be processed having the region of the second film thickness formed therein by utilizing a dry etching method while a change in characteristic value of a plasma is monitored; detecting a first timing at which a member right under the region, within the film to be processed, which had the second film thickness before the processing performed by utilizing the dry etching method begins to be exposed in accordance with the change in characteristic value of the plasma during the processing performed by utilizing the dry etching method; and estimating a second timing right before a member right under a region, of the film to be pr
    Type: Application
    Filed: August 10, 2007
    Publication date: March 20, 2008
    Inventor: Mitsuhiro Omura
  • Patent number: 7329549
    Abstract: The present invention is a monitoring method of monitoring a change of a processing state of an object to be processed when a predetermined process is conducted to the object to be processed by using a processing unit. The method includes: a step of respectively setting constant response variables for two states before and after a processing state changes, the response variables being different from each other; and a step of conducting a multiple regression analysis about the response variables in order to produce a model expression, predictor variables of the multiple regression analysis being a plurality of detected data from a plurality of detectors provided in the processing unit. Then, the method includes: a step of actually obtaining a plurality of detected data from the plurality of detectors when the predetermined process is conducted to the object to be processed; and a step of estimating or monitoring a processing state by applying the obtained plurality of detected data to the model expression.
    Type: Grant
    Filed: September 2, 2003
    Date of Patent: February 12, 2008
    Assignee: Tokyo Electron Limited
    Inventor: Susumu Saito
  • Publication number: 20080032427
    Abstract: An ion analysis system to measure ion energy distribution at several points during a process of manufacturing a semiconductor circuit includes at least two ion flux sensors combined in a single system to measure an ion energy distribution function, each of the ion flux sensors having cells including an opening of 50 micrometers or less.
    Type: Application
    Filed: May 22, 2007
    Publication date: February 7, 2008
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Yung Hee Lee, Andrey Ushakov, Yuri Tolmachev, Vladimir Volynets, Won Ceak Pak, Vasily Pashkovskiy
  • Publication number: 20080026488
    Abstract: A method and apparatus for detecting the endpoint in a dry plasma etching system comprising a first electrode (e.g., upper electrode) and a second electrode (e.g., lower electrode) upon which a substrate rests is described. A direct current (DC) voltage is applied between the first electrode and a ring electrode surrounding the second electrode, and the DC current is monitored to determine the endpoint of the etching process. The DC current is affected by the impedance of the plasma, and therefore responds to many variations including, for example, the plasma density, electron/ion flux to exposed surfaces, the electron temperature, etc.
    Type: Application
    Filed: July 31, 2006
    Publication date: January 31, 2008
    Applicants: IBM Corporation, TOKYO ELECTRON LIMITED
    Inventors: Siddhartha Panda, Richard Wise, Lee Chen, Michael Sievers
  • Patent number: 7306955
    Abstract: A method of performing a double-sided process is provided. First, a wafer having a structural pattern disposed on the front surface is provided. Following that, a plurality of front scribe lines are defined on the structural pattern, and a filling layer is filled into the front scribe lines. Subsequently, the structural pattern is bonded to a carrier wafer with a bonding layer, and a plurality of back scribe lines are defined on the back surface of the wafer. Finally, the filling layer filled in the front scribe lines is removed.
    Type: Grant
    Filed: March 23, 2006
    Date of Patent: December 11, 2007
    Assignee: Touch Micro-System Technology Inc.
    Inventor: Chen-Hsiung Yang
  • Patent number: 7297287
    Abstract: An apparatus and method for detection of a feature etch completion within an etching reactor. The method includes determining a correlation matrix by recording first measured data regarding a first etch process over successive time intervals to form a first recorded data matrix, assembling a first endpoint signal matrix using target endpoint data for a specific etch process, performing a partial least squares analysis on the recorded data matrix and the first endpoint signal matrix to refine the recorded data matrix, and computing a correlation matrix based upon the refined recorded data matrix and the first endpoint signal matrix. The method further includes performing a second etch process to form a second recorded data matrix. The correlation matrix and the second recorded data matrix are analyzed to determine whether an endpoint of the second etch process has been achieved.
    Type: Grant
    Filed: March 25, 2002
    Date of Patent: November 20, 2007
    Assignee: Tokyo Electron Limited
    Inventors: David Fatke, Hongyu Yue
  • Patent number: 7297560
    Abstract: The present invention presents a method for detecting an endpoint of an etch process for etching a substrate in plasma processing system (1) comprising: etching the substrate; measuring at least one endpoint signal; generating at least one filtered endpoint signal by filtering the at least one endpoint signal, wherein the filtering comprises applying a Savitsky Golay filter (12) to the at least one endpoint signal; and determining (14) an endpoint of the etch process from the at least one filtered endpoint signal.
    Type: Grant
    Filed: October 31, 2003
    Date of Patent: November 20, 2007
    Assignee: Tokyo Electron Limited
    Inventor: Hongyu Yue
  • Patent number: 7286948
    Abstract: Methods for determining characteristics of a plasma are provided. In one embodiment, a method for determining characteristics of a plasma includes obtaining metrics of current and voltage information for first and second waveforms coupled to a plasma at different frequencies, determining at least one characteristic of the plasma using the metrics obtained from each different frequency waveform. In another embodiment, the method includes providing a plasma impedance model of a plasma as a function of frequency, and determining at least one characteristic of a plasma using model. In yet another embodiment, the method includes providing a plasma impedance model of a plasma as a function of frequency, measuring current and voltage for waveforms coupled to the plasma and having at least two different frequencies, and determining ion mass of a plasma from model and the measured current and voltage of the waveforms.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: October 23, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Steven C. Shannon, Daniel J. Hoffman, Jeremiah T. P. Pender, Tarreg Mawari
  • Patent number: 7258838
    Abstract: A solid state nanopore device including two or more materials and a method for fabricating the same. The device includes a solid state insulating membrane having an exposed surface, a conductive material disposed on at least a portion of the exposed surface of the solid state membrane, and a nanopore penetrating an area of the conductive material and at least a portion of the solid state membrane. During fabrication a conductive material is applied on a portion of a solid state membrane surface, and a nanopore of a first diameter is formed. When the surface is exposed to an ion beam, material from the membrane and conductive material flows to reduce the diameter of the nanopore. A method for evaluating a polymer molecule using the solid state nanopore device is also described. The device is contacted with the polymer molecule and the molecule is passed through the nanopore, allowing each monomer of the polymer molecule to be monitored.
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: August 21, 2007
    Assignee: President and Fellows of Harvard College
    Inventors: Jiali Li, Derek M. Stein, Gregor M. Schurmann, Gavin M. King, Jene Golovchenko, Daniel Branton, Michael Aziz
  • Patent number: 7244369
    Abstract: “A process for fabricating active and passive, polymer-based components for use in integrated optics. As a result of this process, active and passive optoelectronic components of a high quality having a high level of integration and high packing density are fabricated. A patternable polymer resist layer of a high quality is deposited onto an optoelectronic component. An etching mask is used in conjunction with a high-grade anisotropic deep etching to produce a pattern, which is filled with monomers through gas-phase or liquid-phase diffusion. The optical properties of the optical component can be selectively changed as a function of the type of monomers used for the diffusion, as well as of the temperature and application time. The process makes it possible to increase the packing density of future integrated monomode optics and simultaneously produce large quantities in a cost-effective manner.
    Type: Grant
    Filed: July 5, 1997
    Date of Patent: July 17, 2007
    Assignee: Deutsche Telekom AG
    Inventor: Hans Wilfried Peter Koops
  • Patent number: 7211196
    Abstract: A method and system for determining a substrate type during a seasoning process is presented. An optical signal is acquired from a process in a plasma processing system, and the optical signal is compared to a pre-determined threshold value. Depending upon the comparison, the substrate type is determined to be of a correct type, or an incorrect type.
    Type: Grant
    Filed: March 26, 2004
    Date of Patent: May 1, 2007
    Assignee: Tokyo Electron Limited
    Inventors: Hieu A. Lam, Hongyu Yue
  • Patent number: 7208326
    Abstract: An edge protection process for semiconductor device fabrication includes forming a protective layer on the circumferential edge region of a semiconductor substrate. The semiconductor substrate is placed in a plasma atmosphere and trench structures, such as deep trenches and shallow trench isolation structures are etched in the substrate. The protective layer substantially prevents the etching of the circumferential edge region, such that the formation of black silicon is substantially minimized during the etching process.
    Type: Grant
    Filed: October 18, 2004
    Date of Patent: April 24, 2007
    Inventors: Michael Rennie, Jon Davis, Robert Fuller, Franz Hagl
  • Patent number: 7204934
    Abstract: A method for processing recess etch operations in substrates is provided including forming a hard mask over the substrate and etching a trench in the substrate using the hard mask, and forming a dielectric layer over the hard mask and in the trench, where the dielectric layer lines the trench. A conductive material is then applied over the dielectric layer such that a blanket of the conductive material lies over the hard mask and fills the trench, and the conductive material is etched to substantially planarize the conductive material. The etching of the conductive material triggers an endpoint just before all of the conductive material is removed from over the dielectric layer that overlies the bard mask. The conductive material is recess etched to remove the conductive material over the dielectric layer that overlies the hard mask and removes at least part of the conductive material from within the trench.
    Type: Grant
    Filed: October 31, 2001
    Date of Patent: April 17, 2007
    Assignee: Lam Research Corporation
    Inventors: Linda Braly, Vahid Vahedi, Erik Edelberg, Alan Miller
  • Patent number: 7192505
    Abstract: There is provided by this invention a wafer probe for measuring plasma and surface characteristics in plasma processing environment that utilizes integrated sensors on a wafer substrate. A microprocessor mounted on the substrate receives input signals from the integrated sensors to process, store, and transmit the data. A wireless communication transceiver receives the data from the microprocessor and transmits information outside of the plasma processing system to a computer that collects the data during plasma processing. The integrated sensors may be dual floating Langmuir probes, temperature measuring devices, resonant beam gas sensors, or hall magnetic sensors. There is also provided a self-contained power source that utilizes the plasma for power that is comprised of a topographically dependent charging device or a charging structure that utilizes stacked capacitors.
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: March 20, 2007
    Assignee: Advanced Plasma, Inc.
    Inventors: Gregory A. Roche, Leonard J. Mahoney, Daniel C. Carter, Steven J. Roberts
  • Patent number: 7181306
    Abstract: A method of operating a plasma etcher wherein gas is introduced into the etcher at a substantially higher rate than a previous standard rate for a desired etch selectivity, and the throttle valve's open value is set to a substantially greater open value than a previous standard open value for the desired etch selectivity. The method may also include introducing the gas at a lower pressure than the pressure of the previous standard pressure for a desired etch selectivity.
    Type: Grant
    Filed: September 17, 2004
    Date of Patent: February 20, 2007
    Assignee: Intersil Americas, Inc.
    Inventor: David A. DeCrosta
  • Patent number: 7169625
    Abstract: A method and apparatus for automatic determination of semiconductor plasma chamber matching a source of fault are provided. Correlated plasma attributes are measured for process used for calibration both in a chamber under study and in a reference chamber. Principal component analysis then is performed on the measured correlated attributes so as to generate steady principal components and transitional principal components; and these principal components are compared to reference principal components associated with a reference chamber. The process used for calibration includes a regular plasma process followed by a process perturbation of one process parameter. Similar process perturbation runs are conducted several times to include different perturbation parameters. By performing inner products of the principal components of chamber under study and the reference chamber, matching scores can be reached. Automatic chamber matching can be determined by comparing these scores with preset control limits.
    Type: Grant
    Filed: July 25, 2003
    Date of Patent: January 30, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Matthew F. Davis, Lei Lian
  • Patent number: 7158848
    Abstract: A plasma processing apparatus for processing a sample within a vacuum vessel, including: a plurality of sensors for detecting plural kinds of information relating to a processing state of the sample as monitor data; data selecting means for selecting a detection time range of the monitor data thus detected which is used for monitoring the plasma processing apparatus; a signal filter for converting the monitor data within the selected detection time range into an effective signal; a model expression unit for generating a predicted value of a patterned physical-shape of a sample based on the effective signal; and a display screen for displaying the patterned physical-shape predicted value; wherein the display screen displays the patterned physical-shape predicted value without measuring a patterned shape after processing of the sample.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: January 2, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Junichi Tanaka, Hiroyuki Kitsunai, Hideyuki Yamamoto, Shoji Ikuhara, Kazue Takahashi
  • Patent number: 7139632
    Abstract: A method for enhancing a process and profile simulator algorithm predicts the surface profile that a given plasma process will create. An energetic particle is first tracked. The ion fluxes produced by the energetic particle are then recorded. A local etch rate and a local deposition rate are computed from neutral fluxes, surface chemical coverage, and surface material type that are solved simultaneously.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: November 21, 2006
    Assignee: Lam Research Corporation
    Inventors: David Cooperberg, Vahid Vahedi
  • Patent number: 7132302
    Abstract: A method of increasing the cell retention capacity of a silicon nitride read-only-memory on a wafer. The method includes carrying out a baking process after performing the last plasma treatment of the wafer but before a wafer sort test.
    Type: Grant
    Filed: May 17, 2004
    Date of Patent: November 7, 2006
    Assignee: Macronix International Co., Ltd.
    Inventors: Kuen-Chi Chuang, Chen-Chin Liu, Jiong-Zhong Chen
  • Patent number: 7129104
    Abstract: Devices and techniques for coupling radiation to intraband quantum-well semiconductor sensors that are insensitive to the wavelength of the coupled radiation. At least one reflective surface is implemented in the quantum-well region to direct incident radiation towards the quantum-well layers.
    Type: Grant
    Filed: April 8, 2003
    Date of Patent: October 31, 2006
    Assignee: California Institute of Technology
    Inventors: Sarath D. Gunapala, Sumith V. Bandara, John K. Liu
  • Patent number: 7118926
    Abstract: A method for optimizing a seasoning recipe for a dry etch process. The method includes setting a critical value of reproducibility, a main etch recipe, and a preliminary seasoning recipe. A test wafer is then etched using the preliminary seasoning recipe in a dry etch chamber. Next, a main etch process is performed with respect to at least 10 run wafers in the dry etch chamber using the main etch recipe and an end-point detection time for each wafer is determined. An initial dispersion and a standard deviation are then determined using the determined end-point detection times. The critical value of reproducibility is then compared to the initial dispersion. If the initial dispersion is equal to or less than the critical value of reproducibility, the preliminary seasoning recipe is used as the seasoning recipe, otherwise the preliminary seasoning recipe is modified and the process is repeated until an optimal seasoning recipe is determined.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: October 10, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong Cho, Chang-Jin Kang, Kyeong-Koo Chi, Cheol-Kyu Lee, Hye-Jin Jo
  • Patent number: 7094613
    Abstract: Embodiments of the invention generally relate to a method for etching in a processing platform (e.g. a cluster tool) wherein robust pre-etch and post-etch data may be obtained in-situ. The method includes the steps of obtaining pre-etched critical dimension (CD) measurements of a feature on a substrate, etching the feature; treating the etched substrate to reduce and/or remove sidewall polymers deposited on the feature during etching, and obtaining post-etched CD measurements. The CD measurements may be utilized to adjust the etch process to improved the accuracy and repeatability of device fabrication.
    Type: Grant
    Filed: October 21, 2003
    Date of Patent: August 22, 2006
    Assignee: Applied Materials, Inc.
    Inventors: David Mui, Wei Liu, Hiroki Sasano
  • Patent number: 7067333
    Abstract: A method for controlling a process includes determining incoming state information associated with the process. A plurality of control models associated with the process is provided. A confidence metric is determined for each of the control models based on the incoming state information. The one of the plurality of control models having the highest associated confidence metric is selected. A control action for determining at least one parameter in an operating recipe used to implement the process is generated using the selected control model. A system includes a process tool and a process controller. The process tool is configured to process a workpiece in accordance with an operating recipe.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: June 27, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Alexander J. Pasadyn, Matthew A. Purdy
  • Patent number: 7067432
    Abstract: A new methodology of monitoring process drift and chamber seasoning is presented based on the discovery of the strong correlation between chamber surface condition and free radical density in a plasma. Lower free radical density indicates either there is a significant process drift in the case of production wafer etching or that the chamber needs more seasoning before resuming production wafer etching. Free radical density in the plasma is monitored through measuring the emission intensities of free radicals in the plasma by an optical spectrometer. A timely detection of the extent of process drift and chamber seasoning can help to minimize the chamber downtime and improve its throughput significantly. Such method can also be implemented in existing production wafer etching or chamber seasoning practices in an in-situ, real-time, and non-intrusive manner.
    Type: Grant
    Filed: June 26, 2003
    Date of Patent: June 27, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Songlin Xu, Thorsten Lill
  • Patent number: 7058467
    Abstract: A monitor data acquisition section acquires a plurality of monitor data relating to a processing state of one sample in a processing apparatus, via sensors. A data selection section selects monitor data belonging to an arbitrary processing division included in a plurality of processing divisions for the sample, from among the plurality of monitor data. A monitoring signal generation section generates monitoring signals based on the monitor data belonging to the arbitrary processing division selected by the data selection section. A display setting controller displays a plurality of monitoring signals obtained with respect to samples processed in the processing apparatus, on a display section in a time series manner.
    Type: Grant
    Filed: November 15, 2004
    Date of Patent: June 6, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Junichi Tanaka, Hiroyuki Kitsunai, Hideyuki Yamamoto, Shoji Ikuhara, Kazue Takahashi
  • Patent number: 7033904
    Abstract: A semiconductor device includes a first insulation layer including a first conductor pattern, a second insulation layer formed on the first insulation layer and including a second conductor pattern, and a third conductor pattern formed on the second insulation layer, wherein there is formed a first alignment mark part in the first insulation layer by a part of the first conductor pattern, the third conductor pattern is formed with a second alignment mark part corresponding to the first alignment mark part, the first and second alignment marks forming a mark pair for detecting alignment of the first conductor pattern and the third conductor pattern, the second conductor pattern being formed in the second insulation layer so as to avoid the first alignment mark part.
    Type: Grant
    Filed: December 2, 2004
    Date of Patent: April 25, 2006
    Assignee: Fujitsu Limited
    Inventors: Katsuyoshi Kirikoshi, Eiichi Kawamura
  • Patent number: 7029593
    Abstract: A method for controlling CD of etch process defines difference between designed dimension and etched dimension as dimensional displacement and defines target value of the dimensional displacement. A plurality of samples are prepared in each group having different exposure ratios. The plurality of samples of each group are etched until etch end point is detected and then over-etched for uniform time interval after detecting the etch end point. Using etch end point and over-etch time, correlation function of the over-etch time to the etch end point time is determined and the over-etch time to the etch end point is determined using the correlation function.
    Type: Grant
    Filed: October 14, 2003
    Date of Patent: April 18, 2006
    Assignee: Samsung Electronics Co., Ltd,
    Inventors: Myeong-Cheol Kim, Yong-Hoon Kim, Jeong-Yun Lee
  • Patent number: 7026173
    Abstract: A mask layer and a to-be-processed layer are irradiated with light to measure interference light formed of reflected lights from the mask layer and reflected lights from the to-be-processed layer. Thereafter, an interference component brought by the mask layer is removed from the waveform of the measured interference light, thereby calculating the waveform of the interference light brought by the to-be-processed layer. The thickness of the remaining to-be-processed layer is determined on the basis of the calculated waveform of the interference light and the thickness of the remaining to-be-processed layer is compared with a desired thickness thereof. In this way, an end point of processing on the to-be-processed layer is detected.
    Type: Grant
    Filed: June 2, 2004
    Date of Patent: April 11, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takeshi Yamashita, Takao Yamaguchi
  • Patent number: 7026172
    Abstract: A high density plasma chemical vapor deposition (HDP-CVD) process is used to deposit silicon dioxide in trenches of various widths. The thickness of the silicon dioxide filling both narrow and wide trenches is made more uniform by reducing an HDP-CVD etch to deposition ratio. The lowered etch to deposition ratio is achieved by lowering a ratio of oxygen to silane gas, by lowering the power of a high frequency bias signal, and by lowering the total gas flow rate.
    Type: Grant
    Filed: October 22, 2001
    Date of Patent: April 11, 2006
    Assignee: ProMOS Technologies, Inc.
    Inventors: Tai-Peng Lee, Chuck Jang
  • Patent number: 7005305
    Abstract: A technique is provided that may be used to improve optical endpoint detection in a plasma etch process. A semiconductor structure is manufactured that includes at least one electrical device. The technique is adapted for forming a signal layer on or in a wafer, wherein the signal layer comprises a chemical element that causes a characteristic optical emission when coming into contact with an etch plasma. The chemical element does not have a primary influence on the electrical properties of the electrical device. The signal layer is for use in a plasma etch process to detect a plasma etch endpoint if the characteristic optical emission is detected. The signal layer may be patterned and may be incorporated into a stop layer.
    Type: Grant
    Filed: May 29, 2003
    Date of Patent: February 28, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Gunter Grasshoff, Christoph Schwan, Matthias Schaller
  • Patent number: 7001784
    Abstract: A method of fabricating final spacers having a target width comprises the following steps. Initial spacers, each having an initial width that is less than the target width, are formed over the opposing side walls of a gate electrode portion. The difference between the initial spacer width and the target width is determined. A second spacer layer having a thickness equal to the determined difference between the initial width of the initial spacers and the target width is formed upon the initial spacers and the structure. The second spacer layer is etched to leave second spacer layer portions extending from the initial spacers to form the final spacers.
    Type: Grant
    Filed: September 19, 2003
    Date of Patent: February 21, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Jyh-Shiou Hsu, Pin-Yi Hsin, Jeng Yu
  • Patent number: 6998277
    Abstract: A method of planarizing a spin-on material layer is provided. A substrate having a plurality of openings thereon is provided. A spin-on material layer is formed on the substrate such that the openings are completely filled. A plasma etching process is carried out to remove a portion of the spin-on material layer and expose the substrate surface. During the plasma etching process, the substrate is cooled to maintain an etching selectivity between the spin-on material layer on the substrate surface and the spin-on material layer within the openings so that a planar spin-on material layer is ultimately obtained.
    Type: Grant
    Filed: September 15, 2004
    Date of Patent: February 14, 2006
    Assignee: ProMOS Technologies, Inc.
    Inventors: Jefferson Lu, Nien-Yu Tsai, Shu-Ching Yang
  • Patent number: 6989281
    Abstract: A cleaning method for a semiconductor device manufacturing apparatus includes a process of forming a film on a subject piece in a processing chamber, applying light having a predetermined wavelength to a monitoring section to indirectly monitor a thickness of a film formed on the subject piece, introducing cleaning gas capable of removing a substance deposited on the monitoring section into the processing chamber, measuring a reflection light which is the application light reflected near the monitoring section, measuring an amount of a substance corresponding to a thickness of a film deposited on the monitoring section based on a measurement result of the reflection light; and introducing, into the processing chamber, a cleaning gas which can remove the substance on the monitoring section until a measurement value of the amount of the substance on the monitoring section becomes zero.
    Type: Grant
    Filed: October 5, 2004
    Date of Patent: January 24, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihito Yamamoto, Takashi Nakao, Yuuichi Mikata, Yoshitaka Tsunashima
  • Patent number: 6982175
    Abstract: An improved method for determining endpoint of a time division multiplexed process by monitoring an identified region of a spectral emission of the process at a characteristic process frequency. The region is identified based upon the expected emission spectra of materials used during the time division multiplexed process. The characteristic process frequency is determined based upon the duration of the steps in the time division multiplexed process. Changes in the magnitude of the monitored spectra indicate the endpoint of processes in the time division multiplexed process and transitions between layers of materials.
    Type: Grant
    Filed: February 2, 2004
    Date of Patent: January 3, 2006
    Assignee: Unaxis USA Inc.
    Inventors: David Johnson, Russell Westerman
  • Patent number: 6979577
    Abstract: Concerning a plurality of wafers which compose one lot, amounts of misalignment between alignment marks of these wafers and alignment patterns transferred on photoresists are measured in advance, and then, a mutual relation between a thickness of an interlayer dielectric film and a value of Wafer Scaling is calculated. When exposure is actually executed, first, an interlayer dielectric film is formed on the alignment marks in a lot and planarized. After that, the thickness of the interlayer dielectric film after planarization is measured. The value of the Wafer Scaling is estimated from an average value of the thicknesses of the interlayer dielectric films in the lot and the above-mentioned mutual relation. Then, photoresists are coated on the interlayer dielectric films in the lot, and the photoresists are exposed while the correction is executed so as to compensate the value of the Wafer Scaling.
    Type: Grant
    Filed: October 10, 2003
    Date of Patent: December 27, 2005
    Assignee: FASL LLC
    Inventor: Tohru Higashi
  • Patent number: 6976782
    Abstract: In a plasma processing system, a method of determining the temperature of a substrate is disclosed. The method includes positioning the substrate on a substrate support structure, wherein the substrate support structure includes a chuck. The method further includes creating a temperature calibration curve for the substrate, the temperature calibration curve being created by measuring at least a first substrate temperature with an electromagnetic measuring device, and measuring a first chuck temperature with a physical measuring device during a first isothermal state. The method also includes employing a measurement from the electromagnetic measurement device and the temperature calibration curve to determine a temperature of the substrate during plasma processing.
    Type: Grant
    Filed: November 24, 2003
    Date of Patent: December 20, 2005
    Assignee: Lam Research Corporation
    Inventor: Robert J. Steger
  • Patent number: 6977184
    Abstract: A method for fabricating a spacer of a gate structure is provided. The method performing a first etch process implementing a first etchant gas. The first etch process is configured to implement an interferometry endpoint (IEP) detection method to detect a removal of a portion of a spacer layer having a specific thickness from over the surface of the substrate, thus leaving a thin spacer layer. The method further includes performing a second etch process for a predetermined period of time implementing a second etchant gas. The second etch process is configured to remove the thin spacer layer, leaving the spacer for the gate structure.
    Type: Grant
    Filed: October 31, 2001
    Date of Patent: December 20, 2005
    Assignee: Lam Research Corporation
    Inventors: Wen-Ben Chou, Shih-Yuan Cheng, Wayne Tu
  • Patent number: 6969619
    Abstract: A method of endpoint detection during plasma processing of a semiconductor wafer comprises processing a semiconductor wafer using a plasma, detecting radiation emission from the plasma during the semiconductor processing, and tracking data points representing changes in spectra of the radiation as a function of time during the semiconductor processing. At any point prior to or during processing a plurality of profiles are provided, each profile representing a different processing condition affecting detection of the desired plasma processing endpoint of the semiconductor wafer. After selecting a desired profile, a first set of parameters are input, representing simplified values for determining when changes in spectra of the radiation indicate that plasma processing of the semiconductor wafer reaches a desired endpoint.
    Type: Grant
    Filed: February 18, 2003
    Date of Patent: November 29, 2005
    Assignee: Novellus Systems, Inc.
    Inventor: Jaroslaw W. Winniczek
  • Patent number: 6967109
    Abstract: A method and apparatus for measuring a potential difference for plasma processing with a plasma processing apparatus that processes a sample by introducing a gas into a vacuum chamber and generates plasma. A light-emitting portion is formed on a measurement-use sample of the sample to be processed and a current flows into the light-emitting portion according to a potential difference that has been generated across the light-emitting portion. An intensity of light emitted from the light-emitting portion according to a predetermined light intensity is measured and a potential difference on the measurement-use sample according to a predetermined light intensity is measured.
    Type: Grant
    Filed: July 1, 2004
    Date of Patent: November 22, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Tatehito Usui, Tetsuo Ono, Ryoji Nishio, Kazue Takahashi, Nobuyuki Mise