Abstract: A computer implemented method, apparatus, and computer usable program code for detecting monotonicity. A determination is made as to whether a function that is assumed to be monotonic will remain monotonic after performing an operation in response to receiving the operation. The operation is allowed to be performed in response to a determination that the function will remain monotonic after performing the operation.

Abstract: A stochastic processor of the present invention includes a fluctuation generator configured to output an analog quantity having a fluctuation, a fluctuation difference calculation means configured to output fluctuation difference data with an output of the fluctuation generator added to analog difference between two data, a thresholding unit configured to perform thresholding on an output of the fluctuation difference calculation means to thereby generate a pulse, and a pulse detection means configured to detect the pulse output from the thresholding unit.

Abstract: A simplified transaction data management system using automatic calculation with multiple editable fields is provided. The system enables a user to manage transactions with a simplified interface, with multiple editable fields and automatic calculation of other fields based on mathematical relations with inputs that are received in any of the other editable fields. For example, either net amounts subject to a tax or gross amounts including the tax may be entered for a transaction, and the other value is automatically computed and displayed. Either value may subsequently be re-entered, and the other value may again automatically be computed and displayed, replacing the earlier input and output.

Abstract: Random number generator having a transistor that generates an analog random telegraph signal (RTS) having a first or second signal state, a RTS detection unit for detecting the RTS generated by the transistor, a RTS sampling unit that supersamples the RTS detected by the RTS detection unit and thus generates a digitized RTS, a signal state duration detection unit that determines, from the digitized RTS, a first time variable representing the time duration of at least one first signal state of the generated RTS and a second time variable representing the time duration of at least one second signal state of the generated RTS, and a random number conversion unit, which is coupled to the signal state duration detection unit, and that generates a random number from the first time variable and the second time variable.

Abstract: For sequentially input data string, the outliner and the change point are detected through calculation of the outlier score and the change point score by combining a time-series model learning device to learn the generation mechanism of the read data series as the time-series statistic model, a score calculator to calculate the outlier score of each data based on the time-series model parameter and the input data, a moving average calculator to calculate the moving average of the outlier score, a time-series model learning device to learn the generation mechanism of the moving average series as the time-series statistic model and the above score calculator that further calculates the outlier score of the moving average based on the moving average of the outlier score and outputs the result as the change point score of the original data.

Abstract: A stochastic processor and a stochastic computer comprises a fluctuation generator configured to generate and output analog quantity having fluctuation comprised of chaos of tent mapping, a mixer configured to output a fluctuation superposed signal with the analog quantity output from the fluctuation generator superposed on an input signal represented by analog quantity and a thresholding unit configured to perform thresholding on the fluctuation superposed signal output from the mixer to generate and output a pulse.

Abstract: A quantum noise random number generator system that employs quantum noise from an optical homodyne detection apparatus is disclosed. The system utilizes the quantum noise generated by splitting a laser light signal using a beamsplitter having four ports, one of which receives one of which is receives the laser light signal, one of which is connected to vacuum, and two of which are optically coupled to photodetectors. Processing electronics process the difference signal derived from subtracting the two photodetector signals to create a random number sequence. Because the difference signal associated with the two photodetectors is truly random, the system is a true random number generator.

Abstract: A synthesizer is disclosed and is digitally tuned and locked in a measured frequency. The synthesizer uses both the dual voltage control oscillator, each operating over less than an octave, in combination with the microwave doublers to produce a multi-octave RF output with low having low harmonics and free of spurious output signals thereon. The synthesizer uses a sampling downconverter that would, without the benefits of the present invention, produce an ambiguous IF output signal that is translated from the VCO microwave frequency. The ambiguity of the sampling downconverter is corrected by using in-phase and quadrature components of the IF output signal produced by the downconverter along with an Arc Tan to generate a series of digital phase data that is compared against a known reference to eliminate the ambiguity of the VCO frequency. The synthesizer further uses at least one clocking source having an output that is selectively filtered to avoid singularity problems normally plaguing downconverters.

Abstract: In a method for determining a minimum value of an optimization function under constraints given by equations, a set of points which satisfy the constraints is regarded as a Riemannian manifold within a finite-dimensional real-vector space, the Riemannian manifold is approached from an initial position within the real-vector space. An exponential map regarding a geodesic line equation with respect to a tangent vector on the Riemannian manifold ends at a finite order, an approximate geodesic line is generated as a one-dimensional orbit. An approximate parallel-translation is performed on the tangent vector on the Riemannian manifold and on the orbit generated in the orbit generating step by finite-order approximation of the exponential map regarding the parallel translation of the tangent vector.

Abstract: A generator of random numbers by a flip-flop having a data input receiving a first signal at a first frequency comprised in a predetermined range and the instantaneous value of which is conditioned by a disturbing signal, and having a clock input receiving a second signal at a second predetermined frequency, smaller than the first one, said second signal passing through a delay element giving it a delay greater than or equal to the maximum period of the first signal.

Abstract: A method of producing a uniform duty cycle output from a random bit source. The method includes testing the duty cycle of said random bit source; varying the output voltage of a voltage source if the duty cycle is not substantially fifty percent; and iteratively altering the output voltage of the voltage source until said duty cycle is substantially fifty percent.

Abstract: A random-bit sequence generator includes a biasing circuit, a source of a noisy voltage signal biased by the biasing circuit, an amplification stage generating an amplified signal representative of the sole non-zero-frequency (AC) component of the noisy voltage signal and an output stage electrically in cascade to the amplification stage that generates a random bit sequence in function of the amplified signal. The generator also filters the undesired low-frequency disturbance components because the amplification stage comprises an input low-pass filter that feeds the zero- (DC) component of the noisy voltage signal to one of the inputs of a differential amplifier, to another input of which is fed the non-filtered noisy voltage signal.

Abstract: A resonant protection kit for a power supply includes a circuit adapted to perform analysis, determinative, and counter functions. The circuit collects a divided voltage on a capacitor to calculate an effective voltage value and uses fundamental and non-fundamental waveforms to calculate an effective total current value of the capacitor. The circuit is selectively actuated to cut off the capacitor from a power system or adjust its impedance characteristic for protection if an abnormal voltage or current is sensed.

Abstract: A method and circuit is presented for generating a random bit stream based on thermal noise of a Complementary Metal Oxide Semiconductor (CMOS) device. A circuit implementing the invention preferably includes at least a pair of identically implemented thermal noise generators whose outputs feed a differential amplifier. The differential amplifier measures and amplifies the difference between the noise signals. A sampling circuit compares the difference with a threshold value that is selected to track with process/voltage/temperature variations of the noise generator circuits to output a binary bit having a bit value determined according to the polarity of the noise difference signal relative to the threshold value. The sampling circuit may be clocked to generate a random bit stream.

Abstract: The improved AES processing method provides an efficient alternative to both Mips intensive multiplication and to conventional table lookup, used to multiply terms over a Galois field (GF). The improved method takes advantage of the fact that in the GF, any non zero element X can be represented by a power of a primitive element P. The improved method thereby results in a 2 by 256 table. The log base P of the terms being multiplied are looked up and summed, and the anti-log of the sum is looked up in the same table.

Abstract: A calculating circuit and a method for generating an output signal representing an output number approximating an N-th root and/or a reciprocal of an input number represented by an input signal are described. The calculating circuit includes a subtractor circuit, an integrator circuit, and a multiplier circuit. The subtractor circuit responsive to a first signal and a feedback signal and configured for generating an error signal representing a difference between the first signal and the feedback signal. The integrator circuit responsive to the error signal and configured for computing the output signal. The multiplier circuit responsive to the output signal and configured for generating a feedback signal.

Abstract: A low cost white noise generator. An oscillator provides a signal to an analog-to-digital (AID) converter for digitizing. A bit-order reversal circuit reverses the order of the received bits, wherein the reversal circuit provides bits having an order ranging from LSB to MSB. A digital-to-analog (D/A) converter subsequently converts the reversed digital signal back to an analog signal, which is a white noise signal due to the random nature of reversing the bits provided by the A/D converter.

Abstract: An apparatus for generating random numbers includes a source for generating random quantum phenomena, a detector to detect instances of the random quantum phenomena, and a recorder to record the instances of the random quantum phenomena for use in generating random numbers.

Abstract: A programmable analog system architecture and method thereof are described. The analog system architecture and method introduce a single chip solution that contains a set of tailored analog blocks and elements that can be configured and reconfigured in different ways to implement a variety of different analog functions. The architecture includes an array of analog blocks, including continuous time blocks and different types of switched capacitor blocks. The analog blocks can be electrically coupled to each other in different combinations to perform different analog functions. Each analog block includes analog elements that have changeable characteristics that can be specified according to the function to be performed. The architecture thereby facilitates the design of customized chips at less time and expense.

Abstract: An arithmetic unit for correcting a detection output of a detector for a mechanical error of the detector in accordance with a predetermined input/output characteristic (straight line) is provided. When a digital output of the detector exceeds an upper limit value stored in a main memory, the digital output becomes a new upper limit value. From a virtual line which passes through the new upper limit value and which is parallel to the straight line, a new lower limit value is obtained. A corrected operation output is obtained in accordance with a new input/output characteristic of the detector based on the new upper limit value and the new lower limit value. Thus, the correction accuracy is improved.

Abstract: A method of generating random numbers comprises: generating a first noise and passing the first noise through a first high pass filter which removes a periodic component contained in the first noise to produce a first noise signal having 1/f characteristic; generating a second noise and passing the second noise through a second high pass filter which removes a periodic component contained in the second noise to produce a second noise signal having 1/f characteristic; supplying the first and second noise signals to a differential circuit to derive a different signal between the first noise signal and said second noise signal; and generating, from the different signal, random numbers which do not have a periodicity due to 1/f characteristics of the first and second noise signals.

Abstract: A method for solving a wide variety of linear partial differential equations by exploiting the normally undesirable parasitic resistances present in flexible digital switching components. The terminal relationships of these field programmable interconnect devices can be manipulated under program control to directly mimic the nodal relationships defined in finite difference method models of a partial difference equation problem. Adding analog-to-digital/digital-to-analog converters (“ADCs/DACs”) to automate the solution process can extend the method of analog equation solving. It is also possible to segment larger problems using this approach, feeding sections into the device and injecting/capturing voltages as appropriate to produce an overall solution that will eventually converge after a number of presentation/solution sub-cycles.

Abstract: According to one embodiment, a programmable random bit source is disclosed. The programmable random bit source includes a latch having a data input, a bias input and a clock input. In addition, the programmable random bit source includes a programmable voltage source coupled to the bias input of the latch and a first oscillator coupled to the data input of the latch to output a first oscillating signal. Further, the programmable random bit source includes a second oscillator coupled to the clock input of the latch circuit to output a second oscillating signal having a frequency slower than a frequency of the first oscillating signal.

Abstract: A method for detecting a random missing code by applying a delta-sigma (&Dgr;&Sgr;) analog digital converter having a digital filter is provided. The method includes steps of floating an input end of the delta-sigma (&Dgr;&Sgr;) analog digital converter, and detecting an output code outputted from the digital filter of the delta-sigma (&Dgr;&Sgr;) analog digital converter for determining whether the random missing code exists. A detecting device for detecting the random missing code is also provided.

Abstract: Arithmetic unit having a set of multipliers and adders receives initial data in the form of both digital operands and analog signals. Stochastic multipliers and adders carry out multiplication and addition. The initial data are converted to pseudorandom sequences to perform arithmetical operations of multiplication and addition. The arithmetic unit includes an n-bit pseudorandom numbers generator (12) that generates M-sequences with the period of N=2n−1 time slots. The M-sequences are used in two logic units (14, 16) that generate pseudorandom sequences with a given probability of occurrence of 1's. The digital operands are converted to pseudorandom sequences by data-to-sequence converters (54) that receive n-bit operand and pseudorandom sequences with a given probability of occurrence of 1's from one of the logic units.

Abstract: A semiconductor arithmetic unit which realizes a maximum or minimum value retrieval operation at high speed and with a high degree of accuracy used in a vector quantization processor is composed of a binary-multivalue-analog merged operation processing circuit. A multi-loop circuit includes an amplifying circuit group composed of a plurality of sets of first amplifiers with a floating gate to which first electrodes and a single second electrode are capacitively coupled with a predetermined ratio, a logical operation circuit to which output signals of the amplifying circuit group are inputted and which outputs a logical 0 or 1, and a second amplifying circuit to which an output signal of the logical operation circuit is inputted and whose output is distributed to all of the second electrodes of the amplifying circuit group.

Abstract: The present invention relates to a method of modelling a circuit travelled by a drilling mud during drilling, the circuit including both the well and the surface equipment, in particular solid separation devices, in which method, for each time sequence, there are calculated the mass concentration of each liquid and solid species present in the mud, the total flow rate, and the grain size distribution of each solid species downstream from each item of equipment. The invention also provides inversion of the above method to estimate the size of the cuttings on the basis of the measured efficiency of solid separation devices.

Abstract: One embodiment of the present invention provides a system that solves a problem involving an interval parameter p through an interval solution process. During operation, the system receives a representation of the problem, wherein the problem includes a number of variables x1, x2, x3, . . . xn and at least one interval parameter p. The system stores the representation in a computer memory, and then performs the interval solution process on the problem. During this interval solution process, the system splits the problem into sub-problems by splitting the interval parameter p into subintervals, and creating separate sub-problems for each subinterval. The system then performs the interval solution process on the sub-problems. By splitting the interval parameter p, the system can achieve a tighter bound on the solution set of the problem. The decision to split on any parameter p is made in exactly the same way it would be made if p were a variable of the problem.

Abstract: One embodiment of the present invention provides a system that solves a global optimization problem specified by a function ƒ and a set of inequality constraints pi(x)≦0 (i=1, . . . , m), wherein ƒ and pi are scalar functions of a vector x=(x1, x2, x3, . . . xn). The system operates by receiving a representation of the function ƒ and the set of inequality constraints, and then storing the representation in a memory within the computer system. Next, the system performs an interval inequality constrained global optimization process to compute guaranteed bounds on the minimum value of the function ƒ(x) subject to the set of inequality constraints. While performing the interval global optimization process, the system applies term consistency at various places in the process over a subbox X, and excludes any portion of the subbox X that violates term consistency.

Abstract: One embodiment of the present invention provides a system that solves a global optimization problem specified by a function | and a set of equality constraints q1(x)=0 (i=1, . . . , r), wherein | is a scalar function of a vector x=(x1, x2, x3, . . . xn). During operation, the system receives a representation of the function ƒ and the set of equality constraints and stores the representation in a memory within a computer system. Next, the system and performs an interval global optimization process to compute guaranteed bounds on a globally minimum value of the function ƒ (x) subject to the set of equality constraints. Performing this interval global optimization process involves, applying term consistency to the set of equality constraints over a subbox X, and excluding portions of the subbox X that violate the set of equality constraints.

Abstract: A random number generating apparatus which is suitable for miniaturization and which can easily generate binary random numbers that are cryptographically secure is provided. The apparatus comprises: a semiconductor device having a junction; reverse bias applying circuit for applying a reverse bias voltage of a degree so as to cause a breakdown current in the junction; and a binarizing circuit for binarizing a noise signal created in a current path including said junction for generating random numbers from the binarized signal.

Abstract: In a method for determining a minimum value of an optimization function under constraints given by equations, a set of points which satisfy the constraints is regarded as a Riemannian manifold within a finite-dimensional real-vector space, the Riemannian manifold is approached from an initial position within the real-vector space. An exponential map regarding a geodesic line equation with respect to a tangent vector on the Riemannian manifold ends at a finite order, an approximate geodesic line is generated as a one-dimensional orbit. An approximate parallel-translation is performed on the tangent vector on the Riemannian manifold and on the orbit generated in the orbit generating step by finite-order approximation of the exponential map regarding the parallel translation of the tangent vector.

Abstract: A random number generator comprises a laser for generating photons, an assembly of neutral density filters to attenuate the photons, a photomultiplier tube to detect the occurrence of a fraction of the attenuated photons at a rate of a single photon detected during a set length of time and to detect the occurrence of a single photon during each interval in a series of like time intervals, and a clock and shift register to record a first value for detection of any photons during a selected single time interval in the series of time intervals and to record a second value for detection of no photons during the selected single time interval. The values recorded in the shift register for the series of time intervals are a string of random numbers.

Abstract: A random number generating method and a random number generating device are provided which are capable of generating uniform random numbers. Random pulses are generated by comparing a voltage level obtained by amplifying a voltage level of a thermal noise produced by a thermal noise generating device with a reference voltage level. A pulse controller, if time intervals among random pulses are within a predetermined time, excludes random pulses occurred within the predetermined time and if time intervals among random pulses exceed the predetermined time, random numbers are generated based on time intervals among pulses measured by a counter.

Abstract: An arithmetic unit for correcting a detection output of a detector for a mechanical error of the detector in accordance with a predetermined input/output characteristic (straight line) is provided. When a digital output of the detector exceeds an upper limit value stored in a main memory, the digital output becomes a new upper limit value. From a virtual line which passes through the new upper limit value and which is parallel to the straight line, a new lower limit value is obtained. A corrected operation output is obtained in accordance with a new input/output characteristic of the detector based on the new upper limit value and the new lower limit value. Thus, the correction accuracy is improved.

Abstract: The present invention provides an event-correlation technique that can infer from patterns of events to achieve improved problem analysis in communication networks. Further, the technique adapts itself to uncertainties and changes in communication networks to better serve the needs of communication networks. This is accomplished by forming fuzzy cognitive maps including causally equivalent fragments using the network element interdependencies derived from a database defining the network managed objects and event notifications that can convey the state of one or more managed objects. The technique further samples generated incoming real-time events from the communication network. The sampled events are then mapped to the fragments to diagnose problems.

Abstract: A system for creating non-algorithmic, digital random numbers (20) and publishing the numbers (20) at both a high and low rate of speed on a secured Internet site (34). The numbers (20) which are used for encryption and are stored as a sequence of numbers that can incorporate a predetermined time delay, and are subsequently published on the Internet site.

Abstract: A method for generating data characterizing an item described by an ordered string of characters, comprises the steps of: (i) for a set of separation metrics each representing a unique number of positions of separation between arbitrary characters in a character group in the ordered string of characters, associating first with each separation metric; generating a set of character groups, wherein each character group comprises at least two characters contained within the ordered string of characters; and (ii) for at least one given character group in the set of character groups, for each given separation metric in the set of separation metrics, generating second data representing number of occurrences that the given character group satisfies the given separation metric; generating third data associated with the given character group, wherein the third data is based upon the second data and the first data; and storing the third data in memory for subsequent use.

Abstract: A DDS (Direct Digital Synthesis) frequency synthesizer can be adapted to operate as a pseudo random noise generator by including a swept address ingredient that distributes (but does not eliminate) repetitive frequency components that would otherwise appear in the output of the basic DDS technique, (which fetches fixed but randomized values from a waveform memory). These residual distributed long period frequency components in the output of a swept DDS pseudo random noise generator are suppressed by making the sweep itself irregular. The noise generator includes an Address Increment Register (AIR) whose content: (1) alters the address used to fetch fixed randomized values from the waveform memory; and (2) is incremented to produce the swept address (different sequences of addresses). At some point the AIR value has been incremented as high as it will go (i.e., the end of the sweep has been reached), and the process must start over.

Abstract: A method and device for the generation of a random signal, comprising:

Abstract: A method for detecting a random missing code by applying a delta-sigma (&Dgr;&Sgr;) analog digital converter having a digital filter is provided. The method includes steps of floating an input end of the delta-sigma (&Dgr;&Sgr;) analog digital converter, and detecting an output code outputted from the digital filter of the delta-sigma (&Dgr;&Sgr;) analog digital converter for determining whether the random missing code exists. A detecting device for detecting the random missing code is also provided.

Abstract: The device of the invention comprises an oscillator circuit (11) fitted with semiconducting logic elements and further means (112) such as switches controlling startup or shutdown of said circuit and, in that process, causing it to heat or cool in order to generate a random signal at the output of said logic elements. In order to attain random signals continuously, several such devices, and furthermore sub-assemblies (21, 22) to control in alternating manner their heating and cooling are used.

Abstract: A matched filter and signal reception apparatus having a low power consumption and small circuitry size. In the matched filter, an analog input signal is converted to digital data by an analog to digital (A/D) converter, digital multiplication, as a correlation calculation, is executed by a plurality of exclusive-OR circuits, and an addition of outputs of the exclusive-OR circuits is performed. In the digital multiplication, the digital data is multiplied by a spreading code of one bit. The outputs from the exclusive-OR circuits are added for each weight of bits, and the addition output results are weighted and summed together.

Abstract: A process and device for generation of a random signal, and a digital-analog conversion system using such a random signal.

Abstract: A system for producing a white-light interference hologram includes a camera adapted for recording a first and a second bitmap image of a scene from separate vantage points, and the separation distance of the vantage points, a computing engine adapted to compute three-dimensional x, y, and z characteristics of an interference hologram topology for the scene from the bitmap image and separation data, wherein x and y are two dimensional locations of bits in a bitmap of the topology and z is a depth dimension for each x,y bit, and a printer adapted to print in color the x,y bitmap, and to create the depth dimension z at each x,y bit location, providing thereby a three-dimensional interference hologram topology for the scene. In a preferred embodiment the depth dimension is created by electrophoresis, using a medium having an electrophoretic gel layer, with the ink applied to the gel in a bit-mapped pattern being ionic in nature, and capable of being migrated in the gel layer by electrophoresis.

Abstract: Methods and an apparatus for generating random numbers are disclosed. In a first embodiment, a method for generating random numbers involves producing a second random number. A pseudorandom number is produced from a digital random number generator and a first random number is produced from an analog random number generator.

Abstract: A single analog filter structure within a partial response channel combines an antialias low pass filter and a time domain waveform shaping equalizer upstream of a digital sampler. The filter also improves latencies associated with timing acquisition of a sampler clock generator loop by removing the latency of a separate equalization filter. The filter also provides a method for adapting a combination of internal filter state voltages and currents in real time for optimizing pole locations of the analog filter structure, during both data and timing recovery operations of the channel.

Abstract: A physical random number generator including a noise source configured to generate a noise signal, an alternating current AC coupling amplifying device which amplifies the noise signal while removing a direct current DC component therefrom by AC coupling to generate an amplified noise signal, an analog/digital A/D conversion device having an accuracy of not less than two bits which A/D converts the amplified noise signal to digital values composed of bit data of not less than two bits, and a processing device which processes the amplified noise signal and which processes digital values converted from a processed amplified noise signal to generate random number data of not less than two bits with an increased differential nonlinearity as compared to digital values unprocessed by the processing device.

Abstract: A processor particularly useful in multimedia applications such as image processing is based on a stream programming model and has a tiered storage architecture to minimize global bandwidth requirements. The processor has a stream register file through which the processor's functional units transfer streams to execute processor operations. Load and store instructions transfer streams between the stream register file and a stream memory; send and receive instructions transfer streams between stream register files of different processors; and operate instructions pass streams between the stream register file and computational kernels. Each of the computational kernels is capable of performing compound vector operations. A compound vector operation performs a sequence of arithmetic operations on data read from the stream register file, i.e., a global storage resource, and generates a result that is written back to the stream register file.

Abstract: A signal processor which can be configured to perform interpolation or decimation of an analog input signal, using a combination of continuous-valued discrete-time sampling together with digital filter coefficients. In its preferred embodiment, the signal processor includes a signal sampling circuit configured to produce a continuous-valued discrete-time sequence of the most recent N input samples, with the sequence being stored in a circular buffer arrangement of sample-and-hold circuits. Further, in its preferred embodiment, the signal processor includes a filter coefficient shift-register that stores digital filter coefficients, with the shift register contents being cyclically shifted to maintain the correct time correspondence with the input samples held in the circular buffer of input samples.