Abstract: This invention provides a logic block comprising an mxn array of partial calculating circuits (where m≧2 and n≧2) operable to generate partial product components of an m-bit multiplicand x n-bit multiplicand binary multiplication and to generate a cumulative sum of the partial products for each bit of one of the multiplicands. A configurable output circuit which is operable under the control of a configuration signal either (a) to sum the cumulative sums of partial products generated by the partial calculating circuits so as to generate a product value, or (b) to pass data representing the cumulative sums of the partial product components to partial calculating circuits within one or more further logic blocks. Also provided is a logic circuit including two or more such logic blocks, data interconnections for data transfer between the logic blocks and control interconnections for control signal transfer to the logic blocks.

Abstract: An apparatus is provided for adding selected bits. The apparatus includes a hardware device having a plurality of ordered input terminals to receive binary signals for a portion of an ordered set of the selected bits. The hardware device also has a plurality of output terminals to transmit digital signals for a plurality of sums. Each sum adds a set of speculative values of a portion of the selected bits. A method is provided for adding a set of ordered selected logic signals. The method includes producing a set of digital signals for a plurality of sums and selecting one of the digital signals for a sum in response to receiving a signal for a correction vector. Each sum adds a set of speculative values for an ordered set of selected logic signals. The selected sum is equal to a sum of speculative values of the selected logic signals as identified by the correction vector. The method also includes transmitting the selected one of the digital signals to an output terminal.

Abstract: A method and apparatus is disclosed that uses an arithmetic circuit for adding numbers represented in a redundant form to also subtract numbers received in redundant form, including numbers received from a bypass circuit. A non-propagative comparator circuit is then used to compare a given value with a result from the arithmetic circuit to determine if the result is equal to the given value. All of the operations described above can be accomplished without propagating carry signals throughout the circuitry.

Abstract: A method and apparatus is disclosed that uses an arithmetic circuit for adding numbers represented in redundant form to subtract numbers received in redundant form, including numbers received from a bypass circuit. The method includes generating a complemented redundant form of at least one number supplied to the arithmetic circuit in redundant form. It also includes providing an adjustment input to the arithmetic circuit to augment a result produced through the arithmetic circuit to generate a valid outcome in redundant form of a subtraction operation.

Abstract: The present invention comprises a method and apparatus that selectably performs either addition or subtraction on two N-nary operands to generate an intermediate, then final, N-nary final result. If the intermediate result of the operation contains less bits than a full register, the intermediate result is “merged” with the second operand in that unaltered bits from the second operand are bypassed to the final result. Accordingly, the final result and the second operand have an equal number of bits.

Abstract: The present invention provides an apparatus and a method for address generation. In one embodiment, an apparatus for an address generation unit of an ALU (Arithmetic Logic Unit) of a microprocessor includes a first carry-propagate adder that adds a lower 16 bits of a constant or displacement and a lower 16 bits of a segment base, and a second carry-propagate adder connected to the first carry-propagate adder, wherein the second carry-propagate adder adds a lower 16 bits of a base and an output of the first 16-bit carry-propagate adder to generate a lower 16 bits of an address. In one embodiment, the first carry-propagate adder and the second carry-propagate adder are each 16-bit carry-propagate adders.

Abstract: An apparatus that performs arithmetic logic and carry-lookahead logic in parallel on two N-nary operands, including saturating or unsaturating, signed or unsigned, addition or subtraction. The operands may be selectably partitioned into 8-bit, 16-bit, 32-bit, or 64-bit operands. For multiple partitions, carry propagation is interrupted on partition boundaries. Each selectable feature may be implemented singly, or in combination with other selectable features.

Abstract: An apparatus and method for performing saturating addition or subtraction on two signed or unsigned operands using N-NARY logic. The two operands may be selectably partitioned into 8-bit, 16-bit, 32-bit, or 64-bit operands. For multiple partitions, carry propagation is interrupted on partition boundaries so that partitions may be saturated independently.

Abstract: The present invention discloses an apparatus and method for performing carry propagate logic on two 1-of-4 two-bit addends to produce a 1-of-3 carry propagate indicator. The preferred embodiment of the present invention will set an H indicator for a given dit n if the sum of An and Bn is less than or equal to two, will set a P indicator if the sum is three, and will set a G indicator if the sum is greater than three.

Abstract: A method for forming a sum of the absolute value of the difference between each pair of numbers of respective first and second sets of numbers. The method includes forming the difference between a first number of the first set and a second number of the second set. Next this difference is either added to or subtracted from a running sum based upon the sign of this difference. This is repeated until all number pairs are either added to or subtracted from the running sum of absolute values of the differences. The initial subtraction is used to set a status bit in a flag register (211) based upon a less than zero output or the carry-out. The status bit controls whether the difference is added to or subtracted from the running sum. The conditional addition to or subtraction from the running sum may generate a carry-out representing the most significant bit of the running sum. This carry-out is stored and later added to the running sum to recover the most significant overflow bits.

Abstract: The present invention uses N-nary logic to perform addition or subtraction, along with carry propagate logic, within one gate. The gate produces as outputs a 1-of-4 result value and a 1-of-3 HPG indicator. The preferred embodiment of the present invention implements subtraction using three's complement addition. In an alternative embodiment, four's complement addition is implemented to achieve the subtract function and the HPG indicator is a 1-of-2 signal that combines the H(alt) and P(rop) indications.

Abstract: The present invention utilizes N-nary logic to implement an add function and a carry-lookahead function within the same gate, producing an N-nary sum and an N-nary HPG indicator.

Abstract: The present invention discloses a method and apparatus for adding two 1-of-N addends to produce a 1-of-N sum. In the preferred embodiment, the addends and sum comprise 1-of-4 logic signals.

Abstract: Circuits containing resonant tunneling devices are disclosed which offer significant advantages for realizing ultra-dense, ultra-high performance multivalued logic arithmetic integrated circuits. Multivalued logic circuits implemented with resonant tunneling devices can achieve increased speed and density over binary circuits and multiple-valued circuits implemented in conventional IC technologies since multiple binary bits are very efficiently processed by architectures which make use of devices with multiple negative transconductance regions.

Abstract: Apparatus, and an associated method, for generating multi-bit sequences used, for instance, to form an address pointer or a data pointer of a computer system. The circuitry is embodied in a single-cycle path and is operable to generate an output sequence which is of a bit length which is a multiple of an input sequence. In one implementation, the circuitry is used to generate 48-bit address pointers and 16-bit data pointers.

Abstract: Circuit designs of basic digital logic gates are disclosed using Resonant Tunneling Diodes (RTDs) and MOSFETs, which reduces the number of devices used for logic design, while exploiting the high speed negative differential resistance (NDR) characteristics of RTDs. Such logic circuits include NAND, NOR, AND, and OR gates and Minority/Majority circuits, which are used in full adder circuits. By implementing RTDs along with conventional MOSFETs, the use of series connected MOSFETs, which results in low output rise and fall times, especially for a large number of inputs, can be avoided. Furthermore, the RTD logic design styles do not require the use of resistors or any elaborate clocking or resetting scheme.

Abstract: A method for controlling a microprocessor to transform data from a signed format to an unsigned format so that the data can be processed by unsigned instructions. In particular, a subtraction between two signed numbers can be transformed into a subtraction between two unsigned numbers.

Abstract: In the present invention, a method for directing parallel processing computing device to perform the operation of setting a signed value of N bits to an absolute value comprises the steps of: performing an arithmetic shift right of N-1 bit to form a bit mask; performing an exclusive-OR logical operation with the signed value of N bits and the bit mask to form a result; and subtracting the bit mask from the result of the exclusive-OR logical operation to form the absolute value of the signed value of N bits. Further, an apparatus for parallel processing a signed value to form an absolute value comprises: means for performing an arithmetic shift right of N-1 bit to form a bit mask; means for performing an exclusive-OR logical operation with the signed value of N bits and the bit mask to form a result; and means for subtracting the bit mask from the result of the exclusive-OR logical operation to form the absolute value of the signed value of N bits.

Abstract: An apparatus sums a plurality of columns of binary bits to produce a plurality of partial sum and carry bits. The bits of a particular column being of the same order of magnitude, and the bits of different columns differing in orders of magnitude. The apparatus includes one or more full adder. Each full adder receives three bits as an input to produce a first sum bit and a first carry bit as output. The apparatus also includes one or more half adders. Each half adder receives two bits as input to produce a second sum bit and a second carry bit as output. The full adders and half adder are interconnected as a plurality of interconnecting column adders. Each column adder sums bits of the input of at least one column and generates a partial sum and carry bit. Each column adder has a plurality of stages. A plurality of conductors interconnect the stages of each column adder with other stages in the same column adder and with stages in other adjacent column adders.

Abstract: A method of controlling a microprocessor to transform unsigned data to a signed format so that the unsigned data can be processed by signed instructions. In particular, a subtraction between two unsigned numbers can be transformed into a subtraction between two signed numbers.

Abstract: A mechanism in a microprocessor to transform signed data to an unsigned format so that the signed data can be processed by unsigned instructions. In particular, a subtraction of two signed numbers can be transformed into a subtraction of two unsigned numbers.

Abstract: A microprocessor operable to transform unsigned data to a signed format so that the unsigned data can be processed by signed instructions. In particular, a subtraction between two unsigned numbers can be transformed into a subtraction between two signed numbers.

Abstract: The expression A-sign(A), where A is a signed binary integer represented in 2's complement form, sign(A) is equal to one when A is greater than zero, sign(A) is equal to zero when A is zero, and sign(A) is equal to negative one when A is less than zero, is calculated by bit-complementing A, bit-complementing (A-1) when A is less than zero, bit-complementing A when A is equal to zero, and bit-complementing (A+1) when A is greater than zero. Zero detect for A is provided by determining whether a first carry-out bit from (A+0) and a second carry-out bit from (A+1) have different logical values. In this manner, A-sign(A) can be calculated by a general purpose computer in a single instruction cycle.

Abstract: A linear address generation apparatus is provided which adds the segment base address to the displacement provided in the instruction while the instruction is being decoded. The linear and logical address generation are combined. Whereas linear address generation may have formerly required 2-3 clock cycles, 1-2 clock cycles may be achieved using the apparatus disclosed herein. The reduced latency in generating linear addresses may lead to reduced data access latency, and further may lead to increased performance in a microprocessor employing the apparatus. Performance increases are derived from the reduced number of clock cycles required for execution of memory accesses, and due to instructions dependent upon the memory accesses receiving data more quickly. For embodiments of the microprocessor employing the x86 microprocessor architecture, the apparatus additionally detects an arithmetic carry from low order bits of the addition to higher order bits of the addition.

Abstract: An address limit violation detection circuit in a microprocessor-based computer system for eliminating delay between the generation of a definite limit violation (DLV) signal and the generation of a potential limit violation signal. The detection circuit includes a full adder circuit which is adapted to receive a linear address, a base address, and a limit value and further adapted to produce a plurality of sum bits and a plurality of carry bits in response thereto. The circuit further includes a DLV detection circuit adapted to receive the plurality of sum bits and carry bits from the full adder circuit and further adapted to produce a DLV signal in response thereto. The DLV signal is indicative of whether the linear address is greater than the sum of the base address and the limit value.

Abstract: An output-processing circuit for a neural network, which may be implemented on an integrated circuit, comprises at least one latch and at least one adder. Outputs from a plurality of neurons are sequentially received by the output-processing circuit. The output-processing circuit uses gating functions to determine which neuron outputs are summed together to produce neural network outputs.

Abstract: A rectifying transfer gate circuit includes first and second field effect transistors and one diode. The source of the first field effect transistor is coupled to a first input node and the gate thereof is coupled to a second input node. Meanwhile, the source of the second field effect transistor is coupled to the second input node and the gate thereof is coupled to the first input node. The diode is coupled between the common drain of the first and second field effect transistors and an output node, so as to increase the speed of the operation in the application circuit utilizing the above rectifying transfer gate circuit.

Abstract: A floating point addition and subtraction circuit includes a comparison subtraction circuit receiving two operands to be processed for making a comparison in the size between their exponent parts so as to subtract the smaller exponent part from the larger one, the comparison subtraction circuit providing the comparison result and the subtraction result. A mantissa selecting circuit and a shift circuit align the mantissa of the operand. Leading zero counting circuit counts the number of zeros successively positioned in the high order direction from the least significant bit of the mantissa of the operand having the smaller operand. Comparator circuit compares the counting result and the subtraction result by the comparison subtraction circuit, to thereby detect a sticky bit according to the comparison result.