Abstract: A receive module. The receive module has a first voltage divider for adjusting a first receive threshold; a first comparator, connected to the first voltage divider, for evaluating differential signals received from a bus of the bus system using the first receive threshold; a second voltage divider for adjusting a second receive threshold or a third receive threshold; a second comparator, connected to the second voltage divider, for evaluating the differential signals using the second or third receive threshold adjusted by the second voltage divider; and a switching unit for the switchover between the second and third receive threshold as a function of an operating mode of the receive module, to which the receive module is to be switched for a first or second communications phase of a communication on the bus, the first and second voltage dividers being connected to the bus in each case.

Abstract: Systems and methods are provided for managing data transmissions in integrated circuits using a handshake, credit path, and data path. For example, the handshake between transmission and receiving sides can enable information to be passed over a separate path from the data path. Based on a calculated round trip delay, the system can identify the number of top level flops or registers needed in the credit path, which can be the same as the number of top level flops or registers in the data path. The receiving side can calculate the required number of credits per requested virtual channel based on the available queuing resources of the receiving side and the round trip delay of the data path, in order to ensure full bandwidth data streaming on the channel.

Abstract: An information handling system bus port above a subject information handling system bus device may host an information handling system bus out of band message access control list of information handling system bus target device identifiers of other information handling system bus connected devices that the subject device is permitted to communicate with. The port may compare an information handling system bus target device identification field in out of band messages from the subject device to the list and route only out of band messages from the subject device in which the target device identification in the target device identification field is on the access control list through the information handling system bus. The port may discard (and generate error notifications, statuses, etc.) for out of band messages in which the target device identification in the target device identification field is not on the access control list.

Abstract: In aspects, a Local Interconnect Network (LIN) communication circuit including a first LIN master associated with a first LIN bus and a second LIN master associated with a second LIN bus is disclosed. A data link is connected between the first and second LIN masters. A first mirroring client is established at the first LIN master for receiving message bits corresponding to a LIN message in a first slot on the first LIN bus and for transmitting the message bits bitwise over the data link. A second mirroring client is established at the second LIN master for receiving the message bits and transmitting them over the second LIN bus. The first and second LIN masters include synchronised schedule tables such that the message bits on the second LIN bus are transmitted in a corresponding slot to the first.

Abstract: Peer-to-peer arrangements between graphics processing units (GPUs) are provided herein. A method includes establishing synthetic devices representing GPUs in an address domain associated with a host processor, where the GPUs have a different address domain than the host processor. The method also includes forming a peer arrangement between the GPUs such that data transfers between the GPUs in the different address domain can be initiated by the host processor interfacing with the synthetic devices.

Abstract: Devices for performing communications are disclosed. In some implementations, a device includes: an upstream port for receiving data from or transmitting data to one or more external devices located on an upstream path through a link including a plurality of lanes; a lane margining controller coupled to the upstream port and for transmitting, via the upstream port, to the one or more external devices, a margin command for requesting a lane margining operation to acquire margin status information to indicate a margin of each of the plurality of lanes, and controlling the upstream port to receive the margin status information from the external devices; and a port setting controller coupled to be in communication with the upstream port to receive the margin status information and for determining a setting of the upstream port based on the margin status information.

Abstract: A method is provided to generate a configuration descriptor for a chipset in a computing unit. The method includes determining, by one or more processors, a plurality of desired interface configurations for the chipset and for each of the one or more desired interface configurations, determining one or more ports of the chipset and corresponding platform connectors that satisfy features of the each of the one or more of the desired interface configurations based on a chipset description and a platform description. The method further includes assigning a port from among the determined one or more ports to the each of the one or more of the desired interface configurations and generating a chipset configuration descriptor based on the assigning of ports to each of the one or more desired interface configurations. In some embodiments, the chipset is initialized based on the configuration descriptor.

Abstract: Systems and devices can include an upstream port, a downstream port, and a multilane link connecting the upstream port to the downstream port, the multilane link comprising a first link width. The upstream port or the downstream port can be configured to determine that the downstream port is to operate using a second link width, the second link width less than the first link width; transmit to the upstream port an indication of a last data block for the first link width across one or more lanes of the multilane link; cause a first set lanes to enter an idle state; and transmit data on a second set of lanes, the second set of lanes defining the second link width.

Abstract: Disaggregated computing architectures, platforms, and systems are provided herein. In one example, a method includes receiving user input to establish a compute unit comprising a host processor and at least two graphics processing units (GPUs) having a peer-to-peer capability. The method also includes instructing a management element for a communication fabric to form the compute unit and communicatively couple the host processor and the at least two GPUs over the communication fabric. The method also includes instructing the management element to establish an isolation function to form the peer arrangement between the at least two GPUs in the communication fabric, where the isolation function isolates a first address domain associated with the at least two GPUs from at least a second address domain associated with the host processor by at least establishing synthetic devices representing the at least two GPUs in the second address domain.

Abstract: Disclosed are ticketed flow control mechanisms in a processing system with one or more masters and one or more slaves. In an aspect, a targeted slave receives a request from a requesting master. If the targeted slave is unavailable to service the request, a ticket for the request is provided to the requesting master. As resources in the targeted slave become available, messages are broadcasted for the requesting master to update the ticket value. When the ticket value has been updated to a final value, the requesting master may re-transmit the request.

Abstract: Aspects of the present disclosure relate to power bridge circuitry comprising a first interface configured to interface with a source power domain; a second interface configured to interface with a target power domain; transition circuitry to receive a transition indication that the power bridge circuitry is to transition to an idle state; communication circuitry to communicate messages between the interfaces; and message identification circuitry to identify messages communicated by the communication circuitry, the identification circuitry being configured to detect the communication of a given message directed to a target component connected to the second interface and indicating cessation of communication between the target component and a source component connected to the first interface.

Abstract: Disaggregated computing architectures, platforms, and systems are provided herein. In one example, a method includes receiving user input to establish a compute unit comprising a host processor and at least two graphics processing units (GPUs) having a peer-to-peer capability. The method also includes instructing a management element for a communication fabric to form the compute unit and communicatively couple the host processor and the at least two GPUs over the communication fabric. The method also includes instructing the management element to establish an isolation function to form the peer arrangement between the at least two GPUs in the communication fabric, where the isolation function isolates a first address domain associated with the at least two GPUs from at least a second address domain associated with the host processor by at least establishing synthetic devices representing the at least two GPUs in the second address domain.

Abstract: Disaggregated computing architectures, platforms, and systems are provided herein. In one example, a method of operating a data system is provided. The method includes initiating an isolation function in a communication fabric to form a peer arrangement between graphics processing units (GPUs) coupled to the communication fabric. The isolation function isolates a first address domain associated with the GPUs from at least a second address domain associated with the host by at least establishing synthetic devices representing the GPUs in the second address domain.

Abstract: Verifying a device under test (DUT) in which the DUT includes a bridge with a late write buffer includes storing write requests provided to the bridge in an initiator queue, and storing write requests provided to the target memory in a target queue. Upon both the initiator and target queues being non-empty, when entry addresses of top entries of the initiator and target queue match, data entries of the top entries of the initiator and target queue do not match, and the initiator queue has more than one entry, determining whether an entry address of a next entry in the initiator queue matches the entry address of the top entry in the initiator queue, and when the entry addresses of the next entry and the top entry in the initiator queue match, merging the top and next entry of the initiator queue and deleting the top entry of initiator queue.

Abstract: Computing architectures, platforms, and systems are provided herein. In one example, a computing system is provided. The computing system includes a management processor configured to initiate a peer-to-peer arrangement between a first peripheral component interconnect express (PCIe) device and a second PCIe device over a PCIe fabric comprising one or more PCIe switches. The peer-to-peer arrangement is established to detect data transfers from the first PCIe device directed to addresses corresponding to an address range established for the second PCIe device by a peer-to-peer management entity executed on a host processor, and redirect the data transfers over the PCIe fabric to the second PCIe device such that the data transfers are received by the second PCIe device without passing through the host processor.

Abstract: Disaggregated computing architectures, platforms, and systems are provided herein. In one example, a method of operating a data processing system is provided. The method includes instructing a PCIe fabric communicatively coupling a plurality of physical computing components including one or more central processing units (CPUs), one or more storage modules and one or more PCIe switches to establish a first PCIe communication path between the management processor and a storage module of the one or more storage modules. The method also includes storing at least an operating system to the storage module using the first PCIe communication path and instructing the PCIe fabric to remove the first PCIe communication path between the management processor and the storage module. Moreover, the method includes instructing the PCIe fabric to establish a second PCIe communication path between a CPU of the one or more CPUs and the storage module comprising the operating system.

Abstract: A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units. The agents send requests in the form of read and write transactions. The system also includes a memory that includes coherent memory regions. The memory is in communication with the agents. The system includes a coherent interconnect in communication with the memory and the agents. The system includes a second identical coherent interconnect in communication with the memory and the agents. The system also includes a comparator for comparing at least two inputs, the comparator is in communication with the two coherent interconnects.

Abstract: Embodiments of the apparatus of identifying internal destinations of network packets relate to a network chip that allows flexibility in handling packets. The handling of packets can be a function of what the packet contents are or where the packets are from. The handling of packets can also be a function of both what the packet contents are and where the packets are from. In some embodiments, where the packets are from refers to unique port numbers of chip ports that the packets arrived at. The packets can be distributed for processing within the network chip.

Abstract: A device management method and an apparatus. The device management method of the present disclosure includes receiving, by a switching device, diagnostic information sent by a managed device, where the diagnostic information is used to indicate at least one of a software version, a hardware version, or a running status of the managed device; and sending, by the switching device, the diagnostic information to a device management controller. The embodiments of the present disclosure resolve a problem of processing performance deterioration caused by device management performed by a central processing unit (CPU) of a server.

Abstract: A modular interconnectivity assembly for interconnecting elements of a point of sale system, the modular interconnectivity assembly including at least one interconnectivity module including an Input/Output (I/O) hub having at least one upstream facing port and at least two downstream facing ports, at least one upstream connector connected to the at least one upstream facing port of the (I/O) hub and adapted for communication in accordance with a first communication protocol, at least one downstream connector connected to at least one of the at least two downstream facing ports and adapted for communication in accordance with the first communication protocol and at least one interface connected to another of the at least two downstream facing ports and adapted for communication in accordance with a second communication protocol, different from the first communication protocol.

Abstract: Disaggregated computing architectures, platforms, and systems are provided herein. In one example, a method of operating a data processing system is provided. The method includes communicatively coupling graphics processing units (GPUs) over a Peripheral Component Interconnect Express (PCIe) fabric. The method also includes establishing a peer-to-peer arrangement between the GPUs over the PCIe fabric by at least providing an isolation function in the PCIe fabric configured to isolate a device PCIe address domain associated with the GPUs from at least a local PCIe address domain associated with a host processor that initiates the peer-to-peer arrangement between the GPUs.

Abstract: The automated recovery of the warmth of cache of an application that has been subject to a running state change that degraded the warmth of the cache. To prepare for a loss in warmth, the state of a cache portion identifiers are captured. Such identifies the cache portions that are within the application cache at an instant in time. Thereafter, the application experiences a change in running state that diminishes the warmth of the application cache. For instance, the application might be stopped and restarted. After and despite this cache degradation, the application may continue to operate. However, in order to warm the application cache more quickly, while the application is operating, the application cache is automatically warmed. For instance, while the application is operating, cache portions identified by the captured cache portion identifiers are automatically accessed from a source that is external to the application cache.

Abstract: A device for processing graphics data includes a plurality of graphics processing units. Each graphics processing unit may correspond to a virtualized operating system. Each graphics processing unit may include a configuration register indicating a 3D class code and a command register indicating that I/O cycle decoding is disabled. The device may be configured to transmit a configuration register value to a virtualized operating system indicating a VGA-compatible class code. The device may be configured to transmit a command register value to the virtualized operating system that indicates that I/O cycle decoding is enabled. In this manner, legacy bus architecture of the device may not limit the number of graphics processing units deployed in the device.

Abstract: A system includes a PCIe controller coupled to a device through a nontransparent PCIe bridge. The controller is operable to direct I/O operations to the device on behalf of a host system. The system also includes a PCIe driver operable within the host system to generate I/O request descriptors that specify movement of data from the PCIe controller to the host system as well as from the host system to the PCIe controller. The PCIe controller processes the I/O request descriptors and determines which device is involved in the specified movement of data. The PCIe controller generates I/O commands that contain routing information for the device (e.g., memory addresses and steering information) to route the data between the memory address of the host system and the memory address of the device, bypassing a memory of the PCIe controller.

Abstract: Systems and methods for configuration snooping are provided. A bridge identifies an initialization message of a central processing unit (CPU) for a device that is downstream of a primary interface of the bridge. The bridge identifies a response to the initialization message. The bridge determines the address range for the device. The bridge stores the address range for the device in a list in the bridge.

Abstract: A tunnel for a communication system includes first and second bridges. The first bridge has a first port adapted to couple to a first link and a second port, and has a first programmable bus number and a first programmable function number. The second bridge has a first port coupled to the second port of the first bridge, and a second port, and has a second programmable bus number and a second programmable function number. In a hoist enabled mode, the first bridge forwards a packet on the first link to the second bridge if the second programmable bus number is equal to the first programmable bus number, a bus number of the packet is equal to the first programmable bus number, and a function number of the packet is equal to the second programmable function number.

Abstract: An embodiment may include circuitry to facilitate, at least in part, a first network interface controller (NIC) in a client to be capable of accessing, via a second NIC in a server that is remote from the client and in a manner that is independent of an operating system environment in the server, at least one command interface of another controller of the server. The command interface may include at least one controller command queue. Such accessing may include writing at least one queue element to the at least one command queue to command the another controller to perform at least one operation associated with the another controller. The another controller may perform the at least one operation in response, at least in part, to the at least one queue element. Many alternatives, variations, and modifications are possible.

Abstract: There is provided a file transfer device in which a determining unit determines, when a first file requested by a user terminal is not cached in a file buffering unit, a second file transferred to the user terminal based on a file cache status of the file buffering unit, a transfer protocol unit reads the second file from the file buffering unit while the file buffering unit reads the first file, a transmitting unit transmits the second file to the user terminal, wherein the instructing unit determines to transfer the first file, based on a progress status of reading the first file, the transfer protocol unit suspends reading the second file and reads the first file from the file buffering unit, the transmitting unit transmits the first file read by the transfer protocol unit to the user terminal.

Abstract: A selective booting method and a broadcast receiving apparatus using the same are provided. The broadcast receiving apparatus including: a broadcast reception unit; a display which displays a broadcast received through the broadcast reception unit; a storage unit which stores a plurality of drivers of hardware provided on the broadcast receiving apparatus; and a controller which selectively loads a first driver, among the stored drivers, of first hardware for executing a first operation selected from among a plurality of operations, and then loads a second driver. Therefore, a user may execute foremost a desired operation.

Abstract: A bridge includes a Peripheral Component Interconnect Express interface supporting at least two lanes, an Extensible Host Controller Interface, and a Universal Serial Bus 3.0 root hub. The Peripheral Component Interconnect Express interface is used for coupling to a host. Each lane of the at least two lanes provides a highest data transmission speed. The Extensible Host Controller Interface is coupled to the Peripheral Component Interconnect Express interface for storing data transmitted by the Peripheral Component Interconnect Express interface. The Universal Serial Bus 3.0 root hub includes a first controller and a second controller. The first controller and the second controller are used for controlling data transmission of four ports, and a highest data transmission speed provided by each port of the four ports is not more than the highest data transmission speed provided by the lane.

Abstract: An apparatus and method of fast PCIe multi-function device address decode utilizing a target function data look up table. One or more decode directives (e.g., targeted functions) are provided within the PCIe request packet, thereby eliminating the need for target function search during the decode process in the endpoint device. This enables single-decoder single-step decode implementation in complex multi-function devices.

Abstract: PCI Express is a Bus or I/O interconnect standard for use inside the computer or embedded system enabling faster data transfers to and from peripheral devices. The standard is still evolving but has achieved a degree of stability such that other applications can be implemented using PCIE as basis. A PCIE based interconnect scheme to enable switching and inter-connection between multiple PCIE enabled systems each having its own PCIE root complex, such that the scalability of PCIE architecture can be applied to enable data transport between connected systems to form a cluster of systems, is proposed. These connected systems can be any computing, control, storage or embedded system. The scalability of the interconnect will allow the cluster to grow the bandwidth between the systems as they become necessary without changing to a different connection architecture.

Abstract: A system includes an interface with a plurality of sub-addresses. The interface receives critical data and non-critical data. The critical data are received only at more specific sub-addresses of the interface. The interface transfers the critical data received at the sub-addresses to a critical processor, such that the critical data avoids being received by or being processed by a non-critical processor. The interface transfers the non-critical data from the interface to the non-critical processor. The configuration of the interface is hard-coded such that the configuration of the interface is fixed at power up of the interface and is non-changeable by the non-critical processor. The interface includes an external platform interface that is external to the critical processor, the non-critical processor, and a local controller. The external platform interface includes a limited ability to store the critical and non-critical data.

Abstract: A network switch, based on the PCI Express protocol, is disclosed. The switch includes a processor, local memory and a plurality of non-transparent bridges. By configuring the non-transparent bridges appropriately, the network switch can facilitate a number of different communication mechanisms, including TCP/IP communication between servers, server clusters, and virtualized I/O device utilization. For example, the network switch may configure the non-transparent bridges so as to have access to the physical memory of every server attached to it. It can then move data from the memory of any server to the memory of any other server. In another embodiment, the network switch is connected to an I/O device, and multiple servers are given access to that I/O device via virtualized connections.

Abstract: A communication system includes an I2C bus interconnecting at least one first device and one second device. At least one direct data link, other than the I2C bus, interconnects the first and second devices. The system is configurable to operate in: a first operating mode providing for data only transmission between the first and second devices over the I2C bus; and a second operating mode providing for simultaneous data transmission between the first and second devices over both the I2C bus and said data link.

Abstract: An integrated circuit (IC) device can include a serial communication first interface (I/F) circuit electrically coupled to first physical connections of the IC device, and configured to respond to communication signals received at the first physical connections; at least one serial communication second interface (I/F) circuit electrically coupled to second physical connections of the IC device, and configured to enable data transactions over the second physical connections; and a repeater circuit configured to bypass the first I/F circuit and enable serial communication signals to be transmitted from the first physical connections to the second physical connections. Systems including such an IC device and related methods are also disclosed.

Abstract: Embodiments of the present invention provide a solution for managing inter-domain resource allocation in a Peripheral Component Interconnect-Express (PCIe) network. One processor among a plurality of link processors is elected as a management processor. The management processor obtains information about available resources of PCIe network. When a resource request from a request processor is received, the management processor allocates a resource of the available resources to the requesting processor. The management processor instructs one or more link processors to program one or more inter-domain NTBs through which the traffic between the allocated resource and the requesting processor is going to flow according to the memory address information of the allocated resource, to allow cross-domain resource access between the requesting processor and the allocated resource.

Abstract: Disclosed herein is a system having a multi-processor configuration for electronics devices and systems, such as, computing and communication devices like laptop, notebook, tablets, smartphones, etc. In accordance with one embodiment of the subject matter the system comprises a plurality of processors and a multi protocol multi-root input output virtualization (MPMRIOV) switch communicatively coupled to at least one of the plurality of processors. The system further includes a peripheral and interface virtualization unit (PIVU) coupled to the MPMRIOV switch. In said embodiment, the PIVU is configured to communicatively couple at least one of the plurality of processors with at least one of a Peripheral Component Interconnect (PCI) compliant peripheral, a Peripheral Component Interconnect express (PCIe) compliant peripheral, a non PCI compliant peripheral, and a non PCIe compliant peripheral.

Abstract: According to one embodiment, a system on a chip includes multiple agents each corresponding to an intellectual property (IP) logic and a fabric to couple the agents. The fabric can include a primary message interface and a sideband message interface. The fabric further includes one or more routers to provide out-of-band communications between the agents via this sideband message interface. To effect such communication, the router can perform a subset of ordering rules of a personal computer (PC)-based specification for sideband messages. Other embodiments are described and claimed.

Abstract: An apparatus and method for a Universal Serial Bus (USB) isolating device. An USB isolating device includes a downstream facing circuit and a upstream facing circuit. The downstream facing circuit is coupled to a peripheral device via a first pair of signals and is configured for detecting a speed at which the peripheral device is operating based on a first voltage configuration on the first pair of signals. The upstream facing circuit is coupled to the downstream facing circuit and a host/hub via a second pair of signals and is configured for communicating with the downstream facing circuit on the speed of the peripheral device and adaptively creating a second voltage configuration on the second pair of signals to facilitate the host/hub to adapt to the speed of the peripheral device.

Abstract: A method of selectively exposing expanders in a data storage fabric is disclosed. The method includes generating a phy permission table in a switch expander. The phy permission table is configured for access by an initiator and includes data as to which enclosure expanders are discoverable by the initiator. A zone group of phys from the enclosure expanders assigned to the initiator is created. The phy permission table is updated to identify each phy coupled to the enclosure expanders in the zone group.

Abstract: Methods, apparatus, and systems, for transporting data units comprising multiple pieces of transaction data over high-speed interconnects. A flow control unit, called a KTI (Keizer Technology Interface) Flit, is implemented in a coherent multi-layer protocol supporting coherent memory transactions. The KTI Flit has a basic format that supports use of configurable fields to implement KTI Flits with specific formats that may be used for corresponding transactions. In one aspect, the KTI Flit may be formatted as multiple slots used to support transfer of multiple respective pieces of transaction data in a single Flit. The KTI Flit can also be configured to support various types of transactions and multiple KTI Flits may be combined into packets to support transfer of data such as cache line transfers.

Abstract: In some embodiments a Universal Serial Bus cable includes a first differential pair to transmit bus signals, and a second differential pair to transmit bus signals in a same direction as the bus signals transmitted by the first differential pair. In this manner, a bandwidth of the Universal Serial Bus cable is doubled in that same direction. Other embodiments are described and claimed.

Abstract: A peripheral component interconnect (PCI) express switch apparatus and a method of controlling a connection thereof are provided. In this apparatus, a first virtual bridge is connected to a computer system through a first PCI express port to perform data transmission and reception according to a PCI method with an external device, and a second virtual bridge is connected to an external device through the first virtual bridge and a second PCI express port and enables the external device to perform data transmission and reception with the computer system and according to the PCI method by cooperating with the first virtual bridge. A first cable matching device is connected to the first virtual bridge. Further, a second cable matching device is connected to the second virtual bridge and is connected to the first cable matching device through a PCI cable.

Abstract: Techniques for broadcasting a command in a distributed switch, at a first switch module within the distributed switch. Embodiments receive a request to reset a PCIe link for a first host device, the first host device connected to a plurality of downstream PCIe devices through the distributed switch. A routing table specifying a plurality of downstream switch modules, connected to the first switch modules by one or more ports of the first switch module, is identified. Embodiments suspend PCIe traffic for the first host device on the one or more ports of the first switch module. Broadcast messages are transmitted to the plurality of downstream switch modules, specifying a first reset operation. Upon receiving an acknowledgement message from each of the plurality of downstream switch modules specified in the routing table, embodiments resume PCIe traffic for the first host device on the one or more ports.

Abstract: Fault tolerance is improved, a functional limitation at the time of start-up of an I/O system is avoided, and a start-up time is shortened. A downstream PCI Express bridge sets a PCI Express device connected to the downstream PCI Express bridge itself, among a plurality of single root-compatible PCI Express devices shared by a plurality of root complexes connected to a plurality of upstream PCI Express bridges that exchange data with the downstream PC Express bridge itself through a network, controls and monitors a state of a physical link with the PCI Express device connected to the downstream PCI Express bridge itself, and performs monitoring and notification of an error of the PCI Express device connected to the downstream PCI Express bridge itself.

Abstract: An apparatus for mediating communication between a universal serial bus (USB) device and a host computing device is described. In an example, the apparatus includes a USB host interface configured to be connected to a downstream USB device, and a USB device interface configured to be connected to an upstream host computing device. The apparatus also includes a mediation module positioned between the USB host interface and the USB device interface and configured to determine whether the USB device is authorized to communicate with the host computing device.

Abstract: A method is included for loading a main loadable file and at least one optional loadable file during initialization of a computer system. The method includes loading a main loadable file which includes a resident portion and an input/output network interface software component. The resident portion is a utilization software component configured to use transmission protocols. The method also includes determining which optional loadable files are required to be loaded. The optional loadable files each include an optional portion. The method also includes loading the optional loadable files which contain optional portions corresponding to required protocols.

Abstract: A method and apparatus is described herein for supporting direct memory accesses between peer I/O devices. It is determined whether a guest physical address (GPA) referenced by an access generated from an I/O device, is within a range of GPAs associated with local I/O devices based at least in part on a GPA base and a GPA window size. If the GPA is within the window, then the GPA is translated to an HPA based at least in part on a base HPA associated with a local device and then forwarded to that local device. However, if the GPA is not within the window, then the access is forwarded upstream.

Abstract: In an embodiment, an apparatus comprises a buffer, a plurality of processors, and a processor control module. The processor control module is to manage how many of the plurality of processors are used to process data from the buffer based at least in part on an amount of the data stored in the buffer.