Abstract: A system and method are disclosed for connecting PCI-ordered agents based on fully independent networks. The system and method are free of PCI topology constraints, so that the system and method can be implemented in an inexpensive and scalable way. The method disclosed is used to handle and transport PCI-ordered traffic on a fabric. Based on the actual ordering requirement of the set of PCI agents, the fabric includes two, three, or four independent networks.

Abstract: Open architecture communication systems and methods are provided that allow flexible data transmission between gaming machines and other devices and nodes within a gaming machine network. The gaming machine and other devices employ a communication interface that sends and receives data via a common communication protocol and via common communication hardware. The communication interface and common communication protocol allow data transfer between gaming machines and other network nodes such as gaming service servers, despite the presence of different proprietary gaming machine functions and proprietary communication protocols and despite the presence of various proprietary hardware and proprietary communication protocols relied on by the servers.

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract: Apparatus and method for wireless communication in a wireless communication network includes mapping a PCI command to different symbols across a plurality of slots, allocating the PCI command to the plurality of slots, and transmitting the PCI command across the plurality of slots on an Fractional Transmit Precoding Information Channel (F-TPICH) from a network device to a user equipment (UE).

Abstract: A distributed PCIe adapted to support a hot-plug process triggered by any change in a status of a distributed link, comprises an upstream bus unit including a first bridge connected to a root component and adapted to maintain a first configuration space and a copy of a second configuration space, the first configuration space bridge includes at least hot-plug registers specifying at least capabilities and status of a slot of the first bridge; and a second bridge connected to an endpoint component and adapted to maintain the second configuration space, the second configuration space includes at least hot-plug registers specifying at least capabilities and status of a slot of the second bridge.

Abstract: A connector assembly includes first to fifth connectors, two PCIe slots, and an adapter board. When the first connector is connected to the fifth connector, and the third connector is connected to the fourth connector, signals at the pins of the third connector are transmitted to the second group of pins of the first PCIe slot through the fourth connector, the fifth connector, and the first connector in series. When the second connector is connected to the fifth connector, and the third connector is connected to the fourth connector, signals at pins of the third connector are transmitted to the fourth group of pins of the second PCIe slot through the fourth connector, the fifth connector, and the second connector in series.

Abstract: A peripheral component interconnect express (PCIe) switch includes non-transparent endpoints, each of which is associated with a bus hierarchy domain. A source non-transparent endpoint in a source bus hierarchy domain receives a packet including a destination address and identifies a destination bus hierarchy domain including a destination non-transparent endpoint based on the destination address. Further, the source non-transparent endpoint translates a requester identifier in the packet to a translated requester identifier and generates a translated request packet including the translated requester identifier. The PCIe switch routes the translated request packet to the destination non-transparent endpoint through a non-transparent interconnect in the PCIe switch. In this way, the PCIe switch interconnects multiple bus hierarchy domains and is non-transparent in the multiple bus hierarchy domains.

Abstract: In one embodiment, a system-on-chip (SoC) can be configured to receive a request from a master agent in a fabric coupled to the master agent, send a show command grant to the master agent responsive to selection of the request by the fabric, receive a command portion of a transaction corresponding to the request in the fabric and determine a target agent to receive the transaction based on the command portion, and thereafter send a transaction grant to the master agent for the transaction. Other embodiments are described and claimed.

Abstract: A bridge circuit 10 is provided between first data port A1, A2 and second data port B1, B2. The bridge circuit comprises a first transceiver stage 40 comprising at least one input buffer 11, 14 and at least one tri-state output buffer 12, 13 linked to the first data port, a second transceiver stage 50 comprising at least one input buffer 21, 24 and at least one tri-state output buffer 12, 13 linked to the second data port, a first detection circuit 31 for detecting the arrival of a packet by the first data port, a second detection circuit 37 for detecting the arrival of a packet by the second data port. A selection circuitry 34, 35 enables the output of tri-state output buffer of the first or of the second transceiver stage depending of the detection made by the first and second detection circuits.

Abstract: A network system that is part of a main system includes: a first PCI express-network bridge with a first control unit and a first PCI express adapter terminating a first PCI express bus; and a second PCI express-network bridge connected to the first PCI express-network bridge through a network. The second PCI express-network bridge includes a second control unit and a second PCI express adapter terminating a second PCI express bus, wherein the first control unit detects a destination of a packet sent from the first PCI express adapter, searches a physical address of the destination from a packet encapsulating table, and encapsulates the packet in a frame so that the frame includes the physical address, and wherein the second control unit removes the encapsulation tagged to the packet, and transfers the packet to the destination through the second PCI express bus by referring to a PCI express configuration register.

Abstract: A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. The plurality of hub interfaces provide a plurality of signal interfaces between the hub module and each of the plurality of spoke modules, wherein each of the plurality of signal interfaces is isolated from each of the other signal interfaces of the plurality of signals interface, and wherein each of the plurality of signal interfaces operates in accordance with a common signaling format.

Abstract: Mechanisms are provided for implementing a multi-root PCI manager (MR-PCIM) in a multi-root I/O virtualization management partition (MR-IMP) to control the shared functionality of an multi-root I/O virtualization (IOV) enabled switch fabric and multi-root IOV enabled I/O adapter (IOA) through the base functions (BF) of the switches and IOAs. A hypervisor provides device-independent facilities to the code running in the I/O Virtualization Management Partition (IMP), Multi-Root (MR)-IMP and client partitions. The MR-IMP may include device specific code without the hypervisor needing to sacrifice its size, robustness, and upgradeability. The hypervisor provides the virtual intermediary functionally for the sharing and control of the switch and IOA's control functions.

Abstract: A data storage apparatus having improved data transfer performance. The storage apparatus has: plural controllers connected to each other by first data transfer paths; plural processors controlling the controllers; and second data transfer paths through which the controllers send data to various devices. Each of the controllers has a data-processing portion for transferring data to the first and second data transfer paths. The data-processing portion has a header detection portion for detecting first header information constituting data, a selection portion for selecting data sets having continuous addresses of transfer destination and using the same data transfer path from plural data sets such that a coupled data set is created from the selected data sets, a header creation portion for creating second header information about the coupled data set, and coupled data creation means for creating the coupled data set from the selected data sets and from the second header information.

Abstract: A packet communication device autonomously selects an appropriate operation mode according to a connection environment to an external device before a service of the device is started. When the device is connected to the external buses, connection interface units notify an external device discrimination unit of connection of the device. The external device discrimination unit issues a polling packet to the connected device, discriminates the connected external device on the basis of the response packet, and notifies an operation mode switching unit. The operation mode switching unit selects an operation mode conforming to a connection environment of the packet communication device to the external device and switches the operation mode of the device to the mode.

Abstract: Upstream network interfaces (2-1-2-N) and downstream network interfaces (5-1-5-M) have an upstream PCI-PCI bridge function and a downstream PCI-PCI bridge function, respectively. These network interfaces (2-1-2-N, 5-1-5-M) and a network (3) are incorporated in a system as a single multi-root PCI express switch. The network (3) tunnels TLPs (Transaction Layer Packets) between the upstream network interfaces (2-1-2-N) and the downstream network interfaces (5-1-5-M) or between the downstream network interfaces (5-1-5-M). This enables to distribute and connect a plurality of computers and a plurality of I/Os on a large scale without changing software, root complexes, and I/Os.

Abstract: In an embodiment, an apparatus comprises a buffer, a plurality of processors, and a processor control module. The processor control module is to manage how many of the plurality of processors are used to process data from the buffer based at least in part on an amount of the data stored in the buffer.

Abstract: There is provided an interface card system for SD bus control. The interface card system for SD bus control includes a CPU bus interface 11a and/or an SD bus interface 11b, a host interface module 16 connected to the interfaces which interprets an SD command and controls operation of the whole of the interface card system, first and second internal SD host engines 15a and 15b which function as a host controller, first and second selectors 14a and 14b respectively connected to the internal SD host engines which each select a path for data or a command, first and second SD bus interfaces 13a and 13b respectively connected to the selectors, and a data pass-through control section 17 connected to the SD bus interfaces connected to the selectors which allows an SD command and data to pass through.

Abstract: An apparatus and a method for setting a primary port on a PCI multi-port bridge. More specifically, there is provided a method that comprises detecting a configuration signal at the PCI multi-port bridge and automatically setting the primary port on the PCI multi-port bridge based on the configuration signal. A system for implementing the method is also provided.

Abstract: To obtain a computer that can change over from the active system to the standby system without reconnecting the I/O adapters. The computer according to the present invention carries over the identifiers logically identifying connection paths between computer modules and I/O adapters from active computers to standby computers.

Abstract: An apparatus includes a PHY assembly in electrical communication with a first interface assembly and with a second interface assembly, the PHY assembly configured to receive a power signal from a PSE, the PHY assembly having a first PHY and a second PHY. The first PHY is configured to receive a first data signal from the PSE through the first interface assembly via the frame-based computer networking connection and provide the first data signal to the second PHY for transmission to a network device through the second interface assembly via the frame-based computer networking connection. The second PHY is configured to receive a second data signal from the network device through the second interface assembly via the frame-based computer networking connection and provide the second data signal to the first PHY for transmission to the PSE through the first interface assembly via the frame-based computer networking connection.

Abstract: An apparatus and method of low latency precedence ordering check in a PCI Express (PCIe) multiple root I/O virtualization (MR-IOV) environment. The precedence ordering check mechanism aids in enabling a port to comply with PCIe MR-IOV ordering rules. A posted information array mirrors a posted transaction queue, storing precedence order indicator and Virtual Hierarchy (VH) tag information for corresponding posted transaction entries stored in the posted transaction queue. The selector queries the posted information array periodically, such as each cycle, to determine whether the non-posted/completion transaction at the output of their respective queues have any preceding posted transactions of the same VH somewhere in the posted queue.

Abstract: A protocol adapter for transferring diagnostic signals between a vehicle network and a computer including a vehicle connector, a common connector plate, and a common electronics package. The vehicle connector is interfaced with the vehicle network. The common connector plate is interfaced with the vehicle connector. The common electronics package is interfaced with the common connector plate, and wirelessly transmits the diagnostic signals from the vehicle network to the computer.

Abstract: A supervisory control and data acquisition protocol converter having encoded meter register input ports which are able to interrogate, read, and retain data stored in viscous fluid or gas meter registers which communicate with the Automatic Meter Reading (AMR) protocols and convert that data upon request to an industrial monitoring and control system protocol such as MODBUS®, DF1, EtherNet/IP™, or ADAM 4000. The present art further provides serial RS-232C and RS-485, and Ethernet ports whereby said data may be transmitted and/or the apparatus may be setup according to user defined specifications. The present art apparatus also provides industrial standard pulse (0-5 volts) and current (4-20 milliamps) inputs. The present art further provides a user configurable display which may display any or only a portion of the aforesaid data along with other user desired data. The apparatus further serves a web page over the Ethernet port with the aforesaid data populating a table.

Abstract: In a first embodiment of the present invention, a method for multi-root sharing of a plurality of single root input/output virtualization (SR-IOV) endpoints is provided, the method comprising: CSR redirection to a management processor which either acts as a proxy to execute the CSR request on behalf of the host or filters it and performs an alternate action, downstream routing of memory mapped I/O request packets through the switch in the host's address space and address translation with VF BAR granularity, upstream routing of requests originated by I/O devices by table lookup indexed by Requester ID, and requester ID translation using a fixed local-global RID offset.

Abstract: Method and apparatus for providing failover operation for a connection between a first PCIE bridge and a first input/output (IO) device are provided. A first set of bussed bits is exchanged between the first PCIE bridge and the first IO device over a first link using a first set of lanes of the first PCIE bridge. In response to detecting a failure in the first link, at a PCIE bridge end, the first set of lanes is swapped with a second set of lanes of the first PCIE bridge for exchanging a second set of bussed bits between the first PCIE bridge and the first IO device over a second link using the second set of lanes, the second link connecting a second PCIE bridge with a second IO device.

Abstract: An apparatus for transmitting data across a high-speed serial bus includes an IEEE 802.3-compliant PHY having a GMII interface; an IEEE 1394-compliant PHY in communication with the IEEE 802.3-compliant PHY via a switch; the switch determining whether data transmission is be routed to the IEEE 802.3-compliant PHY or the IEEE 1394-compliant PHY; a first connection, the first connection for transmitting data between a device and the IEEE 802.3-compliant PHY; and a second connection, the second connection for transmitting data between a device and the IEEE 1394-compliant PHY.

Abstract: A device configured to switch a clock speed for multiple links running at different clock speeds and a method for switching the clock signals are disclosed. A frequency divider derives a plurality of clock signals at different frequencies from a source clock signal. A clock switching controller selects a maximum data rate among data rates requested by a plurality of ports of links and outputs a transmit clock signal at the selected maximum data rate to the ports along with a clock enabling signal for each of the ports. Each of the clock enabling signals selectively enables the transmit clock signal for matching a data rate requested by each port. The clock speed may be selected and updated as required by the ports glitch-free in a known amount of time without interrupting data transfers on any of the other ports.

Abstract: An adaptive USB extender is installed in a computer and includes a USB host controller mounted on a computer motherboard, a USB receptacle mounted on an I/O board, a USB cable interconnecting the I/O board and the USB host controller for transmitting USB-compliant signals, and an active signal driver mounted on the I/O board and connected between the USB receptacle and the USB cable for amplifying and buffering the USB-compliant signals, thereby maintaining the signal integrity of the USB-compliant signals.

Abstract: A USB system includes a USB hub, a USB device, and a USB bus interconnecting the USB hub and the USB device. The USB hub asserts a reset signaling on the USB bus to initiate a high-speed detection handshake. The USB hub and the USB device activate corresponding dual-mode squelch detectors in a first (handshake) mode of operation. The USB device transmits a device chirp signal to the USB hub. The USB hub responds with a sequence of hub chirp signals. The USB device detects the hub chirp signals and then the USB hub and the USB device establish a communication link in a high-speed mode of communication in accordance with USB 2.0. The dual-mode squelch detectors in the USB hub and the USB device can also be activated in a second (normal) mode of operation.

Abstract: A performance and power optimized computer system architecture and method leveraging power optimized tree fabric interconnect are disclosed. One embodiment builds low power server clusters leveraging the fabric with tiled building blocks while another embodiment implements storage solutions or cooling solutions. Yet another embodiment uses the fabric to switch non-Ethernet packets, switch multiple protocols for network processors and other devices.

Abstract: A computing system peripheral device compatible with the peripheral component interconnect express (PCI-E) protocol responds to a DL_DOWN command primitive by configuring a general-purpose input/output (GPIO) port into a known state without invoking a GPIO module reset. In addition, select resources are excluded from resources on the peripheral device that are issued a reset command. The select resources can include a GPIO module, a memory element and a PCI-E SERDES module. After the remaining reset resources have completed their individual initialization processes, the central processor core on the peripheral device is reset. The described response to the DL_DOWN command primitive avoids cache data loss, masks signal transitions on I/O ports and timing problems that prevent some peripheral devices from being recognized in a computer's basic input/output system (BIOS).

Abstract: A solution is presented to securing endpoints without the need for a separate bus or communication path. The solution allows for controlling access to endpoints by utilizing a management protocol by overlapping with existing interconnect communication paths in a packet format and utilizing a PCI address BDF (Bus number, Device number, and Function number) for verification.

Abstract: A data processing system includes a processor core, a system memory coupled to the processor core, an input/output adapter (IOA), and an input/output (I/O) host bridge coupled to the processor core and to the IOA. The I/O host bridge includes a register coupled to receive I/O messages from the processor core, a buffer coupled to receive I/O messages from the IOA, and logic coupled to the register and to the buffer that services I/O messages received from the register and from the buffer.

Abstract: A data processing system includes an input/output (I/O) host bridge to which at least one I/O adapter is coupled by an I/O link. In a register of the I/O host bridge, a configuration partitionable endpoint (PE) field is set to identify a PE to be used for an I/O configuration operation. Thereafter, the host bridge initiates the I/O configuration operation on the I/O link and determines if an error occurred for the I/O configuration operation. In response to a determination that an error occurred for the I/O configuration operation, an error state is set in the I/O host bridge only for the PE indicated in the configuration PE field of the register in the I/O host bridge, wherein I/O configuration errors are isolated to particular PEs.

Abstract: An apparatus and method are provided that enable I/O devices to be shared among multiple operating system domains. The apparatus has a first plurality of I/O ports, a second I/O port, and core logic. The first plurality of I/O ports is coupled to a plurality of operating system domains through a PCI Express fabric. Each of the first plurality of I/O ports is configured to route PCI Express transactions between said plurality of operating system domains and the switching apparatus. The second I/O port is coupled to a first shared input/output endpoint, where the first shared input/output endpoint is configured to request/complete said PCI Express transactions for each of the plurality of operating system domains. The core logic is coupled to the first plurality of I/O ports and the second I/O port. The core logic routes the PCI Express transactions between the first plurality of I/O ports and the second I/O port.

Abstract: A system and method using new PCI Express transaction layer packet headers so that unchanged header information within a burst of transactions does not need to be re-transmitted. After the first full packet header of a burst is sent, subsequent packet headers in the burst are smaller. Thus, more reduced headers can be transmitted over time with a resulting increased efficiency. Both sides of the PCI Express transaction must support this system and method for this approach to be enabled. Once enabled, both the PCI Express transmitter and receiver can use the regular full header PCI Express packets as well as the reduced header packets.

Abstract: A controller circuit can provide communication paths between multiple host devices and at least one function interface (I/F), where a function I/F can allow access to a predetermined circuit function. The controller circuit can include an endpoint buffer circuit having a plurality of storage locations configurable as endpoints according to a predetermined data transmission protocol and a data switching circuit coupled to the endpoint point buffer circuit. The data switching circuit is configurable to provide communication paths that enable a first host I/F and a second host I/F to access at least a same function I/F, and enable the first and second host I/Fs to communicate with one another.

Abstract: A system for implementing non-standard I/O adapters in a standardized input/output (I/O) architecture, the system comprising an I/O adapter communicatively coupled to an I/O hub via an I/O bus, the I/O adapter communicating in a first protocol, the I/O bus communicating in a second protocol different than the first protocol, and the I/O adapter including logic for implementing a method comprising initiating a first request to perform an operation on a host system, the first request formatted for the first protocol and comprising data required to process the first request, and creating a second request responsive to the first request, the second request comprising a header and formatted according to the second protocol, the creating comprising storing the data required to process the first request in the header of the second request. The method further comprising sending the second request to the host system.

Abstract: An electronic flash memory external storage method and device for data processing system includes firmware which directly controls the access of electronic storage media and implements standard interface functions, adopts particular reading and writing formats of the external storage media, receives power via USB, externally stores data by flash memory and access control circuit with the cooperation of the firmware and the driver with the operating system, and has write-protection so that the data can be safely transferred. The method according to present invention is highly efficient and all parts involved are assembled as a monolithic piece so that it has large-capacity with small size and high speed. The device operates in static state and is driven by software. It is plug-and-play and adapted to data processing system.

Abstract: An SE0 timer detects that an SE0 state of a universal serial bus continues for 3 ms or more, and asserts an SE03ms detected signal to a suspending/reset discriminating circuit. The suspending/reset discriminating circuit connects a pull-up resistor to a D+ data line, detects that the universal serial bus is in the SE0 state, and asserts a reset detected signal to a reset control circuit. The reset control circuit asserts a threshold level changing signal to a receiver for a high-speed mode. The receiver changes the threshold into 250 mV. When the reset control circuit detects a K state of the universal serial bus after chirp driving K is executed and ended, the reset control circuit negates the threshold level changing signal to the receiver. The receiver changes the threshold back to 125 mV.

Abstract: A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. The plurality of hub interfaces provide a plurality of signal interfaces between the hub module and each of the plurality of spoke modules, wherein each of the plurality of signal interfaces is isolated from each of the other signal interfaces of the plurality of signals interface, and wherein each of the plurality of signal interfaces operates in accordance with a common signaling format.

Abstract: A server computer system includes a set of visual indicators for representing status of one or more data storage devices that are connected to one or more nodes of the server system. Control circuitry has at least first and second bus interfaces and is configured to set the state of the visual indicators responsive to signals received through the bus interfaces, and to operate in at least first and second configurable modes. In the first mode, both of the first and the second bus interfaces communicate with a single node. In the second mode, the first bus interface communicates with a first node and the second bus interface communicates with a second node.

Abstract: Provided is a RAID controlled storage device of a PCI-Express (PCI-e) type, which provides data storage/reading services through a PCI-Express interface. The RAID controller typically includes a disk mount coupled to a set of PCI-Express SSD memory disk units, the set of PCI-Express SSD memory disk units comprising: a set of volatile semiconductor memories; a disk monitoring unit coupled to the disk mount for monitoring the set of PCI-Express memory disk units; a disk plug and play controller coupled to the disk monitoring unit and the disk mount for controlling the disk mount; a high speed host interface coupled to the disk monitoring unit and the disk mount for providing high-speed host interface capabilities; a disk controller coupled to the high speed host interface and the disk monitoring unit; and a host interface coupled to the disk controller.

Abstract: According to one embodiment of the invention, a data modifying bus buffer generally includes a switch that is configured to selectively couple a first databus to a second databus. The switch is controlled by a buffer controller. The first databus and a second databus have a similar predetermined protocol. The buffer controller is operable to monitor the first databus for the presence of a particular sequence of the signals such that, when the particular sequence of the signals is found, the first switch may be selectively opened or closed.

Abstract: A flash memory-based storage grouped into memory regions is controlled by determining whether the flash memory is accessed or not. Power to a first of the memory regions is controlled according to the determination result. Power to a second of the memory regions is controlled according to the determination result. Controlling includes enabling provision of power to the first memory region while concurrently denying power to the second memory region.

Abstract: A communication apparatus for carrying out communications to and from an external apparatus that includes a first interconnecting unit and a first non-transparent port and effects an interconnection for communications via the first non-transparent port is provided. The communication apparatus includes a second interconnecting unit that includes a second non-transparent port communicably connected to the first non-transparent port. The second interconnecting unit effects an interconnection for communications via the second non-transparent port. The second interconnecting unit performs, when the communication apparatus carries out communications to and from the external apparatus, address translation between an address for use by the communication apparatus and an address for use by the second non-transparent port.

Abstract: Provided is an MRA (multi-root aware) PCI express switch accommodating a plurality of root complexes. The MRA PCI express switch includes: a setting register storing necessary information to set a PCI tree based on a switch connection topology and a physical connection state; and a virtual switch bridge controller storing necessary information to establish a virtual PCI tree, irrespective of a status of the setting register. The root complexes can be booted based on the information in the virtual switch bridge controller.

Abstract: Routing circuitry for automatically routing either a first set of USB signals derived from an Ethernet local area network (LAN) at an Ethernet connector or a second set of USB signals derived from a USB host at a USB connector to an output connector which can interface with a data processing device.

Abstract: A server having remote peripheral device access functions for accessing different types of peripheral devices located on a remote host, such as USB, SATA and IDE devices. The remote device access function is implemented in the IPMI section of the server. The IPMI section is connected to a bridge of the server, and communicates with the bridge using a single predetermined communication protocol, such as the PCI protocol, regardless of the type of the peripheral devices being remotely accessed. An application on the remote host communicates with the IPMI section of the server to transmit the data generate by or to be consumed by the peripheral device using a predetermined network protocol.

Abstract: An apparatus for processing a PCI Express protocol, includes: a PCI Express transaction layer reception unit for transmitting status information, and performing a data writing operation; a PCI Express data link layer transmission unit for creating a flow control packet, transmitting the flow control packet to a PCI Express physical layer, and transmitting an integrity acknowledgement packet to the PCI Express physical layer; and a PCI Express physical layer for transmitting the flow control packet and the integrity acknowledgement packet to an upstream device, and transmitting the writing request packet to a PCI Express data link layer reception unit. Further, the apparatus includes a PCI Express data link layer reception unit for transmitting the writing request packet to the PCI Express transaction layer reception unit, and transmitting the integrity acknowledgement packet to the PCI Express data link layer transmission unit and a PCI Express transaction layer reception unit.