Abstract: PCIe is a point-to-point protocol. A PCIe switch fabric has multi-path routing supported by adding an ID routing prefix to a packet entering the switch fabric. The routing is converted within the switch fabric from address routing to ID routing, where the ID is within a Global Space of the switch fabric. Rules are provided to select optimum routes for packets within the switch fabric, including rules for ordered traffic, unordered traffic, and for utilizing congestion feedback. In one implementation a destination lookup table is used to define the ID routing prefix for an incoming packet. The ID routing prefix may be removed at a destination host port of the switch fabric.

Abstract: An example method is provided and includes receiving a first signal transmitted to an address on a two-wire bus from a master device, where the two-wire bus couples the master device with a first slave and a second slave that share the address such that the first slave and the second slave receive the first signal. The method includes blocking a second signal from the second slave to the master device using digital isolation buffers. In particular embodiments, the digital isolation buffers are configured between the master device and the second slave. In addition, the two-wire bus may include a clock line and a data line. The digital isolation buffers may include a first digital isolation buffer located on the clock line between the master device and the second slave, and a second digital isolation buffer located on the data line between the master device and the second slave.

Abstract: A system and method using new PCI Express transaction layer packet headers so that unchanged header information within a burst of transactions does not need to be re-transmitted. After the first full packet header of a burst is sent, subsequent packet headers in the burst are smaller. Thus, more reduced headers can be transmitted over time with a resulting increased efficiency. Both sides of the PCI Express transaction must support this system and method for this approach to be enabled. Once enabled, both the PCI Express transmitter and receiver can use the regular full header PCI Express packets as well as the reduced header packets.

Abstract: An electronic device includes a main board. The main board includes a number of PCI interfaces, an addressing unit, a determination unit, and a control unit. The addressing unit is configured for addressing addresses of each of the PCI interfaces of the main board from an address bus of the electronic device. The determination unit is configured for determining whether any PCI interfaces are not connected to corresponding PCI devices according to a value at the addressed addresses. The control unit is configured to turn off the PCI interfaces that are not connected to corresponding PCI devices. A method for controlling status of the PCI interfaces is also provided.

Abstract: Methods and devices for manipulating HDMI-CEC messages transmitted over a network including at least two HDMI-CEC display devices with their associated at least two HDMI-CEC cluster trees that at least partially overlap, and enabling each of the HDMI-CEC display devices to communicate using HDMI-CEC with its associated HDMI-CEC cluster tree according to its current HDMI-CEC network view.

Abstract: Methods and apparatus for implementing a port management protocol which can be used to manage communication between one or more USB devices and a USB host at a distance greater than that allowed by the USB Specifications are provided. In one aspect, a method for prolonging a bus event of a USB device at least until a notification is received that a corresponding bus event has been completed by the USB host is provided; and subsequently exchanging bus traffic between the USB host and USB device upon completion of the bus event by both devices.

Abstract: Methods and apparatus relating to increase Input Output Hubs in constrained link based multi-processor systems are described. In one embodiment, a first input output hub (IOH) and a second IOH are coupled a link interconnect and a plurality of processors, coupled to the first and second IOHs include pre-allocated resources for a single IOH. Other embodiments are also disclosed and claimed.

Abstract: A processor module includes at least one storage device, at least one central processing unit (CPU) that uses a preset interface, and a module controller to relay a connection between a common interface bus formed on the based board and an interface used by the CPU.

Abstract: An indication of a version of a firmware stored in an input/output adapter may be provided by a method that includes detecting whether a first pin is connected to an external circuit, detecting whether a second pin is unconnected to an external circuit, and causing the indication to be provided if the first pin is connected and the second pin is unconnected. The indication may be provided on the first pin. The first pin may include a power supply pin and the indication may be an average rate of power supplied to the input/output adapter.

Abstract: Embodiments of the invention relate to non-standard I/O adapters in a standardized input/output (I/O) architecture. An aspect of the invention includes initiating a first request to perform an operation on a host system. The first request formatted for a first protocol and including data required to process the first request. A second request is created responsive to the first request, the second request including a header and is formatted according to the second protocol. The creating includes storing the data required to process the first request in the header of the second request. The second request is sent to the host system.

Abstract: Methods and systems for mass storage of data over two or more tiers of mass storage media that include nonvolatile solid-state memory devices, hard disk devices, and optionally volatile memory devices or nonvolatile MRAM in an SDRAM configuration. The mass storage media interface with a host through one or more PCIe lanes on a single printed circuit board.

Abstract: Provided is an MRA (multi-root aware) PCI express switch accommodating a plurality of root complexes. The MRA PCI express switch includes: a setting register storing necessary information to set a PCI tree based on a switch connection topology and a physical connection state; and a virtual switch bridge controller storing necessary information to establish a virtual PCI tree, irrespective of a status of the setting register. The root complexes can be booted based on the information in the virtual switch bridge controller.

Abstract: A PCIe fabric includes at least one PCIe switch. The fabric may be used to connect multiple hosts. The PCIe switch implements security and segregation measures for host-to-host message communication. A management entity defines a Virtual PCIe Fabric ID (VPFID). The VPFID is used to enforce security and segregation. The fabric ID may be extended to be used in switch fabrics with other point-to-point protocols.

Abstract: Embodiments of the present invention disclose a peripheral component interconnect express interface control unit. The unit includes a P2P module, configured to receive a first TLP from a RC or an EP and forward the first TLP to a reliable TLP transmission RTT module for processing. A reliable TLP transmission module is configured to determine, according to the received first TLP, sending links connected to active and standby PCIE switching units, and send the first TLP to the active and standby PCIE switching units through the sending links at the same time. A destination PCIE interface controller of the first TLP selectively receives the first TLP forwarded by the active and standby PCIE switching units and sends the first TLP to a destination EP or a destination RC. Thereby, reliable transmission of a TLP is implemented in a case of a PCIE switching dual-plane networking connection.

Abstract: Embodiments of the present invention disclose a peripheral component interconnect express interface control unit. The unit includes a P2P module, configured to receive a first TLP from a RC or an EP and forward the first TLP to a reliable TLP transmission RTT module for processing; the reliable TLP transmission module, configured to determine, according to the received first TLP, sending links connected to active and standby PCIE switching units, and send the first TLP to the active and standby PCIE switching units through the sending links at the same time, so that a destination PCIE interface controller of the first TLP selectively receives the first TLP forwarded by the active and standby PCIE switching units and sends the first TLP to a destination EP or a destination RC, thereby implementing reliable transmission of a TLP in a case of a PCIE switching dual-plane networking connection.

Abstract: In one embodiment, a system-on-chip (SoC) can be configured to receive a request from a master agent in a fabric coupled to the master agent, send a show command grant to the master agent responsive to selection of the request by the fabric, receive a command portion of a transaction corresponding to the request in the fabric and determine a target agent to receive the transaction based on the command portion, and thereafter send a transaction grant to the master agent for the transaction. Other embodiments are described and claimed.

Abstract: Methods and apparatus for supporting dual casting of inbound system memory writes from PCIe devices to memory and a peer PCIe device. An inbound system memory write request from a first PCIe device is received at a PCIe root complex and the memory address is inspected to determine whether it falls within an address window defined for dual casting operations. If it does, an IO write request is generated from the inbound system memory write request and sent to a second PCIe device associated with the address window. During a parallel operation, the original inbound system memory write request is forwarded to a system agent configured to receive such write requests.

Abstract: A method and apparatus is described herein for supporting direct memory accesses between peer I/O devices. It is determined whether a guest physical address (GPA) referenced by an access generated from an I/O device, is within a range of GPAs associated with local I/O devices based at least in part on a GPA base and a GPA window size. If the GPA is within the window, then the GPA is translated to an HPA based at least in part on a base HPA associated with a local device and then forwarded to that local device. However, if the GPA is not within the window, then the access is forwarded upstream.

Abstract: A SAS expander forms a first path coupling the SAS initiator and a first port of a SAS target together. The first SAS expander notifies the SAS initiator of a virtual expander address instead of a SAS address of the first SAS expander. The first SAS expander notifies the SAS initiator of a virtual target port address, at least instead of a SAS address of the first port of the SAS target. A second SAS expander forms a second path coupling the SAS initiator and a second port of the SAS target together. The second SAS expander notifies the SAS initiator of the virtual expander address instead of a SAS address of the second SAS expander. The second SAS expander notifies the SAS initiator of the virtual target port address, at least instead of a SAS address of the second port of the SAS target.

Abstract: Disclosed are various embodiments for an interface between a host device and one or more peripheral devices in a computing system. A peripheral-side controller, a host-side controller, and a peripheral-side translator are located on a peripheral device that is in communication with a host device. The peripheral-side translator transfers data from an internal bus in the peripheral device to an external interface for the peripheral device. The internal bus is associated with a first bus protocol, and the external interface is associated with a second bus protocol.

Abstract: A universal serial bus (USB) signal test device includes a printed circuit board. A first connector, a second connector, and a number of USB hub integrated circuit (ICs) are arranged on the printed circuit board. The USB hub ICs are connected in series. A USB signal is passed through the USB hub ICs and an auxiliary test device in that order. The USB signals are measured with an oscilloscope after being passed through the USB hub ICs and the auxiliary test device.

Abstract: Virtual Functions (VFs) 602-1 to 602-N of an I/O device are separately allocated to a plurality of computers 1-1 to 1-N. In an address swap table 506, a root domain that is an address space of the computer 1 and mapping information of an I/O domain that is an address space unique to the I/O device 6 are registered. Mapping is set with the VFs 602-1 to 602-N as units. When accessing the VFs 602-1 to 602-N of the I/O device 6 to which each of the computers 1-1 to 1-N is allocated, an I/O packet transfer unit 701 checks the address swap table 506 to swap source/destination addresses recorded in packet headers.

Abstract: A method for computing includes connecting a host device to a peripheral device via a bus that is physically configured in accordance with a predefined standard and includes multiple connection pins that are specified by the standard, including a plurality of ground pins. At least one pin, selected from among the pins on the bus that are specified as the ground pins, is used in order to indicate to the peripheral device that the host device has an extended operational capability.

Abstract: A management hub is disclosed. The management hub comprises an interface; a master hub controller coupled to the interface; a plurality of ports coupled to the master hub controller; a microcontroller coupled to the master hub controller; and hub setting switch and a slave hub controller coupled to the microcontroller and the plurality of ports. The management hub also includes a memory device coupled to the microcontroller, the memory device including a hidden drive information partition and a hidden drive organizer partition for managing and identifying information in various drives coupled to the plurality of ports, wherein when the management hub is first connected to a host system the drives are displayed in an inactive state.

Abstract: In one embodiment, the present invention is directed to an integrated endpoint having a virtual port coupled between an upstream fabric and an integrated device fabric that includes a multi-function logic to handle various functions for one or more intellectual property (IP) blocks coupled to the integrated device fabric. The integrated device fabric has a primary channel to communicate data and command information between the IP block and the upstream fabric and a sideband channel to communicate sideband information between the IP block and the multi-function logic. Other embodiments are described and claimed.

Abstract: A hybrid computing system comprising: a network fabric; at least one Root Complex board (RCB) and at least one Endpoint Board (EB). Each Root Complex board (RCB) comprises a first processor; a PCIe root complex connected to the first processor; and a first PCIe network switch directly connected to the PCIe root complex. Each Endpoint Board (EB) comprises a second processor; a PCIe interface connected to the second processor; and a second PCIe network switch connected to the PCIe interface. The PCIe network switches of each board (RCB, EB) are connected to the network fabric wherein each Root Complex board (RCB) and each Endpoint Board (EB) are configured for simultaneous use within the hybrid computing system.

Abstract: Embodiments of the invention relate to upbound input/output expansion requests and response processing in a PCIE architecture. A first request to perform an operation on a host system is intitiated. The first request is formatted for the first protocol and includes data that is required in order to process the first request. A second request is created in response to the first request, the second request includes a header and is formatted according to the second protocol. The data required to process the first request in the header of the second request is stored, and the second request is sent to the host system.

Abstract: The present subject matter discloses methods and systems of application sharing in multi-host computing system (100) running multiple operating systems. In one embodiment, the method for application sharing in a multi-host computing system (100) comprises receiving a request to launch an application in a first operating system of the multi-host computing system (100) from a second operating system of the multi-host computing system (100), generating an application launch request to launch the application and transmitting the application launch request to a widget daemon running on the first operating system using a PCIe to PCIe application redirection engine. The method further comprises initiating an application sharing session between the first operating system of the multi-host computing system (100) from the second operating system of the multi-host computing system (100).

Abstract: A data transfer device includes a serial interface including plural transmission paths and carrying out a data transfer operation with plural operating frequencies, transfer requesting units issuing a data transfer request to the serial interface, a request monitoring unit, a condition setting unit setting a set transmission path condition including at least one of a number of the transmission paths and an operating frequency used when the data transfer requests are issued to switch statuses of the data transfer requests to statuses of switching data transfer requests, a use transmission path condition determining unit determining the set transmission path condition corresponding to the status of the switching data transfer request as a use transmission path condition when the status of switching data transfer request corresponds to the status of data transfer request by comparing the statuses, and a switching unit switching to the use transmission path condition.

Abstract: Accessing data stored in a memory device through an interface, with addressing data on the memory device through at least one address bus, controlling at least data flow to and from the memory device through at least one command bus, and transferring data to and from the memory through at least one data bus wherein commands on the command bus are adjusted depending on the type of memory connected to the interface.

Abstract: A method and apparatus for host enumeration process. One embodiment of the method provides a bit to indicate to the host whether enumeration process should start or continue. The bit may be set when the shared resource process has been successfully completed, or the bit may be set if too much time has elapsed since the shared resource process has started, or the bit may be set if too much time has elapsed before the shared resource process is started, or the bit may be set if the shared resource process has not been performed successfully, or the bit may be set if the port is open and it is unnecessary to perform the shared resource process.

Abstract: To obtain a computer that can change over from the active system to the standby system without reconnecting the I/O adapters. The computer according to the present invention carries over the identifiers logically identifying connection paths between computer modules and I/O adapters from active computers to standby computers.

Abstract: Provided is a dynamically configurable wireless data bus switch for coupling a data bus to a wireless link. For example, there is a dynamically configurable wireless data bus switch including a configurable protocol adaption layer data plane providing a first interface to a data bus and a processor configured to execute a protocol adaption layer control plane. The configurable protocol adaption layer data plane of the dynamically configurable wireless data bus switch is coupled to the processor and is dynamically configurable by the protocol adaption layer control plane.

Abstract: Embodiments of the present disclosure provide a PCIe interface module and a physical layer to negotiate a link by exchanging a number of fast training sequences (N_FTS). The physical layer may count the number of good FTSs exchanged during an initial or a subsequent link training. The number of FTSs to be exchanged during a subsequent link training may be a number in which a maximum initial number of fast training sequences to be exchanged is reduced by the number of good FTSs exchanged during the initial link training, reducing link training time and increasing efficiency.

Abstract: In some embodiments, a serial bus interface circuit includes at least two serial ports, a memory to store a relationship between serial bus addresses and the at least two serial ports, and a controller to control access to the at least two serial ports. The controller may be configured to receive an access request for a serial bus address, determine a first port of the at least two serial ports corresponding to the serial bus address using the relationships stored in the memory, and disable a second port of the at least two serial ports. Other embodiments are disclosed and claimed.

Abstract: A computing device is provided that includes a computing unit, which has a working memory and a processing unit, and a boot memory having control instructions for operating the computing device. The control instructions are stored in boot memory and are to be transferred to the computing unit at start-up of the computing device. A boot control unit is connected to the computing unit by at least a first and a second interface and connected to the boot memory by a third interface. The boot control unit is configured to transfer a first part of the control instructions from the boot memory via the first interface to the computing unit and to transfer a second part of the control instructions from the boot memory via the second interface to the computing unit.

Abstract: A wireless Internet access device, a secure digital (SD) control chip, and a data communication method are disclosed. The method includes the following steps: the wireless Internet access device receives an SD command from a terminal device, where the SD command is converted by the terminal device from a command and/or data sent by an upper layer; the wireless Internet access device determines an interface mode according to the SD interface support of the terminal device; the wireless Internet access device executes the SD command according to the interface mode. In embodiments of the present invention, the SD card is integrated with the wireless Internet access function, which reduces the size of the wireless Internet access device and enables the wireless Internet access device to select a proper mode to meet different service requirements of terminal devices according to the SD interface support of different terminal devices.

Abstract: A multi-function integrated device and an operating method thereof are provided. The multi-function integrated device includes a data reading module, a network access module, and a power control module. The network access module includes a first network component corresponding to a LAN and a second network component corresponding to a WLAN. The power control module turns on the function of the data reading module and/or the network access module according to a control signal received from a host. When the function of the network access module is determined to be turned on, the power control module supplies power to the first network component or the second network component according to the control signal.

Abstract: A connector assembly includes first and second connectors, a flexible printed circuit board, first and second peripheral component interconnection express (PCIe) slots, and a jumper card. When the jumper card is plugged into the first PCIe slot, pins of the jumper card are connected to pins of the first PCIe slot for transmitting signals to the pins of the first PCIe slot and to the pins of the first connector in that order. When the first connector is connected to the second connector, signals at the pins of the first PCIe slot are transmitted to pins of the second PCIe slot.

Abstract: The present invention provides a information transmission device including: a transmission section that transmits information to a first transmission path that transmit information serially; a reception section that receives information from a second transmission path; a waveform shaping section that, according to setting information, shapes at least one of a signal waveform of the information for transmission, and/or a signal waveform of the information for reception; and a controller that, when establishing communication, controls the transmission section to transmit predetermined first information that requests communication establishment, and effects control to change the first setting information and controls the transmission section to re-transmit the first setting information when the reception section has not received the first information within an interval that from the beginning of transmission of the first information until a predetermined duration required for communication establishment has elap

Abstract: A system for enhancing universal serial bus (USB) applications comprises an upstream processor, a downstream processor and a main controller. The upstream processor accepts standard USB signals from a USB host and independently provides responses required by USB specification within the required time frame. The upstream processor also contains storage for descriptors for a device associated with this upstream processor. The main controller obtains the descriptors by commanding the downstream processor, and passes them to the upstream processor. The downstream processor connectable to USB-compliant devices accepts the USB signals from the USB-compliant devices and provides responses required by USB specification within the required time frame. The main controller interconnects the upstream and downstream processors, and provides timing independence between upstream and downstream timing. The main controller also commands the downstream processor to obtain device descriptors independent of the USB host.

Abstract: A SAS expander collects data access information associated with a nexus and determines whether a data prefetch is appropriate. The SAS expander identifies potential data blocks utilizing previous data requests of the nexus. The SAS expander issues a data request to the target for the potential data blocks. The SAS expander stores the potential data blocks within a prefetch cache for future utilization within a data read.

Abstract: A method and system for providing computer input/output (I/O) functionality within a remote computing environment. The system comprises a host audio controller and a remote audio controller for bridging audio data between a host computing system and at least one remote audio device, a host USB controller and a remote USB controller for bridging USB data between the host computing system and at least one remote USB device, and an encoder module and a remote display decoder for bridging a digital video signal from the host computing system to a remote display, wherein the host audio controller, the host USB controller, and the encoder module are communicatively coupled to the remote audio controller, the remote USB controller, and the remote display decoder, respectively, via a computer network.

Abstract: Exemplary embodiments describe a system and a method for performing the functions of a PCI Express feature card remotely from a data processing system. The system is comprised of a circuit board connected to a PCI-E feature card. The PCI-E feature card is remotely located in comparison to the circuit board. Architecturally, the PCI-E feature card appears to the circuit board to be located at the circuit board.

Abstract: An integrated circuit (IC) configured to operate as a slave on an inter-integrated circuit (I2C) or I2C compatible bus. The IC is further configured to receive an address through the I2C bus and store the received address in a register, so as to be identified by the address. A method of address assignment in a master/slave system, the system comprises at least one master, a plurality of slaves, and an I2C or I2C compatible bus. The method comprises sending a first address by the master on the I2C bus to a first of the plurality of slaves and storing the first address on the first slave to identify the first slave by the first address. The method further comprises sending a second address by the master on the I2C bus to a second of the plurality of slaves and storing the second address on the second slave to identify the second slave by the second address. The steps of sending and storing are repeated until all slaves of the system have stored an address.

Abstract: An improved PCI Express multiplier device is disclosed. The PCI Express multiplier device comprises two or more device attachers to attach at least two identical PCI Express devices; a root complex attacher to attach a PCI Express root complex; a copier to copy and forward PCI Express data packets from the root complex to all of the attached identical devices; a collector to collect PCI Express data packets sent from the attached identical devices to the root complex; a selector responsive to the collector to select and forward PCI Express data packets from the collected PCI Express data packets to the root complex.

Abstract: An apparatus and method of fast PCIe multi-function device address decode utilizing a target function data look up table. One or more decode directives (e.g., targeted functions) are provided within the PCIe request packet, thereby eliminating the need for target function search during the decode process in the endpoint device. This enables single-decoder single-step decode implementation in complex multi-function devices.

Abstract: Devices, systems and methods for providing a ring topology for physically connecting compute devices having PCIe bridges are disclosed. Each device, having an internal PCIe bus or other similar standard that natively support a tree structure, is connected in a ring to neighboring compute devices. Two physical links connecting each device to the ring are provided, enabling each device to communicate with all of the other devices on the ring, without requiring a server or main host to enumerate or control the flow of information between devices. If a failure occurs in the physical connection at any single point in the ring, there is still an alternate path to communicate with every device. Methods for performing data transfer between PCIe compute devices connected to the ring are also disclosed.

Abstract: A system for transmitting and receiving data using an industrial expansion bus connected to a chassis is provided, the industrial expansion bus having a plurality of module slots, the system having a programmable logic controller (PLC) control rack and a PLC remote rack. The PLC control rack has a first embedded central processing unit (CPU), and a first peripheral component interconnect express (PCIe) module adapted to send and receive PCIe compliant signals. The PLC remote rack has a second PCIe module adapted to send and receive PCIe compliant signals, and a second embedded CPU. The first PCIe module and the second PCIe module are communicatively coupled with cable to provide an interface between the first and second CPUs. A method for polling a local peripheral and a distant peripheral is also provided.

Abstract: Methods and apparatus are provided for implementing a lightweight notification (LN) protocol in the PCI Express base specification which allows an endpoint function associated with a PCI Express device to register interest in one or more cachelines in host memory, and to request an LN notification message from the CPU/memory complex when the content of a registered cacheline changes. The LN notification message can be unicast to a single endpoint using ID-based routing, or broadcast to all devices on a given root port. The LN protocol may be implemented in the CPU complex by configuring a queue or other data structure in system memory for LN use. An endpoint registers a notification request by setting the LN bit in a “read” request of an LN configured cacheline.