Abstract: To adjusts protocol and analog characteristics of an interface automatically, there is provided a data input/output device coupled to a host computer for inputting and outputting data to and from the host computer, including: an interface coupled to an interface of the host computer; and a controller for controlling the interface of the data input/output device, wherein the controller is configured to: measure an analog characteristic of the interface of the host computer and a protocol characteristic of the interface of the host computer when the data input/output device is reset; and adjust an analog characteristic of the interface of the data input/output device to an optimum value based on a result of the measurement, and then adjust a protocol characteristic of the interface of the data input/output device to an optimum value.

Abstract: A system and method for identifying a peripheral component interconnect express (PCIe) signal obtains a waveform of the PCIe signal. A pre-emphasis value of the PCIe signal is calculated according to the waveform. Accordingly, a signal type of the PCIe signal is determined.

Abstract: An Input/Output (IO) Virtualization (IOV) system provides a mechanism for sharing computer peripheral devices or resources between multiple host computers by presenting a single resource multiple times to numerous host systems. The IOV system provides IO virtualization and host-to-host communication services to the host computers. The system comprises device interfaces coupled to the IO devices. Each IO device comprises at least one endpoint function (EPF). Host interfaces are each coupled to one of a number of host computers. Each host interface includes a proxy, and each proxy comprises configuration data.

Abstract: Methods and apparatus are provided for improving communication between processors in separate computer systems. Components and peripherals in individual computer systems communicate using input/output (I/O) buses such as PCI Express buses. The I/O buses are extended to allow interconnection between computer systems without having to introduce network infrastructure. A transfer controller supporting Direct Memory Access (DMA) is provided to allow even more efficient communication between computer systems.

Abstract: Described are electronics systems and methods for distributing a limited number of lanes of a PCI Express-based processor (CPU) module among a plurality of PCI Express-based I/O modules with which the CPU module is in communication. The CPU module receives a code from each I/O module over a sideband interface between that I/O module and the CPU module. The coded signal represents a link-width capability of the I/O module. The CPU module is configured to allocate a link width to each I/O module based on the fixed number of lanes and the link-width capability as represented by the coded signal received from that I/O module. The link between CPU module and each I/O module is trained in accordance with the link width allocated to that I/O module.

Abstract: A dynamically configurable logic gate includes an input summer for receiving a first input signal and a second input signal to generate a summed input signal. Further the dynamically configurable logic gate includes a nonlinear element that applies a nonlinear function to the summed input signal to produce a nonlinear output signal. The dynamically configurable logic gate output signal corresponds to one of a plurality of different logic gates responsive to adjusting the summed input signal and/or the nonlinear function. In another embodiment, the dynamically configurable logic gate includes feedback to one of the inputs. The dynamically configurable logic gate receives the two inputs and operates as one of a plurality of different logic gate types so as to produce an output signal that corresponds to a memory latch according to a selection of the control signal. An array structure of dynamically configurable logic elements is also disclosed.

Abstract: A PCI Express switch which connects a plurality of peripheral devices to an arbitrary one of a plurality of CPUs through an Ethernet is constituted by a plurality of upstream and downstream PCI Express-network bridges, an Ethernet switch, and a system manager. Each of the upstream and downstream PCI Express-network bridges includes a PCI Express adapter which terminates a link of a PCI Express bus, a network adapter which terminates a link to the Ethernet switch, and a control unit which encapsulates a TLP in a frame, the destination of which is a MAC address of a bridge to which the destination is connected to transmit and receive the frame. Because the switch according to the present invention comprising a plurality of upstream PCI Express-network bridges and a plurality of downstream PCI Express-network bridges connected to the plurality of upstream PCI Express network bridges through a network is equivalent to a conventional PCI Express switch, it is needless to change a conventional PCI software.

Abstract: Port Interface Modules (PIMs) are provided for ports of a Multi-Port Memory Controller. The PIMs include logic that is programmable to be compatible with different types of devices, processors or buses that can be connected to the ports. The PIMs can further include protocol bridges to enable one port PIM to connect to a device or another port PIM in a master/slave fashion.

Abstract: A means for extending the Input/Output System of a host computer via software-centric virtualization. Physical hardware I/O resources are virtualized via a software-centric solution utilizing two or more host systems. The invention advantageously eliminates the host bus adapter, remote bus adapter, and expansion chassis and replaces them with a software construct that virtualizes selectable hardware resources located on a geographically remote second host making them available to the first host. One aspect of the invention utilizes 1 Gbps-10 Gbps or greater connectivity via the host systems existing standard Network Interface Cards (NIC) along with unique software to form the virtualization solution.

Abstract: A connectivity hub enabling multiple peripheral devices to be connected with a computer includes a stationary base station functioning as a connectivity hub and a removable connectivity hub functioning by itself as a travel connectivity hub. The removable travel hub can be plugged into the stationary base station by connecting an upstream port of the removable hub to a downstream port of the base station. Thus, a user of the connectivity hub achieves the functionality of a full-featured connectivity base station as well as that of a small, easily transportable travel hub without having to purchase multiple units.

Abstract: An analog/digital switching circuit for connecting a primary electronic device to a peripheral electronic device, including D+ and D? signal lines connected to a primary electronic device, a first analog/digital switch connected to the D+ signal line, for multiplexing an input D+ signal to an output USB data signal or audio left or right signal, the multiplexed signal feeding into a peripheral device connector for connecting the primary device to a peripheral electronic device, a second analog/digital switch connected to the D? signal line, for multiplexing an input D? signal to an output USB data signal or audio right or left signal, the multiplexed signal feeding into the peripheral device connector, a headset left signal line connected to the primary device and to the output audio left signal of the first analog/digital switch, a headset right signal line connected to the primary device and to the output audio right signal of the second analog/digital switch, a first USB signal line connected to a USB conn

Abstract: A solution enabling the practical use of very large amounts of memory, external to a host computer system. With physical locality and confinement removed as an impediment, large quantities of memory, here before impractical to physically implement, now become practical. Memory chips and circuit cards no longer must be installed directly in a host system. Instead, the memory resources may be distributed or located centrally on a network, asconvenient, in much the same manner that mass storage is presently implemented.

Abstract: A semiconductor storage device includes an external input/output port. A system bus of a server, which is extended to outside of the server, is connected to the external input/output port directly as a serial interface.

Abstract: A method and an apparatus are provided for restricting input/output device peer-to-peer operations in a data processing system to improve reliability, availability, and serviceability. A peer-to-peer (P2P) control logic is provided to perform a lookup of P2P lookup table entries. Each P2P lookup table entry comprises bus, device and function number fields, optional control fields, and an accept/reject bit. Upon receiving a communication request from a requesting I/O device, P2P control logic implemented in either a logical bridge or an I/O device identifies the requester ID of the request and determines if a match exists in the P2P lookup table entries. If a match is found and the accept/reject bit is enabled, I/O operations can be received from the requester.

Abstract: An Input/Output (IO) Virtualization (IOV) system couples or connects multiple host computers and IO devices to a managed transport fabric to provide IO virtualization. The host computers may run any operating system to provide a virtualized environment for guest operating systems. The host interface to the IOV system is PCI-Express (PCIe). The IO devices are PCIe based to provide maximum compatibility with industry standard devices, but are not so limited. The IOV system comprises a management central processor unit (MCPU) coupled to transport fabric. The IOV system comprises device interfaces coupled to the transport fabric and to independent input/output (IO) devices. Each device interface couples to the IO device of the independent IO devices. The IOV system comprises host interfaces coupled to the transport fabric. Each host interface couples to a host computer of the independent host computers and exposes functions of the independent IO devices to the host computer.

Abstract: An information processing device includes: an address converter including a base address register in which address conversion information is stored and a conversion circuit that converts a PCI Express standard bus address of an inputted packet to a non-PCI Express standard bus address; and a packet generator. When first configuration information of a first device that has a device-unique unique address, is connected to a non-PCI Express standard bus and is unaware of the unique address is stored, the packet generator generates an address setting-use configuration write request packet, and when second configuration information including change information for changing the base address register to a base address register of a second device where at least one of an address width and an internal memory address is a device-unique unique value, the packet generator generates a change setting-use configuration write request packet and outputs the generated packet to the address converter.

Abstract: A serial input processing apparatus provides how to capture serial data without loss of a single bit while command interpretation is being performed in a command decoder at high frequency. Individual bytes of serial bits of a pre-defined sequence are latched and bit streams are temporarily stored with multiple clocks. The temporary store is conducted before transferring byte information to assigned address registers to register the address. The address registration and the data registration are performed by latching all bit streams of the serial input at the leading edges of clocks. While at a high frequency operation (e.g., 1 GHz or 1 ns cycle time), no additional registers are required for storing bit data during command interpretation with enough time margins between the command bit stream interpretation and next bit data stream.

Abstract: Aspects of a method and system for optimized power management for a network device supporting PCI-E and energy efficient Ethernet are provided. In this regard, in a network interface controller that supports energy efficient Ethernet, a PCI-E core may be transitioned from a low power PCI-E state to a full power PCI-E state when a PHY core in the network interface controller initiates transition from a low power mode to a full power mode and before the PHY core receives an Ethernet packet. In another embodiment, the PHY core in the network interface controller may be transitioned from a low power mode to a full power mode when the PCI-E core initiates transition from a low power PCI-E state to a full power PCI-E state, and before the PCI-E core receives a command to send an Ethernet packet.

Abstract: A device receives a first request from a requesting device for first information that is stored at contiguous address locations beginning at a first address. A plurality of spawned requests are generated that each request a different portion of the first information. A table location is allocated to each one of the plurality of requests, wherein the relative location of each allocated table location is indicative of an order that the information from each spawned request is to be returned to the requesting device relative to the information from each other spawned request.

Abstract: A hardware/software system and method that collectively enables virtualization of the host computer's native I/O system architecture via the Internet and LANs. The invention includes a solution to the problems of the relatively narrow focus of iSCSI, the direct connect limitation of PCI Express, and the inaccessibility of PCI Express for expansion in blade architectures.

Abstract: A system that includes a docking station comprising a graphics processor and a transceiver. The system also includes a computer comprising a display. The computer is in communication with the docking station. The graphics processor receives input signals from the computer and, as a result, provides output signals to the computer. The computer uses the output signals to display images on the display.

Abstract: A method and apparatus are provided to enable a plurality of standard USB peripheral devices, utilizing the USB specification, to be distributed at various nodes across a network, wherein communications across the network may take advantage of any pre-existing network connectivity of a standard, non-modified USB host computer. In particular, a reflector function is added in order to reflect data communications towards a pre-existing transceiver. As a result, the host computer establishes a first profile and second profile for data communication purposes, and uses these profiles to communicate across the network using pre-existing data communication components.

Abstract: A device includes a connector having first and second signal pins adapted to, when the connector is being connected to a mating connector of another device, make a first connection using the first signal pin prior to making a second connection using the second signal pin, a first circuit operatively coupled to the first signal pin and configured to identify at least three pre-determined signal patterns receivable from the another device using the first connection, wherein each of the at least three pre-determined signal patterns corresponds to one of at least three pre-determined interface protocols, and a second circuit operatively coupled to the first circuit and the second signal pin, wherein the second circuit is configured, responsive to the first circuit identifying a pre-determined signal pattern of the at least three pre-determined signal patterns, to interface with the another device using at least the second signal pin, wherein to interface with the another device is according to a pre-determined in

Abstract: Upstream network interfaces (2-1-2-N) and downstream network interfaces (5-1-5-M) have an upstream PCI-PCI bridge function and a downstream PCI-PCI bridge function, respectively. These network interfaces (2-1-2-N, 5-1-5-M) and a network (3) are incorporated in a system as a single multi-root PCI express switch. The network (3) tunnels TLPs (Transaction Layer Packets) between the upstream network interfaces (2-1-2-N) and the downstream network interfaces (5-1-5-M) or between the downstream network interfaces (5-1-5-M). This enables to distribute and connect a plurality of computers and a plurality of I/Os on a large scale without changing software, root complexes, and I/Os.

Abstract: A switch system has a master sub-switch and a slave sub-switch, the master sub-switch having a first bridge for transmitting the received packet via the first bus, a second bridge for transmitting the packet when the address information of the second bridge matches with the address information included in the packet, and a third bridge for receiving the packet from the first bridge and transmitting the packet to the slave sub-witch, the slave sub-switch having a fourth bridge for receiving the packet from the third bridge and transmitting the packet, and a fifth bridge for receiving the packet from the fourth bridge, and transmitting the packet when the address information of the fifth bridge matches with the address information included in the packet, wherein the master sub-switch has a table including address information of the fifth bridge, and transmits the packet to the fifth bridge in reference to the table.

Abstract: A programmable controller includes a switching unit that switches functions of a serial port so that the serial port can process a general-purpose communication protocol, a computer link-only protocol, and does nothing based on a command received from outside.

Abstract: A method and system for probing FCode in problem state memory. A PCI device is detected from a PCI-PCI bridge node included in a device tree. A child node for the detected PCI device is created in problem state memory. The active package is switched to the child node, and the processor switches from running in privileged mode to running in problem mode. FCode of an FCode driver in the PCI device is probed. Data, properties and methods generated in response to the probe are created in problem state memory. After the probe is complete, the active package is switched to the parent node of the child node, and the processor switches back to running in privileged mode.

Abstract: An electronic flash memory external storage method and device for data processing system, includes firmware which directly controls the access of electronic storage media and implements standard interface functions, adopts particular reading and writing formats of the external storage media, receives power via USB, externally stores date by flash memory and access control circuit 2 with the cooperation of the firmware, driver and operating system, and has write-protection so that the data can be safely transferred. The method according to present invention is highly efficient and all parts involved are assembled as a monolithic piece so that it has large-capacity with small size and high speed. The device operates in statistic state and is driven by software. It is plug-and-play and adapted to data processing system.

Abstract: According to one embodiment of the invention, a data modifying bus buffer generally includes a switch that is configured to selectively couple a first databus to a second databus. The switch is controlled by a buffer controller. The first databus and a second databus have a similar predetermined protocol. The buffer controller is operable to monitor the first databus for the presence of a particular sequence of the signals such that, when the particular sequence of the signals is found, the first switch may be selectively opened or closed.

Abstract: This invention provides an electronic device that can suppress the undesired influence of signals flowing on the bus as interference on devices connected to the bus. The electronic device has two ports connected to the bus with corresponding physical layer processing means. The physical layer processing means may optionally be connected together permitting separate connection to separate busses. Thus a bus reset on first bus will not interfere with processing on the second bus.

Abstract: A computer capable of automatic bandwidth configuration according to I/O expansion card (e.g., PCI-Express expansion card) type is provided. A motherboard of the computer includes an I/O expansion slot, a chipset, and a configuration setting circuit. When the I/O expansion slot supports different types of I/O expansion cards having multiple interface card slot combinations, a corresponding bandwidth configuration message is generated on the I/O expansion card. The bandwidth configuration message is used to indicate the type of the I/O expansion card that is being used and thereby control the configuration setting circuit to adjust the bandwidth configuration in the chipset.

Abstract: A network interface is described in which a single computer bus is split over a long distance into two or more intercommunicating buses. On one bus, processing and applications are provided and on the other remote bus, peripheral and local controllers are provided. The buses communicate through a series of: bridge, a first communications controller, a second communications controller, and bridge. Between the communications controllers, a communication path provides long distance communication via a packet-switched network.

Abstract: A method for transmitting data between two storage virtualization controllers (SVCs) is disclosed in the present invention.

Abstract: A communication control apparatus for common bus connection devices is provided between a plurality of devices to which addresses are allocated and a common bus and controlling an access between each of the plurality of devices and the common bus, the communication control apparatus includes: an input determination unit configured to recognize an identification signal indicating the beginning and end of a packet for the common bus which is an information unit capable of being transmitted by one transfer operation through the common bus and determining whether or not there is an input from the common bus to the device in question, a transmission determination unit configured to determine whether or not there is a transmission of the packet from the device in question on the common bus to the common bus, and an access suspend unit configured to determine that another device on the common bus is performing a packet operation and suspending a clock in each unit in the device in question when the input determinati

Abstract: An USB matrix switch system provided for a plurality of USB devices shared with a plurality of hosts is disclosed.

Abstract: According to one embodiment of the invention, a data modifying bus buffer generally includes a switch that is configured to selectively couple a first databus to a second databus. The switch is controlled by a buffer controller. The first databus and a second databus have a similar predetermined protocol. The buffer controller is operable to monitor the first databus for the presence of a particular sequence of the signals such that, when the particular sequence of the signals is found, the first switch may be selectively opened or closed.

Abstract: A switch (304) includes a plurality of bridges (3041, 3042, 3043, 3044, 3045) and a switch forwarding mechanism (20). Each of the bridges transmits and receives a TLP frame complying with PCI express to and from a device connected to each of the bridges. The switch forwarding mechanism includes a plurality of ports (1, 2, 3, 4, 5) to which the bridges are connected, respectively, selects an output port in dependence on a combination of destination information on the TLP frame input from one of the plurality of ports and the port which input the TLP frame, and outputs the TLP frame from the selected output port.

Abstract: A method and device for handling catastrophic switch routing errors. Upon receiving a communication packet in a packet switching device, a port in the switching device is matched with the destination address of the communication packet and a routing code is generated to direct routing of the communication packet internally to the packet switching device. The routing code is analyzed to determine whether a catastrophic routing condition exists in the routing code. If no catastrophic routing condition exists, the routing is executed. However, when there is a catastrophic routing condition, execution of the routing of the communication packet is prevented.

Abstract: Techniques are disclosed for enabling a single computer system to execute both operating systems that permit multiple devices to be mapped to a single PCI function and operating systems that do not permit such mapping. Prior to loading and executing an operating system (e.g., during system reset), the computer system determines whether the operating system supports mapping of multiple devices to a single function. If such mapping is supported, the computer system maps multiple devices on a single PCI card to a single function in the PCI configuration space for the card. If such mapping is not supported, the computer system maps each device to a separate PCI function. The computer system then loads and executes the operating system. The operating system is thereby enabled to access all devices on the bus according to the particular device-function mapping scheme supported by the operating system.

Abstract: The present invention relates generally to a generic fabric interconnect system and method for providing a data path between and among nodes and processing elements within an interconnection fabric.

Abstract: A PCI Express system comprising: a PCI Express adapter; and a PCI Express root complex coupled to the PCI Express adapter, the PCI root complex including: a protocol stack coupled to the PCI express adapter and configured to transmit information to and receive information from the PCI express adapter; an application specific logic module; and a fencing module coupled between the application specific logic module and the protocol stack and configured to, when in operation, block all signals from the application specific logic module from reaching the protocol stack.

Abstract: Virtualization of a PCI Endpoint via the Internet and LANs. The invention is a solution that allows the use of low-complexity, low-cost PCI Express Endpoint Type 0 cores or custom logic for relatively simple virtualization applications. The invention combines two physically separate assemblies in such a way that they appear to the host system as one local multifunctional PCI Express Endpoint device.

Abstract: An intelligent network processor is disclosed that provides a PCI express (PCIe) host bus adapter with firmware selectable hardware capabilities and firmware enabled emulation of capabilities not supported by hardware. Support for Fibre Channel (FC) and Gigabit Ethernet (GbE) protocols are provided through the same fabric ports, including multiple port trunking for both protocols. On chip protocol conversion is provided for switching and routing between FC and GbE ports. Switching using the same crossbar module is provided for both FC and GbE protocols. The crossbar module is coupled to directly access external DDR memory so that messages from FC, GbE, and PCIe interfaces may be switched directly to the DDR memory.

Abstract: A network includes a management module with a first root complex, a first server with a first endpoint coupled to the first root complex, and a second server with a second root complex, a second endpoint coupled to the second root complex, a third endpoint coupled to the first root complex, and a bridge coupled to the second endpoint and to the third endpoint. A method includes discovering a PCIe host bridge adapter (PHBA) and a storage resource coupled to multiple storage extents in a PCIe domain, creating a first virtual function on the storage resource and sending a first identifier for the first virtual function to the PHBA. A network interface device includes a PCIe endpoint that is coupleable to a PCIe root complex, another PCIe endpoint that is coupleable to another PCIe root complex, and a bridge that couples the first PCIe endpoint with the second PCIe endpoint.

Abstract: A redundant storage virtualization computer system is provided. The redundant storage virtualization computer system comprises a host entity for issuing an IO request, a redundant storage virtualization controller set coupled to the host entity for performing an IO operation in response to the IO request issued by the host entity, and a plurality of physical storage devices for providing storage space to the computer system. Each of the physical storage devices is coupled to the redundant storage virtualization controller set. The redundant storage virtualization controller set comprises a first and a second storage virtualization controller both coupled to the host entity, the storage virtualization controllers communicate therebetween via a PCI-Express interconnect.

Abstract: An image sensing device includes an image sensing unit, an interface unit, a control endpoint, an isochronous endpoint, a bulk endpoint, an interrupt endpoint, and an interface unit controller. The image sensing unit senses a moving image and a still image. The interface unit is connected to an external device. The control endpoint receives from the external device a command requesting transfer of the still image. The isochronous endpoint transfers the moving image sensed by the image sensing unit to the external device. The bulk endpoint transfers the still image sensed by the image sensing unit to the external device. The interrupt endpoint transfers error information. The error information includes information indicating that an error has occurred during sensing of the still image. The interface unit controller transfers the error information to the external device through the interrupt endpoint in response to the occurrence of the error.

Abstract: A spoofing module that mimics remote computer resources to optimize system responsiveness and avoid expiration of intentional and unintentional timeouts in extended computer systems. The invention is capable of appearing to the host system and selectively responding to the host system as if it were the actual hardware. The invention includes a throttling mechanism to prevent data over-run.

Abstract: A solution for setup and optimization of a data transfer path in extended computer systems, where the I/O system is virtualized. The solution achieves advantageous results via a mechanism that automates the configuration of multiple data path components. The solution achieves initial optimization and then automates continual optimization of the data path through monitoring of changes and through dynamic adjustment of system resources and data transfer characteristics.

Abstract: Lane configuration of an interface device of an integrated circuit is described. A core is used to tile a portion of an integrated circuit with a first version of the core and a second version of the core. The core is an application specific circuit version of an interface device. The first version and the second version in combination have a sharable interface. Each of the first version and the second version has N lanes. The first version is a primary version and the second version is a secondary version responsive to a shared interface mode. The N lanes of the second version are combined with the N lanes of the first version via the sharable interface for providing 2-by-N lanes of input/output to the first version.

Abstract: Embodiments of the present invention provide a media drive that is intended for reduction in power consumption required for serial communications to/from a host, and a power saving method thereof. In one embodiment, a HDD includes: a cache; a host interface for transferring, to a host, transfer data read out from the cache; a host interface manager that controls the execution of commands so as to generate a transfer unnecessary period during which a command and transfer data need not be exchanged with the host; and a MPU that brings a serial communication part of the host interface into a power save mode during the transfer unnecessary period. The host interface manager determines the optimum data transfer timing of transferring data from the cache to the host on the basis of a transfer rate at which data is transferred to the host, and a read rate at which data is read out from a disk into the cache.