Abstract: A CPCIe switchboard 22 is applied to a slot of a CPCIe backboard 25 of a 3 U size compliant with the CPCIe standard, and cooperative with a CPCIe CPU board 21 and I/O boards 23 applied to other slots, for mutual transmission and reception of PCIe bus signals, and a CPCI bridgeboard 11 is applied to a slot of a CPCI backboard 25 of a 6 U size compliant with the CPCI standard and cooperative with I/O boards 12 applied to other slots for mutual transmission and reception of PCI bus signals, and interconnected with the CPCIe switchboard 22 by a PCIe external cable 5 connected to a PCIe external connector 11n at a front panel 11m and cooperative with the CPCIe switchboard 22 for mutual transmission and reception of PCIe bus signals.

Abstract: A UART interface communication circuit includes a plurality of communication devices, and each includes a UART interface, a selecting apparatus, a CPU, and a multiplexer (MUX). The communication devices connect with each other via the UART interfaces thereof. The selecting apparatus is connected to the CPU for defining one of the communication devices as a master communication device and the rest as slave communication devices. The MUX is connected between the UART interface and the CPU. When the master communication device transmits data carrying an ID to the slave communication devices, a slave communication device corresponding to the ID receives and processes the data, and transmits return data to the master communication device, and then the MUX receives the return data from the slave communication device and passes it to the CPU of the master communication device for processing.

Abstract: A method for determining when all data has been sent for a given PCI Express bus command issued by a backend entity of a PCI Express bus device, by setting a PCI Express bus packet header tag field of a PCI Express bus packet to indicate a backend entity that originated the PCI Express bus command and whether the PCI Express bus packet is a last packet of the PCI Express bus command, and then inspecting the PCI Express bus packet header tag field of the PCI Express bus packet to determine whether the PCI Express bus packet is the last packet of the PCI Express bus command.

Abstract: A processor including an integrated system interface unit configured to manage multiple I/O interfaces and multiple protocols. A processor includes a plurality of processing cores, a cache comprising a plurality of banks, and a system interface unit coupled to the processing cores and the cache. The system interface unit includes an inbound unit configured to receive inbound transactions from a first I/O unit and a second I/O unit, and an outbound unit configured to convey outbound transactions to either the first I/O unit or the second I/O unit. Each of the first and second I/O units is configured to support different protocols. Prior to conveying transaction data to the system interface, the first I/O unit and second I/O units reformat transaction data to conform to a common format. The system interface receives and stores transaction data in either queues dedicated for cacheable transactions or queues dedicated for non-cacheable transactions.

Abstract: Systems and methods for providing memory modules with multiple hub devices. Exemplary systems include a cascade-interconnect memory system with a memory bus, a memory controller and a memory module. The memory controller is in communication with the memory bus for generating, receiving and responding to memory access requests. The memory module includes a first hub device with three or more ports and a second hub device with three or more ports. A first port on the first hub device is in communication with the memory controller via the memory bus, a second port on the first hub device is in communication with a first set of memory devices, and a third port on the first hub device is cascade connected to a first port on the second hub device. A second port on the second hub device is in communication with a second set of memory devices and a third port on the second hub device supports a cascaded connection to a subsequent hub device in the memory system.

Abstract: A bus station in the form of a hardware dongle, operates in conjunction with a USB Device running suitable software. When the bus station determines that a bus host is connected to a first bus communication port thereof, it acts as a transceiver to allow conventional bus communications between said bus host and a bus device connected to a second bus communication port thereof. When the bus station determines that a bus device running suitable software is connected to the first bus communication port thereof, it acts as an alternate host to allow bus communications between said bus device connected to the first bus communication port and a bus device connected to a second bus communication port.

Abstract: Aspects of the disclosure embody a multi-master two-wire serial bus that comprises two or more chained two-wire serial busses. The chained two-wire serial busses include a host two-wire serial bus with a first master device and one or more slave devices. One or more chained two-wire serial busses are coupled to the host bus wherein one or more slave devices on the host two-wire serial bus operate as second master devices, which comprise a digital state machine including a two-wire serial slave component coupled to the master device and a two-wire serial master component coupled to the slave devices on the chained two-wire serial bus. The digital state machine emulates a slave device on the host two-wire serial bus and a master device on the chained two-wire serial bus.

Abstract: In a state negotiation method of a PCI-E upstream device supporting multiple downstream configurations, a state of a second link asserted by a second state machine of the PCI-E upstream device is detected when a first link asserted by a first state machine of the PCI-E upstream device is ready to change from a first state to a second state in a specified duration. A negotiating procedure is performed to have the first link and the second link enter the second state simultaneously if the second link is detected to be in the first state within the specified duration.

Abstract: A multi-interface conversion device includes a USB-to-IDE interface bridging unit, an IDE-to-SATA interface bridging unit, an IDE switching unit, and a switching logic unit. The USB-to-IDE interface bridging unit provides USB to IDE bridging and conversion. The IDE-to-SATA interface bridging unit provides IDE to SATA interface conversion or IDE to eSATA interface conversion or SATA to eSATA interface conversion. The IDE-to-SATA interface bridging unit is connected to the USB-to-IDE interface bridging unit to transmit USB-to-IDE converted data to the IDE-to-SATA interface bridging unit to provide conversion between USB interface and SATA. The IDE switching unit is connected to the USB-to-IDE interface bridging unit and the IDE-to-SATA interface bridging unit for switching the output IDE interface and signal between the USB-to-IDE interface bridging unit and the IDE-to-SATA interface bridging unit.

Abstract: A TOE apparatus and a method for transferring a packet applying the TOE have developed. the device comprises that an embedded processor for receiving information on an address and size of physical memory and generating a prototype header according to contents of the received information; and Gigabit Ethernet for generating header information of a packet using the prototype header, receiving data according to the address and size of the physical memory included in the information received from a host device through a main PCI bus, a PCI-to-PCI bridge, and a sub PCI bus, and adding the header information to the data, so as to transmit the data to a network.

Abstract: Provided are a guaranteed isochronous services method and apparatus in bridged LAN. Isochronous streams are transmitted through bridges to a plurality of listener stations in a distributed network, and each bridge performs filtering, stream group registration and authentication for the isochronous streams. Accordingly, quality of service (QoS) in a distributed network can be improved. Furthermore, isochronous streams to the plurality of listener stations can be guaranteed.

Abstract: Apparatus, systems and methods for clustering multiple PCI Express hierarchies to enable access of components in different hierarchies. Each PCI Express hierarchy includes a root device as well as a cluster port for coupling each hierarchy to each other hierarchy of a physical cluster through a PCI Express switched fabric. Memory addresses and transaction IDs are re-mapped by the cluster port of each hierarchy to partition the PCI Express space of the system of multiple hierarchies. A first portion of the partitioned space is reserved for access to local components within a hierarchy. A second portion of the space is used to access remote components of other hierarchies from within a different first hierarchy. The address and transaction ID values exchanged in such remote transactions are re-mapped and used by the cluster port of each hierarchy to route exchanges between hierarchies using standard PCIe root devices, endpoint devices, and switches.

Abstract: An apparatus for executing user commands in digital equipment operating in a USB mass storage (UMS) mode is configured in such a manner that a USB connecting unit transmits and receives commands and data to and from a PC serving as a host through a universal serial bus (USB) port. A USB control unit controls the USB connecting unit. A storage unit stores an access command table including access commands allocated respectively to address shift values, by which addresses contained in one or more user commands received from the PC deviate from a valid address range. A microcomputer determines whether the command received through the USB connecting unit is a user command. If it is determined that the received command is a user command, the microcomputer controls executing the access commands allocated respectively to the address shift values based on the access command table.

Abstract: In one embodiment, an input/output (I/O) node comprises an I/O memory management unit (IOMMU) configured to translate memory requests. The I/O node is configured to couple to an interconnect and to operate as a tunnel on the interconnect, and wherein the IOMMU is configured translate memory requests passing through the tunnel in the upstream direction. In another embodiment, a system comprises another I/O node configured to bridge another interconnect to the interconnect, wherein the I/O node is the tunnel for the other I/O node.

Abstract: A synchronous controller is formed with a cycle master module and one or more control modules doubly connected through a synchronous bus and an event bus. The event bus is used for transmitting data with a larger volume. The control modules each cyclically carry out execution of a user program for controlling an object apparatus to be controlled. The cycle master module exchanges data with the control modules through the event bus and the synchronous bus. Each of the control modules carries out one cycle of the execution of the user program by using reception of synchronous data transmitted from the cycle master module through the synchronous bus as a trigger.

Abstract: Apparatus and associated methods for a simplified Serial SCSI Protocol (“SSP”) link layer within a SAS device. Features and aspects hereof provide a simplified SSP link layer processor to enable cost reduction and simplification of Serial Attached SCSI (“SAS”) devices requiring only limited SSP exchange functionality. In one embodiment, a SAS expander may incorporate the simplified SSP link layer features and aspects hereof to permit simple management of SAS devices coupled to the expander or coupled downstream through other expanders. The simplified SSP link layer suffices for simple SAS management functions while reducing cost and complexity of the SAS expander. Features and aspects hereof may be implemented with minimal customized circuits for SSP link layer management in the SAS device. In one aspect hereof, the simplified link layer processing may be implemented as a simplified state machine model in combinatorial logic coupled with any requisite memory components.

Abstract: Computing systems including first and second processors configured to control first and second buses, respectively, and a terminator-monitor-bridge (TMB) device coupled between the first and second buses are provided. The TMB device is configured to selectively enable the first processor and the second processor to control at least a portion of the second bus and the first bus, respectively. TMB devices and methods for operating the TMB devices in accordance with the above configuration are also provided.

Abstract: A PC card control apparatus includes a PC card connector, a card detector and an interconnection switching circuit. The PC card connector is configured to provide connections for connecting one of a first PC card compliant with specific card standards and a card-adapting card for connecting a second PC card compliant with a different card standard to the PC card control apparatus. The card detector is configured to detect connection of the card-adapting card to the PC card control apparatus and to subsequently output a detection signal. The interconnection switching circuit is configured to switch the connections of the PC card connector to connect the PC card connector to a bus interface dedicated to the second card upon receiving the detection signal from the card detector.

Abstract: In some embodiments, the invention involves a system and method relating to managing power utilization in partitioned systems. In at least one embodiment, the present invention is intended to control the sleeping/wakefulness of devices, as necessary, to minimize power utilization of devices whose accesses are routed away. Inter-partition communication is used to utilize devices in a sequestered partition while devices in the OS partition are put into a sleep state to save power. Other embodiments are described and claimed.

Abstract: A method for configuring a computer system. The method includes allocating a first plurality of default resources to a plurality of devices of the computer system. Then a PCIe-CardBus controller in the computer system is reconfigured with a plurality of allocable resources that are available to the PCIe-CardBus controller. The method further comprises enumerating the plurality of devices of the computer system by an Operating System (OS) of the computer system for detecting a plurality of un-configured devices in the computer system. According to the enumeration, the OS allocates a second plurality of default resources to the plurality of un-configured devices.

Abstract: A system and method that allows a plurality of SR-PCIMs to operate within a PCIe fabric. The system and method describe a master SR-PCIM election process and transfer of mastership from a master SR-PCIM to a standby SR-PCIM under certain conditions. The system and method leverage the PCI configuration space and PCI messages so that SR-PCIMs from multiple vendors can potentially interoperate.

Abstract: A bus connection device, in the form of a hardware dongle, can be connected to a first electronic device, in the form of a USB peripheral device, and a second electronic device can be connected thereto. The dongle can determine whether the second connected device is a USB host device or a USB peripheral device and, if the second electronic device is a USB host device, it is connected directly to the first electronic device. If the second electronic device is a USB peripheral device, the bus connection device operates to allow the first electronic device to operate as a host device. When the bus connection device is operating to allow the first electronic device to act as a USB host device, it regularly sends tokens to the first electronic device and to the second electronic device, to which the first electronic device can respond by transmitting data intended for the second electronic device, and to which the second electronic device can respond by transmitting data intended for the first electronic device.

Abstract: A system may comprise M data lanes where M is an integer greater than 1, a plurality of PCIe devices, and a PCIe lane controller. Each device may be coupled to corresponding ones of a plurality of PCIe endpoints. The PCIe lane controller may automatically distribute N data lanes to a first of the plurality of PCIe endpoints, and may distribute M minus N data lanes to a remaining plurality of endpoints, where N is an integer.

Abstract: The present invention provides methods and modules allowing for mapping of interface signals at for instance multi-line buses. A mapping of internal signal order schemes to external signal order schemes is enabled such that upon configuration any interface signals may carried on any lines of a multi-line bus. The configurability may obtained by the implementation of mapping logics and mapping algorithms, which associates external interface terminal to signal association to internal interface terminal to signal association in a configurable manner.

Abstract: The present invention discloses a method for accessing a target disk and a system for expanding disk capacity. A processing unit of a master disk array sends a command or data to a PCIe switching unit of the master disk array upon receipt of the command or data; the PCIe of the master disk array sends the received command or data to a control unit in a corresponding disk array according to an address of a target disk indicated in the command or data; the control unit in the corresponding disk array sends the received command or data to the target disk that is directly connected to the control unit. The present invention also discloses a master disk array and a slave disk array.

Abstract: A system on a chip for network devices. In one implementation, the system on a chip may include (integrated onto a single integrated circuit), a processor and one or more I/O devices for networking applications. For example, the I/O devices may include one or more network interface circuits for coupling to a network interface. In one embodiment, coherency may be enforced within the boundaries of the system on a chip but not enforced outside of the boundaries.

Abstract: A data storage domain is provided to determine a set of signal conditioning parameters for data being transmitted over smart cables in a data storage domain between an SAS switch and SAS expanders and among SAS expanders. A first expander interrogates any attached smart cables for cable persistent data and captures in a table the cable persistent data. One or more interfaces of the first expander are operated at a first data rate. The switch collects the captured cable persistent data and, in response, determines a set of signal conditioning parameters for data being transmitted on each attached smart cable. The set of signal conditioning parameters includes a first maximum data rate for each attached smart cable. The signal conditioning parameters are then set for each attached smart cable in accordance with the set of determined signal conditioning parameters, whereby the data storage domain is tuned for optimum signal transmission.

Abstract: A switched fabric mezzanine storage module (560) includes a storage module (562) and a switched fabric connector (563) coupled to the storage module. The storage module is coupled to directly communicate with a switched fabric (506), where the switched fabric storage mezzanine module is coupled to a payload module (502) having one of a 3U form factor, a 6U form factor and a 9U form factor. The payload module can include at least one multi-gigabit connector (518) coupled to a rear edge (519) of the payload module, where the at least one multi-gigabit connector is coupled to communicatively interface with a backplane (504).

Abstract: An apparatus, system, and method are disclosed for adapter card failover. A switch module connects a first processor complex to an adapter card through a first port as an owner processor complex. The owner processor complex manages the adapter card except for a second port and receives error messages from the adapter card. The switch module further connects a second processor complex to the adapter card through the second port as a non-owner processor complex. The non-owner processor complex manages the second port. A detection module detects a failure of the first processor complex. A setup module modifies the switch module to logically connect the second processor complex to the adapter card as the owner processor complex and to logically disconnect the first processor complex from the adapter card in response to detecting the failure.

Abstract: A multi-service platform system, includes a backplane (104), a switched fabric (106) on the backplane, and at least one of a VMEbus network and a PCI network coincident with the switched fabric on the backplane. A payload module (102) has one of a 3U form factor, a 6U form factor and a 9U form factor, where the payload module is communicatively coupled with the backplane using the switched fabric and at least one of the VMEbus network and the PCI network. At least one multi-gigabit connector (118) is coupled to a rear edge (119) of the payload module, where the at least one multi-gigabit connector is coupled to communicatively interface the payload module to the backplane, and where the switched fabric and at least one of the VMEbus network and the PCI network are communicatively coupled with the payload module through the at least one multi-gigabit connector.

Abstract: Apparatus, systems and methods for clustering multiple PCI Express hierarchies to enable access of components in different hierarchies. Each PCI Express hierarchy includes a root device as well as a cluster port for coupling each hierarchy to each other hierarchy of a physical cluster through a PCI Express switched fabric. Memory addresses and transaction IDs are re-mapped by the cluster port of each hierarchy to partition the PCI Express space of the system of multiple hierarchies. A first portion of the partitioned space is reserved for access to local components within a hierarchy. A second portion of the space is used to access remote components of other hierarchies from within a different first hierarchy. The address and transaction ID values exchanged in such remote transactions are re-mapped and used by the cluster port of each hierarchy to route exchanges between hierarchies using standard PCIe root devices, endpoint devices, and switches.

Abstract: Systems are provided for the offloading of protocol control and conversion information within microprocessor-based systems. A converter controller comprises a first interface and protocol, as well as a second interface and protocol. An intermediate protocol and interface is interconnected to both the first protocol and the second protocol, and forwards or offloads protocol information to the system CPU, which comprises device driver information for protocol conversion and/or control. The CPU acts upon the received protocol information, performs protocol conversion as necessary, and forwards the converted protocol information back to the converter controller through the intermediate interface. Some embodiments of the offloading protocol conversion system comprise a SDIO controller within a USB-based device.

Abstract: A device may include a link configured to transmit signals. The signals may provide at least one network topology, such as a bus. A tapping structure may be connected to the device using, for example, at least one of a snap fit, a friction fit or an interference fit. The tapping structure may be configured to tap in-band signals, out-of-band signals, or both in-band signals and out-of-band signals.

Abstract: According to an embodiment of the invention, a method and apparatus for support of a non-standard device containing operating system data are described. According to one embodiment, a circuit comprises a first device that is not compliant with a PCI (peripheral component interconnect) standard, the first device containing operating system data, where the operating system data is not bootable for any non-standard device; a second device that is compliant with the PCI standard, the second device being associated with the operating system data, the association of the second device with the operating system data from the first device enabling the operating system data from the first device to be booted according to the PCI standard; and a memory to receive the operating system data from the first device.

Abstract: The present invention concerns a method and a system for data transmission and control based on Universal Serial Bus (USB). The system comprises a USB Master device and a USB Slave device. The USB Master device comprises a USB Master processor and a Data Storage connected to the USB Master processor. The Slave device comprises a USB Slave processor and a Data Consumer connected to the USB Slave processor. The USB Master processor is coupled with the USB Slave processor via a USB cable. The USB Master processor accepts requests from the USB Slave processor and reads data in the Data Storage connected to it, and then the data is sent to the USB Slave processor via the USB cable, and the USB Slave processor processes the data and transfers them to the Data Consumer for use.

Abstract: A configuration memory space is scanned to locate an identification register whose value matches a predetermined value. The identification register identifies the location of a structure within the configuration space. The location of the beginning of the structure is used along with a predetermined (known) offset to determine the address of a desired configuration register.

Abstract: Exemplary embodiments describe a system and a method for performing the functions of a PCI Express feature card remotely from a data processing system. The system is comprised of a circuit board connected to a PCI-E feature card. The PCI-E feature card is remotely located in comparison to the circuit board. Architecturally, the PCI-E feature card appears to the circuit board to be located at the circuit board.

Abstract: A motherboard includes a chipset, a first connector pad suitable for receiving a first type of PCI connector, a second connector pad suitable for receiving a second type of PCI connector, a plurality of first transmission lines, a plurality of second transmission lines, and a plurality of areas for mounting switches. One end of each first transmission line is connected to the chipset, another end of each first transmission line is connected to an end of a corresponding area, one end of each second transmission line is connected to another end of the corresponding area, another end of each second transmission line is connected to the second connector pad, the first connector pad is connected to the plurality of first transmission lines, and the switches are selectively mounted on the plurality of areas.

Abstract: A wireless Universal Serial Bus (USB) device enumerates one or more real or virtual hubs that support transmission of USB data over a wireless network. The number of virtual hubs presented to a USB host can be varied dynamically according to monitored characteristics of the wireless network, such as the propagation delay, Bit Error Rate, or USB configuration of the peripheral device. Another aspect of the wireless system varies a USB transmission rate according to the amount of bandwidth available on the wireless network.

Abstract: An electronic system interconnect. The interconnect comprises a first node and a second node coupled to the first node. The interconnect is initially configured to include the first and second nodes. A third node is added to the interconnect after the interconnect is initially configured, and the first node responds to the addition of the third node by initiating a new connect handshake with the third node. The first node begins by transmitting a first signal to the third node. The first node signals that the third node has been added to the interconnect if the third node responds to the first signal by transmitting a second signal. The first node causes the interconnect to be reconfigured if the third node transmits a third signal in response to receiving the first signal.

Abstract: A transaction flow control mechanism is disclosed for a bus bridge in a high speed computer system with a high speed interface for a graphics processor. A preferred embodiment provides a flow control mechanism for the bus bridge between a GPUL bus for a GPUL PowerPC microprocessor from International Business Machines Corporation (IBM) and a high speed interface. A preferred embodiment of the invention is a bus transceiver on a multi-chip module.

Abstract: A network interface is described in which a single computer bus is split over a long distance into two or more inter-communicating buses. On one bus, processing and applications are provided and on the other remote bus, peripheral and local controllers are provided. The buses communicate through a series of: bridge, FPGA, FPGA and bridge. Between the FPGAs, a communication path provides long distance communication.

Abstract: A system and method of measurement and processing of physical variables, and in particular electrical variables, comprising: a multimeter to measure multiple electrical variables, similar to any conventional multimeter; a microcomputer capable of the numerical processing of variables, storage and communication; a conventional computer that can read magnetic or optical storage media, or alternately, be connected to the Internet; an Internet website of public access to users of said multimeter; an Internet server which runs mathematical processing software to carry out graphical and numerical analysis.

Abstract: Aspects for high speed USB data routing are presented. The aspects include routing a data stream to and from USB I/O ports serially, and maintaining a frequency of the data stream during the routing. Additionally, a root port router is provided for the root port and a data port router is provided for each I/O port, wherein each data port router delays the data stream by one bit during the routing.

Abstract: Embodiments of apparatuses, systems, and methods are described for communicating information between functional blocks of a system across a communication fabric. Translation logic couples to the communication fabric. The translation logic implements a higher level protocol layered on top of an underlining protocol and the communication fabric. The translation logic converts one initiator transaction into two or more write transactions and then transmits the write transactions using the underlining protocol of the communication fabric. The translation logic converts the initiator transaction into two or more write transactions and then transmits the write transactions using the underlining protocol of the communication fabric so that the communication fabric does not block or poll for responses, and that data may be transferred in a direction opposite from the initiator transaction request.

Abstract: A circuit and method to provide pipeline bit handling across a bus bridge between two different buses. In a preferred embodiment, the pipeline bit handling circuit provides rule enforcement for a P-bit address modifier across a bus bridge between two different buses with different rules for the P-bit address modifier. In a bus domain where pipeline transactions are allowed if the P-Bit is asserted and are not allowed if the P-Bit is not asserted, embodiments herein allow a master bus device to ensure that all bus devices will see a P=0 command with a defined minimum spacing to any other P=0 command. The required separation for P=0 commands is maintained within the bus bridge. In the preferred embodiments, the separation between P=0 commands is maintained by immediately retrying P=0 commands rather than spacing snoop requests.

Abstract: An integrated device (e.g., an integrated PCI bridge device) buffers received PCI bus strobe signals and distributes strobe signals for PCI receive data relative to the PCI data lines, enabling all PCI receive data to be latched using locally-generated PCI strobe signals generated based on the same PCI bus strobe signals. In addition, data line latch modules having primary and secondary flip-flops enable the PCI receive data to be held for an entire clock cycle, optimizing conversion between a PCI clock domain and a local clock domain of the PCI bridge device. A transmission circuit also can be configured to transmit data according to either double data rate (DDR) mode or quad data rate (QDR) mode in an efficient manner.

Abstract: A bridge accessible by a host processor can expand access over a first bus to a second bus. The first bus and the second bus are each adapted to separately connect to respective ones of a plurality of bus-compatible devices. Allowable ones of the devices include memory devices and input/output devices. The bridge has a link, together with a first and a second interface. The first interface is coupled between the first bus and the link. The second interface is coupled between the second bus and the link.

Abstract: An exemplary device for USB to RS232 adapter includes a computer with a code update software stored therein, a connector, and a voltage converter coupled to the connector. The computer is configured to connect to one end of the USB to RS232 adapter. The connector is configured to connect to an opposite end of the USB to RS232 adapter for receiving a low voltage signal from the computer via the RS232 adapter. The voltage converter is for receiving the low voltage signal and converting the low voltage signal to a high voltage signal to be transmitted to the computer via the connector and the USB to RS232 adapter, so that the computer starts the code update software to update the USB to RS232 adapter.

Abstract: A method of electrically coupling a central processing unit (CPU) of a network server to a plurality of network interface modules. The method comprises providing each of the plurality of network interface modules with a respective bus adapter chip to route an I/O bus having a first format from the central processing unit to a primary side of each of the plurality of bus adaptor chips and routing another I/O bus of the first format from a secondary side of each of the plurality of bus adapter chips to respective ones of the network interface modules. The bus adapter chips also provide for arbitered access along the I/O buses and isolation of the CPU from electrical disruption when one the network interface modules is removed.