Abstract: A serial data routing device for use in routing serial data between a computer and a peripheral device. The data routing device includes a computer data converter which communicates data under the USB protocol with a computer and which converts data received from the computer into converted computer data. A peripheral data converter is also included which communicates data under the USB protocol with the peripheral device and which converts data received from the peripheral device into converted peripheral data. A data router is provided in communication with the computer data converter and the peripheral data converter and transfers converted computer data and converted peripheral data between them. It includes a data routing controller which controls the routing of the converted computer data and the converted peripheral data between the computer data converter and the peripheral data converter such that the computer and peripheral device operate as though directly connected by a USB bus.

Abstract: A local area network compliant with universal serial bus (USB) standard includes a USB switching hub and a plurality of hosts. The USB switching hub is used for packet transmission and receiving, wherein the USB switching hub is compliant with USB standard. Each of the hosts is coupled to the USB switching hub. Each of the hosts includes a network control unit and a USB host unit. By the USB switching hub for packet transmission, USB can be used as a way of communicating among the hosts. Thus, networking can be achieved without network cards, resulting in convenience in use and reduced costs.

Abstract: A system and method for providing communication between two computer bus segments. Two half-bridge circuits are connected to respective computer bus segments and frame data for a high speed transfer of the data between the half-bridge circuits. A common application is to connect multiple PCI segments that are individually limited to the number of components connected thereto. Connection through the high speed half-bridge circuits allows additional PCI components to communicate on a second computer bus segment, acting as an expansion bus.

Abstract: Disclosed are a system and method of transmitting data in a processing platform. A switch may comprise an upstream port coupled to a root device to communicate with a processing system. The switch may also comprise a plurality of downstream ports where each downstream port is adapted to be coupled to a device. Data may be transmitted between downstream ports based upon routing information for transmitting data from the upstream port to each of the downstream ports.

Abstract: A technique for controlling synchronous and asynchronous devices connected to an inter-integrated circuit bus (I2C bus) is designed such that, in a system using an inter-integrated circuit bus (I2C bus), the controlling system includes a central processing unit (CPU), a system memory and a shared memory, each of which is connected to the system bus. The shared memory saves information about a variety of devices, which are connected to the I2C bus. The controlling system further includes a microcontroller for communicating with the shared memory and for controlling the devices which are connected to the I2C bus, asynchronous master devices which are controlled by the microcontroller, and synchronous slave devices which are controlled by the microcontroller. The microcontroller, the non-synchronous master devices and the synchronous slave devices are connected to the I2C bus.

Abstract: The present invention relates to a method of in-band communication, outside the standard SCSI communication protocol, between SCSI bus repeaters and initiator devices. The present invention implements the communication mode during the message phase of the SCSI protocol and allows initiators on a SCSI bus to determine the number, location and status of SCSI repeaters accessible on the SCSI bus.

Abstract: A self-configurable, adaptable and programmable (hereinafter “CAP”) I/O bus (15) is provided in a digital computer (11) to establish compatibility between the input/output bus of computer (11) and an incompatible input/output bus of an external module (12). Computer (11) includes a field programmable gate array (FPGA) (31) for translating the bus configuration used by module (12) to that employed by computer (11). Two preselected CAP I/O Bus conductors (17, 18) pass an identification number from the module (12) to computer (11) that points to the location of the information necessary to compatibly configure FPGA (31). This information, which includes a bus logic FPGA image file and a device driver, and may include a protocol driver, may be found in one of several locations, including onboard computer (11) in memory, onboard module (12), or at an external site such as a server (28) accessible via the Internet.

Abstract: The present invention relates to an improved method and apparatus for routing data and, more particularly, to a novel backplane for use in a data routing device, the backplane being an active backplane employing a PCI-PCI bridge interface chip and a bus operating at up to 64-bit and 66 MHz frequency. The present invention is also directed to a data routing device employing such a novel passive backplane.

Abstract: The invention provides for clearing a delayed transaction buffer associated with master-to-slave transactions on a PCI bus. In a slave such as a PCI bridge chip, or in other slave VLSI devices on the PCI bus, one or more delayed transaction buffers are used to store delayed transaction data to improve bus performance when the master retries a past transaction. A counter section counts time via clock cycles following receipt of a delayed transaction within each buffer. After a preselected time period, the buffer is flushed so that other delayed transaction data can be stored within the buffer. In the preferred embodiment, a free running n-bit counter and a plurality m-bit time out counters are used to provide the “time out” feature of the invention. Each time out counter generates a flush signal which deletes delayed transaction information stored within the associated buffer after the preselected time out period.

Abstract: A method and arrangement passes data between two busses without needing conventional bridge-interface protocols. Consistent with one method embodiment of the present invention, data is passed between a first bus on a reference chip and an external bus using a two-way buffer arrangement between the external bus and the first bus. The method includes coupling a two-way buffer arrangement between the external bus and the first bus, determining which of the busses is the initiating bus, and in response to this determination, controlling the two-way buffer arrangement to asynchronously copy data through the two-way buffer arrangement from the initiating bus to the other bus, wherein data is passed automatically in response to its presence at the buffer arrangement without any clock cycle delays. An example application is directed to interfacing with a bus used for a rapid silicon processing chip.

Abstract: The invention provides a method of performing data transfers on a PCI bus between a PCI bus master and a selected device. Wherein, there is a request signal and a grant signal on the PCI bus for a read/write transaction, and during the read/write transaction, the request signal and the grant signal are idle. The method comprises the steps of: (a) driving a first ready signal by the PCI bus master; (b) driving a second read signal by the selected device in response to the first ready signal, which initiates the read/write transaction; (c) using the request signal and the grant signal as a data transfer strobe signal during the write and read transaction, respectively, the data transfer strobe signal has a plurality of clocks; and (d) performing the data transfers on rising and falling edges of the clocks of the data transfer strobe signal.

Abstract: Apparatus by which a maximum number (e.g. 16) of external high speed computer data storage devices (e.g. computer hard drives) that are housed within portable carriers can be efficiently connected to and concurrently operated from the same low voltage differential (LVD) SCSI bus of a host computer by eliminating the adverse effects (e.g. parasitic capacitance, impedance mismatch and signal distortion) that occur as a consequence of the stub length that is required to couple a data storage device to its SCSI bus. A U-shaped receiving frame is affixed to and enclosed by a chassis, and the portable carrier in which the data storage device is housed is slidably received in and removable from the receiving frame. An isolator board carrying a repeater chip is coupled to the backplane of the receiving frame so that the repeater chip is electrically connected between the SCSI bus and the data storage device within the portable carrier.

Abstract: A computer system includes a host processor, a first PCI bus, a second PCI bus and a PCI-to-PCI bridge. The first PCI bus is coupled with the host processor. The PCI-to-PCI bridge interconnects the first and second PCI buses. The PCI-to-PCI bridge includes a first portion and a second portion. The first portion includes a first configuration register and the second portion includes a second configuration register. A method is also taught.

Abstract: A high speed connection apparatus, method, and system is provided for peripheral components on digital computer systems. The peripheral component interconnect (PCI) specification is used as a baseline for an extended set of commands and attributes. The extended command and the attribute are issued on the bus during the clock cycle immediately after the clock cycle when the initial command was issued. The extended commands and attributes utilize the standard pin connections of conventional PCI devices and buses making the present invention backward-compatible with existing (conventional) PCI devices and legacy computer systems. Alternate embodiments of the present invention utilize a side-band address port (SBA port) to enable multiple targets to receive the same set of data. The conventional PCI command encoding is modified and the extended command is used to qualify the type of transaction and the attributes being used by the initiator of the transaction.

Abstract: A technique is disclosed for facilitating data processing in a computer system. The technique utilizes logic to implement a dual mode design for PCI/PCI-X computer systems that enables optimal efficiency in regardless of which mode the system is operating in. The technique involves the implementation of two sets of transmitting and receiving elements, one tuned to PCI protocol timing and the other to PCI-X protocol. Therefore, allowing the system to process both PCI and PCI-X transactions without adversely affecting the other functional mode. The technique also enables an operator to adjust the clock timing separately for each protocol without having a detrimental affect on the other operating protocol.

Abstract: A device that enables a card to be hot-plugged into a socket on a processor-base machine includes a signal bus arbitrator, a signal bus switch, a power bus switch, a cover plate switch, status signals and a controller. The controller monitors the status signals and other signals from the cover plate switch and the signal bus arbitrator to generate control signals that activate the power bus switch and the signal bus switch to control power and signal transmitting facilities at the socket.

Abstract: An improved and more efficient mapping scheme between a fiber channel (FC) interface and small computer system interface (SCSI) for multiple initiator support. In accordance with the method of the present invention an alternate mapping path is provided for processing commands from a FC host to a SCSI target while a single command is being processed therebetween through the normal mapping path. The alternate mapping path may be provided by designating another command pin(s) on the SCSI chip in the gateway or bridge box as an additional mapping address(es) or may be provided by using and coupling additional port(s) on each of the targets having multiple ports wherein the additional port(s) is/are associated with an additional mapping address(es).

Abstract: A Wide Area Serial PCI system for connecting peripheral devices to a computer. The WASP system includes a host computer system connected through a serial bus to a remote device. The serial bus can range from several meters to several kilometers or more. The host computer system includes a CPU and memory, and also includes a first Peripheral Component Interconnect (PCI) bus, also referred to as the local PCI bus. A primary bridge according to the present invention is coupled to the first PCI bus. The primary bridge includes PCI interface circuitry for interfacing to the first PCI bus. The remote device is located remotely from the computer system and comprises a second or remote PCI bus and one or more peripheral devices coupled to the second PCI bus. The remote device also includes a secondary bridge coupled to the second PCI bus. The secondary bridge includes PCI interface circuitry for interfacing to the second PCI bus. The serial bus is coupled between the primary bridge and the secondary bridge.

Abstract: An integrated device includes an external memory interface that includes address decoding logic configured for identifying a destination device register based on register address information retrieved from an external memory. The external memory interface, upon identifying the destination device register, loads the destination device register with register data read from the external memory, for example contiguously following the corresponding register address information. Hence, the integrated device can be programmed on a per register basis, without the necessity of an EEPROM map.

Abstract: The invention relates to A method for releasing the setting of isochronous transaction in a bus network, such as an IEEE-1394 bus network, in which plural buses are connected via a bridge, a bus network utilizing the method and a medium of an information provider, wherein an owner (a resource-possessing node), a talker (a sending node) and a listener (a receiving node) are connected to any of plural buses constituting an IEEE-1394 bus network. In a first step, a command to set synchronous communication is propagated from the owner to a portal of a bridge. A release from the setting of isochronous transaction is executed from the owner to a portal of a bridge. In a second step, a command to set communication between portals of bridges on the same bus is propagated. A release from the setting between portals of bridges on the same bus is executed. In a third step, a command to set communication is propagated between portals of the same bridge.

Abstract: A method of setting synchronous communication in a bus network, such as an IEEE-1394 bus network, in which plural buses are connected via abridge, a bus network utilizing the method and a medium of an information provider. An owner (a resource-possessing node), a talker (a sending node) and a listener (a receiving node) are connected to any of plural buses constituting an IEEE-1394 bus network. In a first step, a command to set synchronous communication is propagated from the owner to a portal of a bridge. In a second step, a command to set communication between portals of bridges on the same bus is propagated. In a third step, a command to set communication is propagated between portals of the same bridge. After the first step is executed, the second and third steps are suitably repeated. Therefore, a command for setting synchronous communication is sequentially propagated and synchronous communication is set for the bus and the bridge on a path from the talker to the listener.