Abstract: The present invention is a data transfer protocol control system with a host bus interface that includes a transmitting/receiving command DMA, a transmitting data DMA and a receiving data DMA for controlling data transfer protocol with a host bus interface considering characteristic, usage frequency, simultaneous processing functions of the command DMA and the data DMAs. A host interface bus is efficiently used and bus usage ratio is distributed properly to support transfer flow properly and improve the entire system performance.

Abstract: A system and method to facilitate communication between an associated bus, such as employs a standard bus protocol, and a connector to which a removable SFF device can be attached. A desired operating mode is selected based on the device attached at the connector, such as either to pass the protocol between the bus and device generally unchanged or to implement suitable protocol conversion for such communication. Thus, by configuring the SFF device to appear as device currently supported by the bus, the SFF device can operate at the connector with native operating system support.

Abstract: A system and method for observing transactions on a packet bus is disclosed. In one embodiment, a computer system includes a plurality of input/output (I/O) nodes serially coupled to a processor. Each of the I/O nodes may be configured to operate in a first (normal) mode, and a second (analysis) mode. During the normal mode, packets may be selectively conveyed through an I/O tunnel in the I/O node, and particular packets may be selectively conveyed to a peripheral bus interface in the I/O node. In the analysis mode, electrical signals corresponding to packets conveyed through the I/O tunnel may be replicated on a peripheral bus coupled to the peripheral bus interface. No conversion from the packet bus protocol to the peripheral bus protocol. A signal analyzer may be coupled to the peripheral bus, thereby allowing observation of the electrical signals.

Abstract: An interface adapter is provided that allows a host device that communicates through a first interface protocol, such as a Fiber Channel compliant interface or a SCSI compliant interface, to connect to a plurality of storage devices that communicate through a second interface protocol, such as an IDE/ATA compliant interface. The interface adapter is configured to convert transmissions received from the host device to the second interface protocol and to convey the converted transmissions to the plurality of storage devices. The interface adapter is also configured to convert transmissions received according to the second interface protocol from the plurality of storage devices to the first interface protocol and to convey the converted transmissions to the host device. In this manner, the host device and the storage devices can accomplish input/output (I/O) transactions despite the fact that they implement different interface protocols.

Abstract: One or more bus bridges are used to partition a large I2C bus into smaller bus segments. By programming address bitmaps that are internal to each bridge, the various bus segments can be made to appear as one logical bus. In addition, the bus topology can be designed to maximize the ability to isolate faults within a given segment, thereby improving the ability of technicians to diagnose problems in very large I2C implementations. In one embodiment, the invention is a unidirectional bus bridge which is designed so that two such bridges can be used in parallel (facing in opposite directions) to implement a fully bi-directional bus bridge. In another embodiment, I2C slave addresses are replicated in a single logical I2C bus by addressing a tunnel command to a bridge, which command contains an address and causes the bridge to which it is addressed to forward the contained address.

Abstract: A method and device for the exchange of data in messages between at least two users which are connected by a bus system and have separate time bases, the messages containing the data being transmitted by the users via the bus system; and a first user, in a function as timer, controls the messages as a function of time in such a way that it repeatedly transmits a reference message, which contains time information regarding the time base of the first user, via the bus at a specifiable time interval; the at least second user forms its own time information, using its time base, as a function of the time information of the first user; a correction value is ascertained from the two pieces of time information; and the second user adapts its time information and/or its time base as a function of the correction value.

Abstract: An electronic flash memory external storage method and device for data processing system, comprising firmware which directly controls the access of electronic storage media and implements standard interface functions, adopts particular reading and writing formats of the external storage media, receives power via USB, externally stores data by flash memory and access control circuit with cooperation of the firmware, and the driver with the operating system, and has write-protection so that the data can be safely transferred. The method according to the present invention is highly efficient and all parts involved are assembled as a monolithic piece so that it has large-capacity with small size and high speed. The device operates in static-state and is driven by the software. It is plug-and-play and adapted to micro-data processing system.

Abstract: The secondary sides of PCI bridges are connected by inverting the normal bridge sense that defines a bridge's transparency window so that memory accessible on the secondary side is implied, as opposed to being implied on the primary side.

Abstract: According to one embodiment of the present invention, an apparatus is provided which includes a first address translation unit and a second address translation unit. The first address translation unit is programmed for a minimum amount of memory addresses required to accept control transactions on a first bus. The second address translation unit is programmed to a memory address range that corresponds to an amount of local memory for caching operations between the first I/O processor and a first I/O interconnect device and an amount of memory space required by the I/O interconnect device. The apparatus includes logic to determine, upon receiving an incoming host request, whether a reply address corresponding to the host request overlaps with the memory address range programmed for the second address translation unit. The apparatus further includes logic to dynamically alter a data flow between the first I/O interconnect device and the host.

Abstract: A method, system, and apparatus for providing data to an I/O adapter from a PCI-to-PCI bus bridge is provided. In one embodiment, once the PCI-to-PCI bus bridge receives a request for data from the I/O adapter, the PCI-to-PCI bus bridge determines whether the requested data is contained within a cached memory within the PCI-to-PCI bus bridge. If the data is contained within the cached memory, then the requested data is provided to the I/O adapter from the cached memory. If the requested data is not within the cached memory, the data is fetched from system memory, then cached in the PCI-to-PCI bus bridge, and sent to the requesting I/O adapter. To ensure that the data in the cached memory within the PCI-to-PCI bridge is not stale, signals are received, periodically or aperiodically, by the PCI-to-PCI bridge from a PCI host bridge indicating whether the data contained within the buffers is stale.

Abstract: A method, which may be embodied upon a computer readable medium and executed by a processor, for detecting PCI buses in a logically partitioned system. The method may include determining PCI buses that are accessible to a guest operating system via querying a hypervisor, generating a PCI controller list, wherein a PCI controller exists for each determined PCI bus, and constructing a PCI bus structure for each PCI controller in the PCI controller list. The method may further include calling a platform dependent device detection code to detect PCI devices accessible to the logically partitioned system, and connecting to each function of each detected PCI device to authorize the guest operating system to conduct configuration IO operations thereon through a platform dependent code operation.

Abstract: The technical field of the invention generally concerns digital computers and, in particular, repeaters or switches (40) for distributed arbitration digital data buses (52, 54, 56 and 58) to which devices (62, 64, 66, 68, 72 and 74) connect in parallel. The bus repeater/switch (40) includes a plurality of bus interface cards (48) that are connected to the distributed arbitration buses (52, 54, 56 and 58) for receiving signals from and transmitting signals to devices (62, 64, 66, 68, 72 and 74) connected thereto. The bus interface cards (48) connect to a control card (44) which allows signals from one of the sharing buses (52, 54 or 56) to be exchanged with the shared bus (58). The bus switch (40) also includes selector switch (84 or 88) for choosing which particular one of the sharing buses (52, 54 or 56) exchanges digital data signals with the shared bus (58).

Abstract: When a universal serial bus (USB) device is plugged in, the USB device enumerates as a “mass storage device” (or any device capable of input) even though the device is not actually a “mass storage device.” A USB device agent would be included in a storage device on the USB device in the form of an executable file. After the device enumerates the first time as a “mass storage device,” the user selects the “mass storage device” and executes the appropriate executable file containing the agent. The agent would then install itself on the host hard file and thereafter it could function with any other compatible USB device. The agent could then command compatible devices to re-enumerate as what they actually are. The agent could also enable enhanced host/device interactions and enhanced device functionality and diagnostics.

Abstract: Even when an S-PCI bus 1b requests transfer while a P-PCI bus 1a is executing burst transfer, assert of a TRDY# signal for data transfer of the P-PCI side is delayed so that next data transfer of the P-PCI side is completed within 8 clock cycles since the TRDY# signal for data transfer of the P-PCI side is asserted.

Abstract: A parallel SCSI host adapter includes a SCSI bus port and a host I/O bus port. The parallel SCSI host adapter takes a snapshot of state data for a first data channel coupling the SCSI bus port to the host I/O bus port following receipt of a complete Packetized SCSI protocol information unit having a context from the SCSI bus port. Following the snapshot, another Packetized SCSI protocol information unit for the same context is transferred over the first data channel. Since the snapshot requires substantially no time delay relative to a time delay associated with saving the state data in a hardware I/O command block for the context, latency between the information units for the same context is minimized in the parallel SCSI host adapter.

Abstract: A remote memory processor architecture which provides an embedded processor with access to a large off-chip memory space via a HOST processor bus. An on-chip embedded memory provides a cache memory space.

Abstract: A method of and apparatus for communicating data using a hub. The method includes the step of buffering a single transfer request received at a hub during a transaction between the hub and a host controller, where the single transfer request is to be performed between the hub and an agent to generate a result. The method then includes the step of determining whether a transfer inquiry received at the hub from the host controller corresponds to the result.

Abstract: A system on a chip for network devices. In one implementation, the system on a chip may include (integrated onto a single integrated circuit), a processor and one or more I/O devices for networking applications. For example, the I/O devices may include one or more network interface circuits for coupling to a network interface. In one embodiment, coherency may be enforced within the boundaries of the system on a chip but not enforced outside of the boundaries.

Abstract: A method of (and system for) of transporting a sideband signal through a physical layer of an extended bridge, includes on a first node of the extended bridge, providing an interface to a sideband component coupled to a side of the extended bridge, encoding a first data stream being output from the sideband component with a unique header to identify the data output from the sideband component, and multiplexing the first data stream from the sideband component with a second data stream from a principal signal port, and outputting the multiplexed first and second data streams to another node of the extended bridge.

Abstract: A programmable logic controller with enhanced and extended the capabilities. A digital input filter implement filters with considerable less logic by simulating the action of a capacitor being driven by a constant current source whose output voltage is sensed by a comparator with a large amount of hysterisis. A pulse catch circuit captures the input pulse even though the update occurs between scan cycles. A pulse output controller includes a hardware pipeline mechanism to allow for smooth, hardware-controlled transitions from wave-form to wave-form. A free port link allows the user to control the port either manually or by operation of a user program. In order to provide higher performance for communication using PPI protocol, the PLC includes a built-in protocol. An n-bit modem protocol ensures data integrity without use of a parity type data integrity system.

Abstract: A USB host controller for embedded systems employing batched data transfer. The system batches up to 16 individual transactions in a single batch to reduce the number and frequency of interrupts to the microprocessor and to increase USB data throughput.

Abstract: A method of electrically coupling a central processing unit (CPU) of a network server to a plurality of network interface modules. The method comprises providing each of the plurality of network interface modules with a respective bus adapter chip to route an I/O bus having a first format from the central processing unit to a primary side of each of the plurality of bus adapter chips and routing another I/O bus of the first format from a secondary side of each of the plurality of bus adapter chips to respective ones of the network interface modules. The bus adapter chips also provide for arbitered access along the I/O buses and isolation of the CPU from electrical disruption when one of the network interface modules is removed.

Abstract: A cable, adapter, or converter device is disclosed that enables a peripheral device (e.g., external display) normally connected only through a non-USB port to communicate with a host computer via a USB port in addition to its non-USB port. DDC-formatted signals from the peripheral device are converted to the appropriate format for input through the USB port, and signals transmitted to the peripheral device from the USB port are converted to the format recognizable by the external peripheral, allowing access to peripheral features via the host system.

Abstract: A mechanism for optimizing transaction retries within a system utilizing a peripheral component interconnect (PCI) bus architecture. Specifically, one embodiment of the present invention includes a system which optimizes transaction retries issued by a PCI bus master device to a target device coupled to a PCI bus. The system includes a target device communicatively coupled to a PCI bus and able to issue a retry signal over the PCI bus. Furthermore, the system includes a PCI bus master device communicatively coupled to the PCI bus and able to issue a transaction signal to the target device over the PCI bus. Moreover, the system includes a retry timer circuit coupled to the PCI bus master device in order to respond when the PCI bus master device receives the retry signal issued by the target device over the PCI bus. The retry timer circuit causes the PCI bus master device to wait a fixed period of time before reissuing the transaction signal to the target device over the PCI bus.

Abstract: A bus switch module for use in a bus such as an I2C bus is provided. In one embodiment, the switch module includes a control unit and a switch. The control unit includes an input for receiving instructions from a bus driver as to whether to close or open the switch. The switch includes a first and a second data connection which connect the switch to a first and a second segment of the bus and includes a control input for receiving commands from the control unit. The control unit opens and closes the switch in response to instructions received from the bus driver and signals received in the first data connection are passed to the second data connection only when the switch is closed in response to a command from the control unit.

Abstract: A bus arbitration method within a control chipset, The control chipset further comprises a first control chip and a second control chip, data are transferred between the first and the second control chips through a bus, the bus comprises a bidirectional bus The first control chip usually control the authority to use the bus, however the second control chip has higher priority to use the bus. Accompany with a bus specification without waiting cycle, to arbitrate the authority to use the bus can be done fast and without errors. Therefore, no GNT signal line is required and the arbitration time reduces.

Abstract: A bridge accessible by a host processor can expand access over a first bus to a second bus. The first bus and the second bus are each adapted to separately connect to respective ones of a plurality of bus-compatible devices. Allowable ones of the devices include memory devices and input/output devices. The bridge has a link, together with a first and a second interface. The first interface is coupled between the first bus and the link. The second interface is coupled between the second bus and the link.

Abstract: A communication system has multiple communication buses and multiple bus controller cards each supplying at least two independent channels of communication between one or more hosts and the communication buses. One of the controller cards is designated as a primary controller card for managing the communication buses and resetting the communication buses such that if a controller card is inserted to or removed from the system then the buses are reset.

Abstract: The switch input processing module has: a control unit; a first external connection terminal to which either an analog signal of an analog signal system or a serial signal of a serial signal system is supplied; an analog signal transmission and serial signal transmission line which is disposed between the first external connection terminal and the control unit; and a second external connection terminal to which a determination signal indicating that either the analog signal system or the serial signal system is connected to the first external connection terminal is supplied. When the control unit determines that the determination signal indicates connection of the serial signal system, the control unit makes the serial signal transmission line conductive. When the control unit determines that the determination signal indicates connection of the analog signal system, the control unit makes the serial signal transmission line nonconductive.

Abstract: A hub based computer system having a central hub that communicates with a plurality of satellite devices over respective link buses. Each link bus is substantially the same and adheres to a predefined link bus protocol. The link bus protocol establishes a method in which data receiving circuitry of a target device can be put into a known state during a final stage of a source strobe event such as e.g., a data transfer. Once in the known state, the source strobes are stopped on the link bus. The target device uses internal logic clocked by a system clock rather than the source strobe to continuously sample the state of the receiving circuitry to see if the state has deviated from the known state. A change detect circuit determines if the receiving circuitry has deviated from the known state and if so, detects a new source strobe event. The change detect circuit detects the new event in the less stringent clock domain, which allows greater control of the skew and asymmetry of the source strobe.

Abstract: A user configurable, modular port expansion system allows the user of a host system such as a USB-enabled personal computer to customize a desired configuration of one or more peripheral device modules without the use of cables between modules. The peripheral device modules are physically and electrically connectable to each other side-by-side between a hub end module and a power end module in any sequence so that there can be provided, within the limits of the host port specification, virtually any number of selected, expanded functions in any combination. The peripheral device modules may include, by way of example, a standard parallel DB-25 port module, a two-port serial PS/2 module, a two-port serial DB-9 module, a four- or seven-port USB hub, an RJ-11 Ethernet LAN module, and an RJ-11 modem module.

Abstract: A multi-port Peripheral Component Interconnect (PCI) bus bridge allows for cascading of PCI buses and reduction of bus loading and traffic. The multi-port PCI bridge has three or more ports that connect to PCI buses. At each destination port, a pair of data FIFOs is provided for each source port, for read and write data. Each destination port has three address FIFOs, one for posted-memory-write (PMW) addresses, another for delayed-transaction-request (DTR) addresses and data, and a third for delayed-transaction-completion (DTC) addresses. An address mux receives addresses from all source ports and combines them into the three address FIFOs. When addresses arrive concurrently, the address mux delays one address until the first address has been written into the address FIFO, and then writes the delayed address. Since separate data FIFOs are used for each source port, data is not delayed. Concurrent transactions from different source ports to the same destination port can occur.

Abstract: An OCN with memory device address decoding that enables communication among integrated processing elements, including a network, a processing element and a bus gasket. The network transfers packets between multiple ports, where each port conforms to a consistent port interface protocol. The processing element includes a bus and a memory device programmed with the address of each port, so that a transaction on the bus indicating another port is decoded by the memory device. The bus gasket includes a bus interface that generates packets and a port interface that sends and receives the packets according to the consistent port interface protocol and that uses the decoded address as a destination port address. The memory device may be implemented in any desired manner, such as a memory management unit (MMU) or a direct memory access (DMA) device.

Abstract: A computer system having at least one central processing unit, system memory, and a core logic capable of accepting an AGP bus is provided with an AGP to AGP bridge connected to the standard AGP bus. The AGP to AGP bridge can accommodate two or more AGP-compatible devices that can be accessed through the standard AGP bus via the AGP to AGP bridge. A PCI to memory bridge is also provided within the AGP to AGP bridge so that PCI devices may be connected to the AGP to AGP bridge. The AGP to AGP bridge is fitted with an overall flow control logic that controls the transfer of data to or from the various AGP devices and the standard AGP bus that is connected to the core logic of the computer system. The AGP to AGP Bridge can utilize a standard 32-bit AGP bus as well as (two) dual 32-bit buses to enhance bandwidth. In an alternate embodiment of the invention, the dual 32-bit buses can be combined to form a single 64-bit bus to increase the available bandwidth.

Abstract: A method, system, and computer program product for enforcing logical partitioning of input/output slots within a data processing system is provided. In one embodiment, the system includes a hypervisor and at least one DMA address checking component. The hypervisor receives non-direct-memory-access requests for access to input/output slots and prohibits devices within one logical partition from accessing the input/output slots assigned to a different logical partition. The DMA address checking component receives direct-memory-access requests and prohibits requests for addresses not within the same logical partition as the requesting device from being completed. Requests with addresses corresponding to the same logical partition as the requesting device are placed on the primary PCI bus by the DMA address checking component for delivery to the system memory.

Abstract: A method, data processing system, and I/O subsystem suitable for authorizing DMA accesses requested by a 64-bit I/O adapter are disclosed. The system includes one or more processors that have access to a system memory. A host bridge is connected between the processor(s) and an I/O bus. A first I/O adapter, which generates 32-bit addresses, is coupled to the host bridge. A second I/O adapter coupled to the host bridge is enabled to generate an address with a width greater than 32-bits (such as a 64-bit address). The system may include a Translation Control Entry (TCE) table, that is configured with information needed to translate an address generated by the 32-bit adapter to a wider address (such as a 64-bit address). In addition, the TCE may determine whether DMA access to the translated address by the requesting adapter is authorized. The system further includes an Access Control Table (ACT). The ACT determines whether DMA access to the address generated by the 64-bit I/O adapter is authorized.

Abstract: A bridge has a first interface that receives a request through a first bus from a requestor that request to read data, and a second interface that forwards the request through a second bus to a device that connects to a memory. The device obtains the requested data from the memory and forwards to the bridge, which then sends the data to the requestor in an appropriate manner.

Abstract: A method, system, and apparatus for isolating an input/output (I/O) bus error, received from an I/O adapter, from the other I/O adapters that may be in different partitions within a logically partitioned data process system is provided. In one embodiment, the logically partitioned data processing system includes a system bus, a processing unit, a memory unit, a host bridge, a plurality of terminal bridges, and a plurality of input/output adapters. The processing unit, memory unit, and the host bridge are all coupled to each other through the system bus. Each of the plurality of terminal bridges is coupled to the host bridge through a first bus. Each of the input/output adapters is coupled to one of the plurality of terminal bridges through a one of a plurality of second buses, such that each input/output adapter corresponds to a single terminal bridge. Each of the input/output adapters are assigned to one of a plurality of logical partitions within the data processing system.

Abstract: The present invention relates to a repeater circuit for providing effective point-to-point coupling between terminated Small Computer System Interface (SCSI) bus segments. The repeater circuit has an enable input and can perform SCSI address translation to map SCSI addresses from a narrow SCSI bus to high SCSI addresses on a wide SCSI bus.

Abstract: The present invention provides bridge device for transferring data using master-specific prefetch sizes. The bridge device is coupled between a first bus and a second bus with the master devices being coupled to the first bus and the slave devices being coupled to the second bus. The bridge device includes a set of prefetch control registers, a prefetch buffer, and bridge control circuitry. The set of prefetch control registers is arranged to store prefetch sizes of data to be prefetched for a set of the master devices with one prefetch control register being provided for a master device. The prefetch buffer is arranged to store data for transfer. The bridge control circuitry is coupled to the prefetch control registers and the prefetch buffer for transferring data between a source device and a destination device.

Abstract: In a serial bus network, an environment is provided, in which the serial bus is divided to two local buses and a specific terminal connected to one of the local buses can reliably occupy other terminals connected to the other local bus without influence on the terminals connected to the local buses. A specific terminal is connected to a local bus 101, to which an inner portal 3 is connected, and an ID information thereof is preliminarily recorded in a ROM 8. After a power source is turned on, the specific terminal connected to the side of the inner portal 3 is detected according to the ID information from the ROM 8. An ID information of all of nodes connected to a local bus 104, to which an outer portal 4 is connected, is read out and stored in a control portion 5. A bus reset is generated on the local bus 101. In order to give a connection information of the local bus 104, a self-ID packet is generated by the control portion 5 and transmits it through a dedicated PHY 6.

Abstract: A method for updating data of a plug control register in a digital interface having a plurality of audio/video nodes. The method includes the steps of retrieving a signal that determines whether a first audio/video node is entitled to update a value of the plug control register of a second audio/video node, when the first audio/video node requests that the second audio/video node update a value of the plug control register through a read/lock transaction; transmitting the determining signal to the first audio/video node through a lock response packet; and updating the value of the plug control register of the second audio/video node with a data value transmitted from the first audio/video node, when the first audio/video node is entitled to update the value of the plug control register of the second audio/video node and when an argument value transmitted from the first audio/video node is equal to the value of the plug control register of the second audio/video node.

Abstract: Disclosed are a system and method of transmitting data in a processing platform. A switch may comprise an upstream port coupled to a root device to communicate with a processing system. The switch may also comprise a plurality of downstream ports where each downstream port is adapted to be coupled to a device. Data may be transmitted between downstream ports based upon routing information for transmitting data from the upstream port to each of the downstream ports.

Abstract: A “firewall” apparatus is placed between a single bus master device and a multimaster I2C bus system. The firewall apparatus transforms all multimaster bus errors into simple NAK errors and isolates the single bus master from the multimaster bus. Therefore the single bus master needs only to retry transactions that receive unexpected NAKs and all complex multimaster issues, such as bus collisions, transaction termination and bus recovery, associated with the actual error that occurred on the multimaster bus are handled by the firewall apparatus. In accordance with one embodiment, when the single bus master attempts to launch a transaction at a time when the multimaster I2C bus is busy, the firewall apparatus absorbs the address driven by the single bus master and then stalls the transaction until the firewall apparatus is able to successfully acquire and drive the address on the multimaster bus. The firewall apparatus is implemented in a preferred embodiment by a programmed microcontroller.

Abstract: Embodiments of the present invention relate to an apparatus including a first processor module, a second processor module, and a bus. The bus is coupled to the first processor module and the second processor module. The bus is configured to transmit both processor related communication and memory related communication. In embodiments, the first processor module includes a first central processing unit and the second processing module includes a second central processing unit. Accordingly, in embodiments of the present invention, a single bus can be used to communicate between processors and memories. The present invention is useful for real time duplication of memory, high speed duplication of memory, and/or a coherency check of memory between a first processing module and a second processing module.

Abstract: A method and system for distributing messages on a bus bridge interconnect are described. In one embodiment, the interconnect comprises a number of nodes, a bus bridge, and a number of buses. The method and system insure that the messages have been observed by each node. In one embodiment, a message is initiated at an initiating node. The message is forwarded to an adjacent neighbor node. The adjacent neighbor node processes and forwards the message to its adjacent neighbor node. The message is received at the initiating node in its original or modified form. In one embodiment, the message is removed from the interconnect once it is received by the initiating node. In an alternate embodiment, each node generates an appended message by one appending an extended unique identifier (EUI) to the message. Once the appended message is received at the initiating node, the appended message is saved.

Abstract: A microprocessor includes a first bus and a second bus capable of operating simultaneously, a single port memory divided into a plurality of banks, a bus switch circuit provided between the plurality of banks and the first and second buses, and a processor core connected to the first and second buses and the single port memory. The bus switch circuit may be controlled statically, independent of activities on the buses, or may be controlled dynamically according to the activities.

Abstract: The present invention provides a circuit system for data transmission between LPC devices, comprising: a first LPC bus, connected to a first LPC device; a second LPC bus, connected to a second LPC device; and an LPC host controller, able to drive the first LPC device through the first LPC bus and the second LPC device through the second LPC bus; wherein the LPC host controller further comprises an address register. The present invention further provides a method for data transmission between LPC devices, comprising the steps of: starting a first cycle through a first LPC bus by an LPC host controller, wherein a first LPC device sends a request to have a transaction with a second LPC device, and inserting a plurality of wait states after the request is received by the LPC host controller; and starting a second cycle through a second LPC bus by the LPC host controller, wherein the LPC host controller has a transaction with the second LPC device according to the request from the first LPC device.

Abstract: A device includes a first SCSI bus, a second SCSI bus, a first bus controller slot, a second bus controller slot and a bus controller in one of the first bus controller slot and the second bus controller slot. The bus controller includes reset circuitry for generating a SCSI bus reset signal. The SCSI bus reset signal being used to reset the first SCSI bus when the bus controller is in the first bus controller slot and the first SCSI bus is isolated from the second SCSI bus. The SCSI bus reset signal being used to reset the second SCSI bus when the bus controller is in the second bus controller slot and the first SCSI bus is isolated from the second SCSI bus. The SCSI bus reset signal is to reset both the first SCSI bus and the second SCSI bus when the first SCSI bus and the second SCSI bus are bridged and one of the following conditions is met: the bus controller is in the first bus controller slot, or the bus controller is in the second bus controller slot and the first bus controller slot is empty.

Abstract: A PCI function extension control circuit 1 monitors the transaction of a first PCI bus and a second PCI bus and makes a bus switch emit an open and close control signal when it concerns an access to a desired configuration area. The bus switch disconnects or connect the PCI bus 101 and the PCI bus 102 upon the reception of the open and close control signal from the PCI function extension control circuit 1. The PCI function extension control circuit 1 outputs a desired PCI control signal to the first PCI bus, or the second PCI bus.