Abstract: Methods and apparatus for selectively allowing and disallowing changes to an impedance control signal applied to bus driver circuits coupling a device or system to a common, shared bus where impedance of the bus may vary over time. Well known impedance sensing circuits may be coupled to a common bus, such as a PCI bus, and may be used to generate an impedance control signal to be applied to well-known bus driver circuits, including, for example, PCI bus driver circuits, to vary the drive level of such bus driver circuits in accordance with the present electrical impedance sensed on the bus. Features and aspects hereof permit selectively allowing and disallowing changes to such impedance control signals as applied to the driver circuits based upon the present state of the bus and/or the present state of signals driven on the bus by the system embodying the features and aspects hereof.

Abstract: A multi-channel serial advanced technology attachment (SATA) control system and control card thereof includes a first SATA control module, a first access-grant arbitration unit, a second SATA control module, a second access-grant arbitration unit and a path selection module. Through an arbitration process performed in the first and second access-grant arbitration units, an access-grant is determined. And a selection signal is generated based on the process result that is sent to the path selection module, to switch a transmission path to the SATA control module which has acquired the access-grant. Therefore, multi-channel SATA data access function may be achieved.

Abstract: A high speed computer processor system has a high speed interface for a graphics processor. A preferred embodiment combines a PowerPC microprocessor called the Giga-Processor Ultralite (GPUL) 110 from International Business Machines Corporation (IBM) with a high speed interface on a multi-chip module.

Abstract: The present invention relates to a USB-based host-to-host networking method capable of transferring information between two hosts. Devices for the method comprise: a register, a pair of FIFO control command transmitters and at least one FIFO bulk transmitter. The register is to temporarily store control commands for information transaction and acts as a buffer. The control command transmitters is to connect two serial interface engines interfacing respectively with the USB interface of each host, by which the information transfer control commands can be delivered from either host. The bulk information transmitter connects to the two serial interface engines for bulk transfer so that any host is capable of issuing the information transfer control commands for executing data transaction between hosts. The present invention provides a new design for networking controller connection by reducing the number of control command transmitters needed, and also capable of transferring bulk information between hosts.

Abstract: Embodiments of apparatuses, systems, and methods are described for communicating information between functional blocks of a system across a communications fabric. A first functional block communicates a single request fully describing attributes of a two-dimensional data block across the communication fabric to a second functional block capable of decoding the single request to obtain the attributes of the two-dimensional data block. At least one of the functional blocks transmits data associated with the single request across the communication fabric.

Abstract: In at least some embodiments, a computer system comprises a central processing unit (“CPU”), a bridge device coupled to a main memory, and a cache controller coupled between the bridge device and the CPU. The computer system further comprises a cache memory coupled to the cache controller and providing memory space to the CPU, wherein the cache controller allows communication between the CPU and the bridge device when the CPU communicates using a first protocol and the bridge device communicates using a second protocol, and wherein the cache controller allows communication between the CPU and the bridge device when the CPU communicates using the second protocol and the bridge device communicates using the first protocol.

Abstract: An expansion adapter is used to communicate both PCI and AGP devices to the north bridge chip of a computer. The expansion adapter includes a first AGP bus control module communicable with the north bridge chip via a first AGP bus, and a second AGP bus control module in communication with the first AGP bus control module, communicable with an AGP device via a second AGP bus. The identifying codes of the first and second AGP bus control modules are set to show no AGP device function in order to allow the AGP device to communicate with the north bridge chip via the expansion adapter. The expansion adapter further includes a PCI bus control module in communication with the PCI device and the first AGP bus control module for controlling data transmission between the first AGP bus control module and the PCI device.

Abstract: To efficiently personalize multiple bus interfaces, an input/output (I/O) integrated circuit (IC) is provided. This I/O IC can include two local bus control blocks, wherein each local bus control block can be configured to provide a selected personality. The selected personality can include an IDE (intelligent drive electronics) interface, an MPEG-TS (Moving Picture Experts Group Transport Stream) interface, a GPIO (general purpose input/output) interface, or a PCI (peripheral component interconnect) interface. Advantageously, when the two local bus control blocks are configured, they can provide one of a combined IDE/MPEG-TS interface, a combined IDE/GPIO interface, and the PCI interface. Thus, the I/O IC has a common set of pins that can be allocated to one or more bus types, depending on net pin count.

Abstract: A method of communicating a VMEbus transfer (235) from an initiator VMEbus domain (202) over an IP packet network (210) to a responder VMEbus domain (204) can include the initiator VMEbus domain creating the VMEbus transfer and reading a VMEbus destination address (452) of the VMEbus transfer. The VMEbus destination address can be mapped to a responder VMEbus domain IP address and the VMEbus transfer encapsulated in an IP packet (236). The IP packet can be communicated to the responder VMEbus domain over the IP packet network.

Abstract: In one embodiment, the invention provides a method comprising determining information about an input/output device located north of the memory controller; and controlling a response of the memory controller to read/write requests on a processor bus to a bus agent on a system bus south of the memory controller based on the information.

Abstract: A communication system for issuing commands from an initiator to a target, thereby allowing the target to write or read out data into/from a memory area which the initiator has and exchanging the data. The initiator transmits read and write commands for the memory area to the target so as not to exceed the total number of commands which can be held by the target. The target holds the received read and write commands, holds references to the commands by different queues, and independently processes the commands, so that the number of the commands to be transmitted can be managed efficiently.

Abstract: A Peripheral Component Interconnect (PCI) bridge between two buses prefetches read data into a cache. The number of cache lines to prefetch is predicted by a prefetch counter. One prefetch counter is kept for each type of memory-read command: basic memory-read (MR), memory-read-line (MRL) that reads a cache line, and memory-read-multiple (MRM) that reads multiple cache lines. For each type of read command, counters are kept of the number of completed commands, bus-disconnects (indicating under-fetch), and master-discard of data (indicating over-fetch). After a predetermined number of execution of each type of command, the command's prefetch counter is incremented if under-fetching occurred, or decremented if over-fetching occurred, as indicated by the disconnect and discard counters for that type of read command. The command's other counters are reset. Prefetching is optimized for each type of read command. MRM can prefetch more data than MRL or MR.

Abstract: A system and method for scaling a bus based on a location of a device on the bus are disclosed. An information handling system includes a host bridge interfaced between a local bus and a peripheral bus operable to run at a plurality of bus speeds generated by the host bridge. A plurality of expansion slots are coupled to the peripheral bus and a bus switch is coupled to the peripheral bus between at least two of the expansion slots. Control logic is interfaced with the host bridge and the expansion slots. The control logic is operable to enable at least one of the expansion slots based on a signal received from each of the expansion slots by manipulating the bus switches.

Abstract: A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port (“AGP”) bus and host and memory buses, as a bridge between an additional registered peripheral component interconnect (“RegPCI”) bus and the host and memory buses, or as a bridge between a primary PCI bus and an additional RegPCI bus. The function of the multiple use chip set is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or an additional registered PCI bus bridge is to be implemented. The multiple use core logic chip set has an arbiter having Request (“REQ”) and Grant (“GNT”) signal lines for each PCI device utilized on the additional registered PCI bus. Selection of the type of bus bridge (AGP or RegPCI) in the multiple use core logic chip set may be made by a hardware signal input, or by software during computer system configuration or power on self test (“POST”).

Abstract: Disclosed is a clock distribution device and method in a compact PCI system based multi-processing system. A compact PCI based multi-processing system preferably includes processing signals upon mounting various circuit boards on multiple slots, even if the location of the system slot is varied, the skew of clocks transmitted to the other slots may be minimized. Accordingly, the system may be configured in a flexible manner because of such variability of the system slot's location. Further, the system may be efficiently repaired and maintained because it is possible to easily and quickly take measures in response to any failure occurring on the board mounted on the system slot.

Abstract: An aliasing technique allows transparently connecting multiple interconnects across a shared cross-connect interconnect, allowing devices on one interconnect to communicate with devices on another interconnect as if both interconnects were connected by a single interconnect bridge. Each interconnect appears to the cross-connect interconnect as a device on the cross-connect interconnect. Transactions between devices on different interconnects are aliased by a routing engine connected to the cross-connect interconnect for transmittal across the cross-connect interconnect and are invisible to other transactions on the cross-connect interconnect. Transactions between devices on the same interconnect are invisible to other interconnects. Cache coherent requests are supported by the use of additional attribute bits.

Abstract: An architecture is provided that includes a reconfigurable bridge for routing data among functional units. Register transfer units effect the routing of data among registers that are associated with each functional unit. Synchronous and asynchronous register transfers are supported, including interrupt signal generation for efficient digital signal processor support. A preferred embodiment of the reconfigurable bridge includes a plurality of reconfigurable datapath units that provide ancillary functions to facilitate the processing and pre-processing of data items as they are transferred among registers. A preferred embodiment of the invention also includes an instruction memory that contains instructions to effect the desired register transfers and ancillary operations.

Abstract: A suspended or stuck condition of a serial bus controller is released by applying an artificial clock signal to the stuck bus controller in place of the normally applied clock signal. The artificial clock signal causes the stuck controller to advance in a communication transaction which was in progress when the stuck condition occurred, until a data signal is supplied at a logical level which permits the initiation of another transaction in accordance with the serial communication protocol of the bus. The ability to release the stuck condition avoids losing important data and other information that would be lost if the stuck condition was released by performing a reset of the stuck controller or the component to which it is connected.

Abstract: A method of electrically coupling a central processing unit (CPU) of a network server to a plurality of network interface modules. The method comprises providing each of the plurality of network interface modules with a respective bus adapter chip to route an I/O bus having a first format from the central processing unit to a primary side of each of the plurality of bus adaptor chips and routing another I/O bus of the first format from a secondary side of each of the plurality of bus adapter chips to respective ones of the network interface modules. The bus adapter chips also provide for arbitered access along the I/O buses and isolation of the CPU from electrical disruption when one the network interface modules is removed.

Abstract: The present invention provides a circuit system for data transmission between LPC devices, comprising: a first LPC bus, connected to a first LPC device; a second LPC bus, connected to a second LPC device; and an LPC host controller, able to drive the first LPC device through the first LPC bus and the second LPC device through the second LPC bus; wherein the LPC host controller further comprises an address register. The present invention further provides a method for data transmission between LPC devices, comprising the steps of: starting a first cycle through a first LPC bus by an LPC host controller, wherein a first LPC device sends a request to have a transaction with a second LPC device, and inserting a plurality of wait states after the request is received by the LPC host controller; and starting a second cycle through a second LPC bus by the LPC host controller, wherein the LPC host controller has a transaction with the second LPC device according to the request from the first LPC device.

Abstract: A data processing system includes first and second data processing devices coupled to each other through a midplane. Each data processing device includes a data storage processor; a root complex coupled to the data storage processor; and a switch device coupled between the root complex and at least one end point device. The switch device includes a first transparent bridge coupled to the root complex and a second transparent bridge coupled between the first transparent bridge and the at least one end point device, a first data path connected between the first transparent bridge and the midplane and a second data path connected between the first transparent bridge and the midplane through a non-transparent bridge.

Abstract: A configurable switch that enables multiple CPUs to be connected to multiple I/O devices through a single switch. The switches can be cascaded to enable more CPUs and/or more I/O devices in the tree. The configuration is transparent to the enumeration of the bus and endpoint devices. A simple management input such as SMBus or hardware strapping is used to set up the assignation of devices to CPUs. Utilization of a manager and the PCI Express hot plug controller registers enable hot-plug reconfiguration of the device tree as devices a switched between CPUs via PCI buses within the switch.

Abstract: A USB-HUB device in which a request for a device connected to a port of the USB-HUB device may be executed by commonly using a serial interface engine of the HUB device has been disclosed. A USB-HUB device (1) may include a HUB address register (124), a HID address register (125), a first comparator (123), a second comparator (113), a virtual port control unit (18) and a HID request processing unit (131). A HID address register (125) may store a HID address. A first comparator (123) may compare a value of a HUB address register (124) with an address field of a supplied token packet. A second comparator (113) may compare a value of a HID address register (125) with an address field of the supplied token packet. A virtual port control unit (18) may indicate a status of a port to which a device (3) may be virtually connected. A HID processing unit (131) may perform a process in response to a request for the device (3).

Abstract: Embodiments of the present invention relate to an apparatus including a first processor module, a second processor module, and a bus. The bus is coupled to the first processor module and the second processor module. The bus is configured to transmit both processor related communication and memory related communication. In embodiments, the first processor module includes a first central processing unit and the second processing module includes a second central processing unit. Accordingly, in embodiments of the present invention, a single bus can be used to communicate between processors and memories. The present invention is useful for real time duplication of memory, high speed duplication of memory, and/or a coherency check of memory between a first processing module and a second processing module.

Abstract: Even when an S-PCI bus 1b requests transfer while a P-PCI bus 1a is executing burst transfer, assert of a TRDY# signal for data transfer of the P-PCI side is delayed so that next data transfer of the P-PCI side is completed within 8 clock cycles since the TRDY# signal for data transfer of the P-PCI side is asserted.

Abstract: In a serial bus network, an environment is provided, in which the serial bus is divided to two local buses and a specific terminal connected to one of the local buses can reliably occupy other terminals connected to the other local bus without influence on the terminals connected to the local buses. A specific terminal is connected to a local bus 101, to which an inner portal 3 is connected, and an ID information thereof is preliminarily recorded in a ROM 8. After a power source is turned on, the specific terminal connected to the side of the inner portal 3 is detected according to the ID information from the ROM 8. An ID information of all of nodes connected to a local bus 104, to which an outer portal 4 is connected, is read out and stored in a control portion 5. A bus reset is generated on the local bus 101. In order to give a connection information of the local bus 104, a self-ID packet is generated by the control portion 5 and transmits it through a dedicated PHY 6.

Abstract: In a bus system having a plurality of instruments linked to each other, the invention proposes a method which avoids useless data transmission or useless occupation of a data transmission line. A data transmission line is established for starting receipt/transmission of data after available instruments for the transmission/receipt of the date are identified. During the transmission of the data, the enable and disable state of transmission/receipt of the data is monitored and if desired, the data transmission is broken.

Abstract: In one general aspect, methods and devices for use with multiple communications protocols automatically determine which communications protocol to use when connected to a system bus. Signals transmitted on the system bus are monitored to determine what communications protocol the system bus is using. After determining which communications protocol the system is using, a compatible communications protocol is selected from one of several communications protocols stored in a device's memory. As a result, a user may connect a device to the system bus without having to determine which communications protocol is used by the system bus. Furthermore, suppliers may stock a single type of device that is compatible with multiple communications protocols reducing overhead associated with stocking devices. In addition, a device may be switched between systems without regard to the communications protocol of the device or system.

Abstract: A system having a PCI Express fabric and PCI devices connected thereto transmits data from the PCI devices having PCI Express traffic classes assigned. A PCI Express to PCI bridge assigns a predetermined address to the grant line for each PCI device coupled to the PCI bus and stores this address along with the data from the PCI device in the PCI transaction queues. When the data is transmitted along the PCI Express fabric, or when it is processed within the PCI Express to PCI bridge, the address assigned to the respective grant line becomes the PCI Express traffic class for that data. This enables the commands from one device to be processed irrespective of commands from other PCI devices on the PCI bus.

Abstract: In an environment in which plural external storage devices having different function control interfaces are intermixed, when a function of a storage device is controlled from a computer, a common interface for controlling the function of the storage device is provided. A device that provides the common interface manages an interrelationship between a storage area recognized by a host computer and a storage area provided by the storage device and associates a storage area which becomes a target of a function control instruction with the storage device that provides the storage area. A type of the storage device that provides the storage area which becomes the target of the function control instruction is identified and function control is ordered through a function control interface unique to the device.

Abstract: A network interface is described in which a single computer bus is split over a long distance into two or more inter-communicating buses. On one bus, processing and applications are provided and on the other remote bus, peripheral and local controllers are provided. The buses communicate through a series of: bridge, FPGA, FPGA and bridge. Between the FPGAs, a communication path provides long distance communication.

Abstract: A method of directly transferring data across a CompactPCI™ backplane (170) via a fully meshed orthogonal network (370). The CompactPCI backplane (170) incorporates a different type connector at its P4 location, in conjunction with a standard family of IEC 61074 connectors at its P1, P2, P3, and P5 locations, to provide high speed data transfer with additional shielding and noise control.

Abstract: A communication system for issuing commands from an initiator to a target, thereby allowing the target to write or read out data into/from a memory area which the initiator has and exchanging the data. The initiator transmits read and write commands for the memory area to the target so as not to exceed the total number of commands which can be held by the target. The target holds the received read and write commands, holds references to the commands by different queues, and independently processes the commands, so that the number of the commands to be transmitted can be managed efficiently.

Abstract: Techniques are disclosed for enabling a single computer system to execute both operating systems that permit multiple devices to be mapped to a single PCI function and operating systems that do not permit such mapping. Prior to loading and executing an operating system (e.g., during system reset), the computer system determines whether the operating system supports mapping of multiple devices to a single function. If such mapping is supported, the computer system maps multiple devices on a single PCI card to a single function in the PCI configuration space for the card. If such mapping is not supported, the computer system maps each device to a separate PCI function. The computer system then loads and executes the operating system. The operating system is thereby enabled to access all devices on the bus according to the particular device-function mapping scheme supported by the operating system.

Abstract: A self-powered peripheral apparatus is connected upstream to another apparatus via a universal serial bus (USB), wherein one of the conductors of the USB provides a supply voltage to the self-powered peripheral apparatus. One of the two data conductors of the USB is connected to a voltage source of the self-powered peripheral apparatus. The self-powered peripheral apparatus includes a control device for controlling the data conductor supply for supplying the latter only if the supply voltage is present on the supply conductor. The control device includes a circuit for detecting the supply voltage and a logic circuit for controlling the regulator.

Abstract: A bridged controller for reducing the overhead of cache coherency processing on each of a plurality of primary controllers and increasing the overall throughput of the system. The bridged controller interfaces with dual-active pair of host-side controllers and the backend disk drive buses. The third controller allows a doubling of the number of backend busses, reduces the overhead of cache coherency processing on each primary host-side controller and doubles the overall throughput.

Abstract: A system and method is disclosed for providing a pre-fetch memory controller in a computer system that comprises a plurality of master agents. The memory controller comprises a bus interface, a memory interface and a plurality of pre-fetch queues. In one embodiment each pre-fetch queue is assigned to a master agent. In an alternate embodiment the pre-fetch queues are dynamically assigned to master agents. The bus interface services memory read requests, memory write requests, and pre-fetch requests. Data may be pre-fetched from main memory and stored in the pre-fetch queues. This reduces the latency for memory read requests and improves the efficiency of the memory interface with the main memory.

Abstract: If a block read cannot be used to read out from a configuration ROM information, the number of times of issue of a quadlet read request increases. This degrades the processing efficiently of a device that issues the request. In addition, the bus occupation ratio of a 1394 serial bus by the request becomes high, and the speed of processing through the 1394 serial bus decreases. To solve these problems, information stored in the configuration ROM area of a device is read out, and it is determined on the basis of the readout information that configuration information identical to the configuration ROM information is stored in an address area (block readable area) different from the configuration ROM area, the offset is changed, and the configuration information is read out from the address area different from the configuration ROM area.

Abstract: Embodiments are provided in which a method is described for transferring data in a digital system including a first bus, a second bus, a PCI-X bridge coupling the first and second buses, and a first device and a second device residing on the first and second buses, respectively. The first bus has the same or higher bandwidth than that of the second bus. According to the method, the PCI-X bridge immediately starts or resumes forwarding split completion data from the first device to the second device if the first device starts or resumes split completion data transfer to the PCI-X bridge at the beginning of a block (i.e., the start or resume byte address has the form of 128N). If the first device starts transfer to the PCI-X bridge not at the beginning of a block, the PCI-X bridge refrains from forwarding split completion data until (a) the first device sends the data byte at the beginning of the next block to the PCI-X bridge or (b) the byte transfer count is exhausted, whichever occurs first.

Abstract: An electronic system interconnect. The interconnect comprises a first node and a second node coupled to the first node. The interconnect is initially configured to include the first and second nodes. A third node is added to the interconnect after the interconnect is initially configured, and the first node responds to the addition of the third node by initiating a new connect handshake with the third node. The first node begins by transmitting a first signal to the third node. The first node signals that the third node has been added to the interconnect if the third node responds to the first signal by transmitting a second signal. The first node causes the interconnect to be reconfigured if the third node transmits a third signal in response to receiving the first signal.

Abstract: A technique is disclosed for facilitating data processing in a computer system. The technique utilizes logic to implement a dual mode design for PCI/PCI-X computer systems that enables optimal efficiency in regardless of which mode the system is operating in. The technique involves the implementation of two sets of transmitting and receiving elements, one tuned to PCI protocol timing and the other to PCI-X protocol. Therefore, allowing the system to process both PCI and PCI-X transactions without adversely affecting the other functional mode. The technique also enables an operator to adjust the clock timing separately for each protocol without having a detrimental affect on the other operating protocol.

Abstract: Systems are provided for the offloading of protocol control and conversion information within microprocessor-based systems. A converter controller comprises a first interface and protocol, as well as a second interface and protocol. An intermediate protocol and interface is interconnected to both the first protocol and the second protocol, and forwards or offloads protocol information to the system CPU, which comprises device driver information for protocol conversion and/or control. The CPU acts upon the received protocol information, performs protocol conversion as necessary, and forwards the converted protocol information back to the converter controller through the intermediate interface. Some embodiments of the offloading protocol conversion system comprise a SDIO controller within a USB-based device.

Abstract: A user configurable, modular port expansion system allows the user of a host system such as a USB-enabled personal computer to customize a desired configuration of one or more peripheral device modules without the use of cables between modules. The peripheral device modules are physically and electrically connectable to each other side-by-side between a hub end module and a power end module in any sequence so that there can be provided, within the limits of the host port specification, virtually any number of selected, expanded functions in any combination. The peripheral device modules may include, by way of example, a standard parallel DB-25 port module, a two-port serial PS/2 module, a two-port serial DB-9 module, a four- or seven-port USB hub, an RJ-11 Ethernet LAN module, and an RJ-11 modem module.

Abstract: A bus data interface, structure and method for transmitting the data of a PCI bus is disclosed. The bus data interface comprises a high-bit transmitting buffer, a low-bit transmitting buffer, a multiplexer, a strobe generator, and a data distributor. The strobe generator utilizes the bus request signal and bus grant signal to transmit a data strobe signal in response to the PCI clock. According to the rising edge and falling edge of the data strobe signal, the data distributor retrieves data according to the data strobe signal. Further, the invention is compatible with the original PCI bus and allows the PCI bus to transmit data with a dual speed.

Abstract: A system for transmitting and receiving data between a data transmitting device such as a computer and a data receiving device such as a peripheral device is capable of shortening the time required to complete transmission and receipt of all of the data, including re-transmission of missed data. The data transmitting device is provided with a first transmitting section to periodically and sequentially send a plurality of split data obtained by splitting data to be transmitted to the peripheral device, and with a second transmitting section. The second transmitting section sends split data, when the data receiving device was unable to receive split data fed from the first transmitting section, to the data receiving device during a period of time between time bands in which the first transmitting section transmits the split data.

Abstract: A method, system and apparatus for providing inter-connective access of a plurality of controllers to a plurality of serial storage devices are provided. Serial storage devices are provided with a serial operative connection to a data communication bridge. The bridge is operatively coupled to a plurality of controllers. The plurality of controllers is provided concurrent targeted connections to the set of serial storage devices. In one embodiment, InfiniBand® technology further increases the scalability and enhances the reliability of a data communication system provided with a plurality of (S-ATA) storage devices. The reliability of the data communication system is enhanced because if one controller should fail, another controller may still achieve and maintain access to the plurality of serial storage devices.

Abstract: Methods and apparatus for inbound PCI configuration cycles are disclosed. By definition, PCI bridges block upstream progress of configuration cycles initiated by a PCI bus master on their secondary buses. In the described embodiments, a PCI bus master can execute a configuration cycle despite this limitation, by converting the configuration cycle command to Memory Read and Write commands that a PCI bridge will forward upstream. The PCI bus master writes the address of a target configuration register to a first predefined address, and pushes or pulls data from that target register by subsequently initiating a memory access to a second predefined address. A platform chipset is designed to recognize Memory Read and Write accesses to the predefined addresses as relating to an inbound configuration cycle. When a memory access to the second address is received, the chipset uses the information stored at the first address to form and execute a configuration cycle on behalf of the downstream PCI bus master.

Abstract: A system wherein a signal over a Universal Serial Bus (USB) interface is received by a receiver component. A mixed signal block utilizes a mixed signal interface to transmit the signal to a processor block.

Abstract: A method and apparatus embedding PCI-to-PCI bridge functions in PCI devices using PCI configuration header type 0 is disclosed. The PCI-to-PCI bridge function is implemented in PCI devices using the standard Type 0 PCI Configuration Header that supports up to six Base Address Registers. Having the PCI-to-PCI bridge function integrated with other PCI device functions has the advantage of reducing valuable card real estate and power consumption.

Abstract: The present invention is an I2C (inter-IC control) bridge device which implements a communication protocol layered on top of a standard I2C protocol. The layered protocol used by the bridge device is termed the “Layered I2C Protocol”—abbreviated “LIP”. Thus the bridge device is called a “LIP bridge device”. The LIP bridge device provides I2C address extension, data integrity checking, and fault detection and isolation when inserted between an I2C bus master and it's intended target I2C device. Each LIP bridge device has at least two attached I2C busses—a parent bus and a child bus. The LIP bridge operates as a slave on its parent bus, and a master of its child bus. The Layered I2C protocol is specified to operate on a bus between one or more bus masters and the parent bus of one or more LIP bridge devices. The child bus is used for attaching multiple I2C devices and/or one or more LIP bridge devices.