Abstract: A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

Abstract: In accordance with an embodiment of the present disclosure, a semiconductor system includes a first semiconductor device coupled to a first transmission line, and configured to transmit a first packet to a second transmission line on the basis of first destination information of the first packet received through the first transmission line; a second semiconductor device coupled to the first semiconductor device through the second transmission line, and configured to transmit a second packet to a third transmission line on the basis of second destination information of the second packet received through the second transmission line; and a third semiconductor device coupled to the second semiconductor device through the third transmission line, coupled to the first semiconductor device through the first transmission line, and configured to transmit a third packet to the first transmission line on the basis of third destination information of the third packet received through the third transmission line.

Abstract: A calculation processing apparatus is disclosed. In one example, an exclusive memory stores an exclusive area different from an address space of a processor. A data transfer unit performs transfer processing of data items between the address space and the exclusive memory. A calculation processing unit performs calculation processing between the data items stored in the exclusive memory. A command resistor group holds each command of command columns received from the processor in each resistor. A state machine manages a state of processing in the data transfer unit and the calculation processing unit. A control unit controls the command resistor group so as to hold the command and controlling the command resistor group such that the commands held by the command resistor group are fed to any of the data transfer unit and the calculation processing unit depending on the state.

Abstract: A data storage device may include: a nonvolatile memory apparatus including a plurality of groups configured by dividing a plurality of planes in interleaving units; and a controller configured to check whether a group including a read region of a current read command is included in a group including a read operation of a previous read command and whether the read region of the current read command extends over two or more groups, when receiving the current read command, and control the nonvolatile memory apparatus to perform cache read or interleaving read based on the check result.

Abstract: The present disclosure advantageously provides a method and system for transferring data over at least one interconnect. A request node, coupled to an interconnect, receives a first write burst from a first device over a first connection, divides the first write burst into an ordered sequence of smaller write requests based on the size of the first write burst, and sends the ordered sequence of write requests to a home node coupled to the interconnect. The home node generates an ordered sequence of write transactions based on the ordered sequence of write requests, and sends the ordered sequence of write transactions to a write combiner coupled to the home node. The write combiner combines the ordered sequence of write transactions into a second write burst that is the same size as the first write burst, and sends the second write burst to a second device over a second connection.

Abstract: A memory-efficient last level cache (LLC) architecture is described. A processor implementing a LLC architecture may include a processor core, a last level cache (LLC) operatively coupled to the processor core, and a cache controller operatively coupled to the LLC. The cache controller is to monitor a bandwidth demand of a channel between the processor core and a dynamic random-access memory (DRAM) device associated with the LLC. The cache controller is further to perform a first defined number of consecutive reads from the DRAM device when the bandwidth demand exceeds a first threshold value and perform a first defined number of consecutive writes of modified lines from the LLC to the DRAM device when the bandwidth demand exceeds the first threshold value.

Abstract: The present invention relates to a memory with error correction function, comprising a data array, an ECC array, an ECC encoding module, an ECC decoding module, a first data selection module, a second data selection module and a data output module; wherein when data is being written, the first data selection module receives the data to be written, and determines whether to receive the data from the data array in response to a control signal that affects the length of the data; when data is being read, the second data selection module controls the length of the data output from the data output module in response to the control signal that affects the length of the data. The invention further relates to a method of correcting errors in a memory.

Abstract: A distributed storage system replicates data for a primary logical storage object on a primary node of the storage system to a secondary logical storage object on a secondary node on the distributed storage system. Failures in writing data to the primary logical storage object or failures in the replication of the data to the secondary logical storage object can cause data that should be synchronized to become divergent. In cases where the data may be divergent, reconciliation operations can be performed to resynchronize the data.

Abstract: A method of operating a memory controller is provided. The method of operating a memory controller according to an exemplary embodiment of the present inventive concepts includes sequentially receiving, by the memory controller, first data segments each having a first size from a host, sequentially storing, by the memory controller, the first data segments in the buffer until a sum of sizes of changed data among data stored in a buffer included in the memory controller is a second size, and programming, by the memory controller, the changed data having the second size in a memory space of a non-volatile memory as a second data segment.

Abstract: In one embodiment of the invention, a system architecture for bus masters and bus arbiters are provided to support routing and failover. The system comprises large pools of bus masters, a plurality of sets can be configured to control a plurality of slave devices wherein each set contains a collection of bus masters attached to central arbiter driving one of the system buses. Each set controls a group(s) of slave device that are primarily controlled by the bus master(s) within the set. Hence, a system can therefore include of a plurality of sets and can control a group of slave devices.

Abstract: Technologies are generally described herein for bandwidth amplification using a pre-clock signal to latch data at a latch in an input register of a sender section while passing the data through a multiplexer of the sender section in a serial manner. In some configurations, pre-clocking the multiplexer can allow for parallel operations to occur within the sender section, thus hiding or reducing the effects of certain serialization delays associated with the multiplexer. Furthermore, the pre-clocking of the multiplexer, in some configurations, hides or reduces the register latch hold and setup delays. A method may create three levels of parallelization of latencies between a sender circuit, a serialization circuit, and a receiver circuit by overlapping them at same time.

Abstract: A home node of a data processing apparatus that includes a number of devices coupled via an interconnect system is configured to provide efficient transfer of data to a first device from a second device. The home node is configured dependent upon data bus widths of the first and second devices and the data bus width of the interconnect system. Data is transferred as a cache line serialized into a number of data beats. The home node may be configured to minimize the number of data transfers on the third data bus or to minimize latency in the transfer of the critical beat of the cache line.

Abstract: The subject matter described herein relates to methods, systems, and computer readable media for automatically and selectively enabling burst mode operation in a storage device. One method includes monitoring data written by a host device to a storage device. The method further includes determining whether the data is of a type for which burst mode operation of the storage device is indicated. The method further includes, in response to determining that the data is of a type for which burst mode operation is indicated, automatically enabling burst mode operation of the storage device.

Abstract: A system and method are disclosed for managing memory interleaving patterns in a system with multiple memory devices. The system includes a processor configured to access multiple memory devices. The method includes receiving a first plurality of data blocks, and then storing the first plurality of data blocks using an interleaving pattern in which successive blocks of the first plurality of data blocks are stored in each of the memory devices. The method also includes receiving a second plurality of data blocks, and then storing successive blocks of the second plurality of data blocks in a first memory device of the multiple memory devices.

Abstract: An optimized design of n-write/1-read port memory comprises a memory unit including a plurality of memory banks each having one write port and one read port configured to write data to and read data from the memory banks, respectively. The memory further comprises a plurality of write interfaces configured to carry concurrent write requests to the memory unit for a write operation, wherein the first write request is always presented by its write interface directly to a crossbar, wherein the rest of the write requests are each fed through a set of temporary memory modules connected in a sequence before being presented to the crossbar. The crossbar is configured to accept the first write request directly and fetch the rest of the write requests from one of the memory modules in the set and route each of the write requests to one of the memory banks in the memory unit.

Abstract: A method for performing a cycle update on a RAID storage device by a storage system includes storing first data in a first buffer. The method additionally includes retrieving a command block associated with the first data, and executing the command block to perform a set of operations in a sequence specified by the command block. The set of operations includes reading second data from an address of the RAID storage device and generating redundant data based on the first data with the second data. The set of operations further includes storing the redundant data in a second buffer and writing the first data to the address of the RAID storage device when the RAID storage device is a data storage device, and writhing the redundant data stored in the second buffer to the address of the RAID storage device when the RAID storage device is a parity storage device.

Abstract: Telecommunication networks are under stress due to rapid traffic increase cause mostly by large file transfers. Disclosed herein is a cross-layer transport protocol specifically designed to efficiently handle large transactions. Traffic generated from large transactions is shaped into a periodic succession of fixed-size data frames. Each transaction can then be scheduled for transmission using a two-way reservation protocol. Exemplary results show that the proposed approach is capable of significantly improving goodput and end-to-end delay relative to TCP, improving efficiency of bandwidth utilization by over 40%.

Abstract: A method for providing improved sequential read performance in a storage controller is provided. In response to the storage controller receiving a host read request from a host computer, the method includes identifying, by the storage controller, a largest burst length of a plurality of burst lengths in a memory of the storage controller, and determining a maximum number of consecutive times between bursts having a value less than a predetermined value. A burst includes a consecutive group of sequential host read requests from the same host computer. The method also includes multiplying the largest burst length of the plurality of burst lengths by the maximum number of consecutive times between bursts having a value less than the predetermined value to obtain an effective burst length and reading into a storage controller cache memory at least the effective burst length of data from storage devices coupled to the storage controller.

Abstract: A multi-hierarchy interconnect system for a cache system having a tag memory and a data memory includes an address interconnect scheduling device and a data interconnect scheduling device. The address interconnect scheduling device performs a tag bank arbitration to schedule address requests to a plurality of tag banks of the tag memory. The data interconnect scheduling device performs a data bank arbitration to schedule data requests to a plurality of data banks of the data memory. Besides, a multi-hierarchy interconnect method for a cache system having a tag memory and a data memory includes: performing a tag bank arbitration to schedule address requests to a plurality of tag banks of the tag memory, and performing a data bank arbitration to schedule data requests to a plurality of data banks of the data memory.

Abstract: The present disclosure includes methods and apparatuses for power management. One method includes transferring data between a memory and a controller via an input/output (I/O) bus, and adjusting an amount of power consumed in association with transferring the data by throttling the I/O bus.

Abstract: A memory stores data generated by a processor and a transferring unit burst transfers the data from the memory unit to a processing unit. Based on an access capability of the processor when accessing the memory, a prescribed value for a burst width and information concerning the time that the processing unit consumes to process the data are set in advance at the data transferring apparatus. When the transferring unit performs data transfer, the time allowed for data transfer is calculated based on the information concerning the time that the processing unit consumes to process the data, and the burst width is determined as a value greater than or equal to the prescribed value for the burst width and is as close as possible to the prescribed value for the burst width within a range in which data transfer can be finished within the allowed time.

Abstract: The present invention provides a method for increasing data throughput for a wireless USB system that includes wire adapters that wirelessly transmit data between a host system and a USB enabled device.

Abstract: A data processing apparatus may include: a data conversion unit configured to designate one-transfer data as one transfer unit and designate a predetermined number of transfer units as one conversion unit when a plurality of input data sequentially input is converted into transfer data of which the number of bits is the same as that of a data bus having a predetermined number of bits, and the transfer data is sequentially transferred, and arrange the input data in the transfer data within the conversion unit. The data conversion unit may include: a data generation unit, a first data arrangement change unit, and a first data selection unit configured to sequentially select the changed data in which the position of the input data is changed by the first data arrangement change unit and output the selected changed data as the transfer data in the data conversion unit.

Abstract: A method of providing one or more computing devices with access to a plurality of resources. The plurality of resources are provided by at least one physical device. The method comprises, at a first control element receiving a data packet transmitted by one of said one or more computing devices, and determining whether said data packet comprises a command including a first logical identifier identifying one of said resources. If it is determined that said data packet comprises a command including a first logical identifier a second logical identifier is obtained, the second logical identifier being associated with said first logical identifier and identifying said one of said resources. A request including said second logical identifier is transmitted to a second control element, the second control element being arranged to identify a physical device associated with said second logical identifier and to forward said request to the identified physical device.

Abstract: A method and apparatus for a memory bus interface including a read data strobe. The interface includes a chip select for delivering a chip select signal that indicates when a peripheral device is activated, wherein said bus interface provides communication between a host device and said peripheral device. The interface also includes a differential clock pair for delivering a differential clock signal. A read data strobe is included in the interface for delivering a read data strobe signal from the peripheral device. The interface includes a data bus for delivering command, address, and data information. The read data strobe indicates when valid data is present on the data bus.

Abstract: A memory device includes a first bank group, a second bank group, where the first and second bank groups are each configured to output multi-bit data in parallel in response to a read command, a data transferor configured to receive the multi-bit data outputted in parallel from the first bank group or the second bank group and output the multi-bit data at a time interval corresponding to an operation mode, first global data buses configured to transfer the multi-bit data outputted from the first bank group to the data transferor, second global data buses configured to transfer the multi-bit data outputted from the second bank group to the data transferor, and a parallel-to-serial converter configured to convert the multi-bit data outputted from the data transferor into serial data according to the operation mode.

Abstract: A computer peripheral device includes a host interface, which is configured to communicate over a bus with a host processor and with a system memory of the host processor. Processing circuitry in the peripheral device is configured to receive and execute work items submitted to the peripheral device by client processes running on the host processor, and responsively to completing execution of the work items, to generate completion reports and to write a plurality of the completion reports to the system memory via the bus together in a single bus transaction.

Abstract: Techniques are disclosed relating to data inversion encoding. In one embodiment, an apparatus includes an interface circuit. The interface circuit is configured to perform first and second data bursts that include respective pluralities of data transmissions encoded using an inversion coding scheme. In such an embodiment, the initial data transmission of the second data burst is encoded using the final data transmission of the first data burst. In some embodiments, the first and second data bursts correspond to successive write operations or successive read operations to a memory module from a memory PHY.

Abstract: A storage device includes a processing state value calculator that calculates a first processing state value representing a state of data forwarding from the storage device via the connection lines; a notifier that notifies the first processing state value to the second storage device; a receiver that receives a second processing state value representing a state of data forwarding from another storage device (second storage device) via the communication lines and calculated in the second storage device; a multiplicity calculator that calculates, using the first processing state value and the second processing state value, a multiplicity representing the number of data forwarding processes which the storage device is able to simultaneously carry out on the communication lines; and a forwarding controller that forwards data via the communication lines within the calculated multiplicity, so that data may be optimally forwarded via the connection lines.

Abstract: Data is managed in a Host Wireless Adapater (HWA)-Device Wireless Adapater (DWA) system by receiving at the HWA a wireless packet from the DWA which contains a DWA Transfer Result message. At the HWA, the DWA Transfer Result message is parsed. In the event parsing the DWA Transfer Result message indicates there is data ready to be sent over a wireless channel between the HWA to the DWA a Micro-scheduled Management Command (MMC) is generating at the HWA and the MMC is transmitted from the HWA to the DWA. The MMC is transmitted prior to receiving a Transfer Request message at the HWA from an HWA driver and the data is transmitted from the DWA to the HWA in response to receiving the MMC.

Abstract: A system and method for determining media to be exported out of a media library is described. In some examples, the system determines a media component to be exported, determines the media component is in the media library for a specific process, and exports the media component after the process is completed.

Abstract: Various techniques are provided to support efficient data transfers over serial data streams. In one example, a serial device may be used to efficiently transfer data between a host device and the serial device over a data stream of a serial interface. A data stream value identifying the data stream may be stored in a register indexed by a tag associated with a command received from the host device. The command may be passed to a storage media device, wherein the passing is controlled by a processor of the serial device. The tag may be extracted from an address value received from the storage media device in response to execution of the command by the storage media device. The data stream value may be retrieved from the register using the extracted tag as an index without requiring an interrupt to the processor to determine the data stream value.

Abstract: A memory card controller includes a receiver, a flow controller, a continuity determination unit, and a command controller. When size of data transferred from the memory card reaches transfer size specified by first read command, the command controller controls the flow controller to transmit a response representing a transfer busy state, and pauses a transfer operation of the memory card. When the receiver receives a second read command in a state that the transfer operation of the memory card is paused, the command controller controls the flow controller to transmit a response representing transfer ready state to the transfer authorization request from the memory card so as to restart a transfer operation of the memory card.

Abstract: Methods and systems for conducting a transaction between a USB device and a virtual USB device driver are provided. A client USB manager stores in a buffer one or more data packets associated with the virtual USB device driver. The client USB manager dequeues one of the one or more data packets from the buffer. The client USB manager transmits the dequeued data packet to the USB device for processing. The client USB manager re-fills completed data packets from the buffer and queues the data packets for transmitting to the USB device without waiting for the virtual USB device driver.

Abstract: A system and method in accordance with the present invention provides for a solution benefiting from providing for non-duplicative access to data located in a system memory via the alignment of transaction sub-command breaking points with memory burst boundaries associated with the system memory, by creating a plurality of sub-commands for a transaction each having breaking points, identifying a plurality of memory burst boundaries for the system memory each having burst boundary points, and aligning a plurality of breaking points with a plurality of burst boundary points to provide single access to data located in the system memory.

Abstract: Methods and systems for conducting a transaction between a virtual USB device driver and a USB device are provided. A virtual USB manager of a hypervisor receives a one or more data packets from a client. The virtual USB manager stores of the one or more data packets in a buffer. The virtual USB manager dequeues a data packet from the buffer. The virtual USB manager transmits the data packet to the virtual USB device driver for processing.

Abstract: In a network protocol processing system in which variables of each of TCP transmission processing and TCP reception processing depend on each other, asynchronous parallel processing is realized between a transmission processing block and a reception processing block for updated protocol processing. Specifically, the system includes a high priority queue for transferring control data to be processed with high priority, a low priority queue for control data other than the above control data, and priority control means for distributing the control data to two kinds of queues. When a request for session establishment and the session disconnection of a new TCP session is issued from an application during transmission of TCP data, data related with the session establishment and the session disconnection is notified preferentially through the high priority queue, and other control data is transferred through the low priority queue.

Abstract: By referring to a receiving connection information table stored in a memory, a receiving assignment CPU assigns packets to parallel processing CPUs in such a manner that the packets received from the same connection are subjected to a receiving process by a corresponding parallel processing CPU. Each parallel processing CPU identifies the input QoS of a packet and notifies a QoS processing CPU, corresponding to that identified input QoS, of the packet. Each QoS processing CPU is arranged so that it corresponds to a QoS processing queue group in the memory and performs a QoS process on this QoS processing queue group.

Abstract: In one embodiment, the present invention provides for a layered communication protocol for a serial link, in which a link layer is to receive and forward a message to a protocol layer coupled to the link layer with a minimal amount of buffering and without maintenance of a single resource buffer for adaptive credit pools where all message classes are able to consume credits. By performing a message decode, the link layer is able to steer non-data messages and data messages to separate structures within the protocol layer. Credit accounting for each message type can be handled independently where the link layer is able to return credits immediately for non-data messages. In turn, the protocol layer includes a shared buffer to store all data messages received from the link layer and return credits to the link layer for these messages when the data is removed from the shared buffer. Other embodiments are described and claimed.

Abstract: Provided are methods of controlling digital image processing apparatus, in which a communication method may be transitioned to burst communication when an amount of data for communication with an external device is great, digital image processing apparatuses to which the methods are applied, and communication systems including the digital image processing apparatuses. In the methods, according to a type or a state of an external device or an operating state of the digital image processing apparatus, when an amount of data to be transmitted is large, burst communication may be performed, and if the amount of data is not as large, single communication may be performed.

Abstract: An input/output module for use in an industrial control system and connectable to a programmable logic controller (PLC), the input/output module having an interface configured for an electrical connection to the PLC, a plurality of pins configured for connection to one of a plurality of peripherals, an application specific integrated circuit (ASIC) disposed in the I/O module and electrically coupled to a system controller, the ASIC having a plurality of connection paths, each path being configured for a function, and a switch block configured to reassign a signal from a first connection path of the plurality of connection paths to a second connection path of the plurality of connection paths.

Abstract: One embodiment provides a data transfer device, including: a register configured to set an upper limit value for a transfer data size; and a transfer size controller configured to compare the upper limit value and the transfer data size sent from an external device, and to reduce the transfer data size when the transfer data size is larger than the upper limit value.

Abstract: A method handling a pluggable module selectable from a plurality of pluggable modules is executable at a media converter system of a network configuration. The method provides for automatically enabling of a disabled channel or disabling of an enabled channel of the media converter system when the pluggable module is attached to the media converter system, wherein the suggested channel enabling/disabling feature is executed on the basis of a correlation between module specific information extracted from the respective pluggable module and corresponding information extracted via the media converter system. An arrangement for executing the suggested method is also provided.

Abstract: An expandable wireless storage device is provided that includes an interface slot, internal memory, a wireless interface and an aggregated file system view providing component. An external memory, which stores a first subset of multi-media files, can be physically coupled with the expandable wireless storage device using the interface slot. A second subset of multi-media files can be stored on the internal memory. A multi-media file of the multi-media files can be streamed to a playing device using the wireless interface. The internal memory is used as a buffer when the multi-media file resides on the external memory. An aggregated file system view providing component provides an aggregated file system view of the multi-media files.

Abstract: When a data request signal is inactivated while a DMA controller is executing DMA data transfer in a burst transfer mode, an address at this time is held and a remaining number of transfer times is counted. After the DMA data transfer in the burst transfer mode is finished, the address and the remaining number of transfer times are re-set in the DMA controller and then the DMA data transfer is executed. This makes it possible to re-transfer data remaining at the timing when the data request signal is inactivated, and the DMA data transfer using the burst transfer mode is executed to or from a module requesting the DMA data transfer by using level of the data request signal.

Abstract: A data transfer method is provided which includes: sending a stream of data elements from a source to a sink (controlled by a common clock); simultaneously with the sending of the data element stream, sending a first binary signal to the sink, where the first binary signal is low if a data element is to be ignored by the sink, and is otherwise high; simultaneously with the sending of data element stream, sending a second binary signal from the sink to the source, where the second binary signal is low if the data element is not accepted by the sink, and is otherwise high; and simultaneously with the sending of the data element stream, sending a third binary signal to the sink, where the third binary signal marks a beginning and an end of a logical group of data elements within the data element stream.

Abstract: An apparatus for and method of processing a vertex in relation to 3 dimensional (3D) graphics pipeline are provided. According to the method, while a processor processes vertex data in units of batches, vertex data corresponding to a batch to be processed next is extracted and temporarily stored in a buffer independently of the processor. If the processor finishes processing of the current batch, the batch stored in the buffer is output so that the processor can immediately process the batch.

Abstract: A data transfer circuit includes a serial-to-parallel converter configured to convert multi-bit data inputted in series into parallel data by controlling the number of bits of the parallel data and a conversion timing based on an operation mode, and a data transmission unit configured to transfer the parallel data to a first data path or a second data path based on the operation mode.

Abstract: A processor. In response to requests from a processing section, first and second memory controllers transfer first and second data items to the processing section via first and second buses, respectively. When transfers of the data items are concurrently performed via the first and second buses, one of the data items is transferred to the processing section by the buffer controller, and the other of the data items is stored in the buffer by the buffer controller. Then, after termination of transfer of the one of the data items, the other data item is transferred from the buffer to the processing section by the buffer controller.

Abstract: A system and method for determining media to be exported out of a media library is described. In some examples, the system determines a media component to be exported, determines the media component is in the media library for a specific process, and exports the media component after the process is completed.