Abstract: A method of initiating re-enumeration of a USB device without manual intervention is provided. The method involves a sequence emulating detachment and re-attachment of a device to the host while the device remains attached to the host. As the device remains attached to the host throughout the sequence, the host OS is manipulated to receive a plurality of preset device states in order for it to perceive a device change and to eventually initiate device enumeration. The sequence, which involves a series of command exchanges between the device and the host, may be initiated by a software application residing in the host upon an event requiring device enumeration.

Abstract: Multiple data devices (A,B,C) are interfaced via a bus arbiter (S) with an external memory (F) so as to support burst-mode access by each device (A,B,C) one or more read registers (R1,R2,R3) are provided in the memory (F), and each register (R1,R2,R3) supports burst-mode access by a corresponding device (A,B,C). The arbiter (s) selects the register to be used following the initial access burst, according to the device requiring access. Thus, the memory (F) supports multiple burst-mode accesses in parallel.

Abstract: Systems and methods are disclosed for detecting a first device on a first bus issuing a read request for an amount of data to a second device on a second bus. The systems and methods further include detecting a bridge requesting a first portion of the data from the second device on behalf of the first device in response to the bridge receiving the read request, where the bridge couples the first bus to the second bus. In addition, the systems and methods include triggering the bridge to request an additional portion of the data on behalf of the first device.

Abstract: A first processor that executes at least one application or process includes a first interface module that interfaces the first processor to a second processor and that includes N interfaces. N is an integer greater than 1. The first processor also includes a first communication control module (CCM) that selects M of the N interfaces based on bandwidth requested by the at least one application to transmit data generated by the at least one application to the second processor.

Abstract: A bus system, which may prevent data from being incorrectly transferred when an early termination occurs during a burst mode, may include a bus, for example, an advanced high-performance bus (AHB), at least one bus master device, a bus arbiter and at least one transfer mode selection circuit. The at least one bus master device may generate a burst cycle control signal, a transfer start signal and a bus control request signal for requesting control of the bus, and may be activated in response to a bus control grant signal, so as to exchange data via the bus. The bus arbiter may generate the bus control grant signal in response to the bus control request signal and provide the bus control grant signal to the bus master device. The at least one transfer mode selection circuit may convert a burst mode into a single mode to generate a selection signal, when the bus control grant signal is deactivated before a burst mode operation is completed.

Abstract: A data transfer request of a data pro cessing device with respect to a synchronous memory is divided by a burst transfer length unit request dividing section into a plurality of data transfer requests in which a data transfer amount is an amount of data to be burst-transferred at a time and the data to be burst-transferred at a time is within a single memory bank. An assembling section assembles the divided data transfer requests into a plurality of new data transfer requests obtained by combining the divided data transfer requests, one for each memory bank. A data processing device can efficiently access continuous data stored in a plurality of memory banks, and is useful as a memory access control circuit of controlling an access operation of a data processing device with respect to a synchronous memory.

Abstract: The invention relates to a communication method and interface between a companion chip (CC) and a microcontroller (MC), a communication protocol being transmitted, having a first group of data (10) being drawn on for direct, non-real-time-critical access to the chip (CC), and a second group of data (20) based on which a real-time-critical access to the chip (CC) takes place, the data groups (10, 20) each comprising an operation code (OC), the length of which is shorter in the second data group (20) than in the first data group (10), and each data group (10, 20) being identifiable by the bit pattern of the operation code (OC).

Abstract: A USB device, integrated circuit, smart card and method are disclosed. A USB transceiver is connected to a data interface and operable at a respective low speed and full speed configuration. A processor as a USB device controller is operatively connected to the low speed USB transceiver and full speed USB transceiver and operable for transmitting a different device descriptor to a USB host for performing an enumeration depending on whether a low speed or high speed operation is chosen.

Abstract: A memory controller has a control unit receiving a transfer data from a transmission circuit and executing a burst transfer of the transfer data to a reception circuit. The transmission circuit transmits a first data of a first bit length for a first burst times by a burst transmission. The amount of the transfer data is equal to a product of the first bit length and the first burst times. The reception circuit receives a second data of a second bit length for a second burst times by a burst reception. When the amount of the first data received by the control unit becomes equal to or more than a product of the second bit length and the second burst times, the control unit transfers the received first data as the second data to the reception circuit, regardless of the number of the first data received by the control unit.

Abstract: A bus bridge between a high speed DMA bus and a lower speed peripheral bus sets a threshold for minimum available buffer space to send a read request dependent upon a frequency ratio and the DMA read latency. Similarly, a threshold for minimum available data for a write request depends on the frequency ratio and the DMA write latency. The bus bridge can store programmable values for the DMA read latency and write latency.

Abstract: The present apparatus and method control the flow of communication between a host and a data storage device. A plurality of data transport streams are maintained as active while a first burst of data for a first transport stream is initiated. The first burst is interrupted prior to the complete communication of the burst. The first transport stream is maintained as active and a first burst of data for a second transport stream is initiated. The first burst of the second transport stream is interrupted, the second transport stream is maintained as active and the method and apparatus return to continue the communication of the first burst of the first transport stream. Typically, a first stream ID is asserted prior to initiating the first burst of the first transport stream and a second stream ID is initiated prior to initiating the first burst of the second transport stream.

Abstract: An improved method, device and data processing system are presented. In one embodiment, the method includes a source device sending a request for a bus grant to deliver data to a data bus connecting a source device and a destination device. The device receives the bus grant and logic within the device determines whether the bandwidth of the data bus allocated to the bus grant will be filled by the data. If the bandwidth of the data bus allocated to the bus grant will not be filled by the data, the device appends additional data to the first data and delivers the combined data to the data bus during the bus grant for the first data. When the bandwidth of the data bus allocated to the bus grant will be filled by the first data, the device delivers only the first data to the data bus during the bus grant.

Abstract: Various methods and apparatus are described for a target with multiple channels. Address decoding logic is configured to implement a distribution of requests from individual burst requests to two or more memory channels making up an aggregate target. The address decoding logic implements a channel-selection hash function to allow requests from each individual burst request to be distributed amongst the two or more channels in a non-linear sequential pattern in channel round order that make up the aggregate target.

Abstract: A semiconductor memory device adapted to burst transmission is provided for improving flexibility of data write operation. The semiconductor memory device is composed of a memory array, a set of write registers, and an input buffer designed to sequentially receive a series of write data during a burst cycle, and to write the write data into the associated write registers. The device also includes a write release register containing a set of write release flags associated with the write registers, respectively, and a write release register controller asserting the associated write release flags in response to the write data being written into the associated write registers. The device also contains a write amplifier designed to concurrently write the write data contained in the write registers associated with the asserted write release flags, selectively, when the burst cycle is aborted in response to a control signal.

Abstract: A memory card controller is provided with a clock start/end control unit that suspends supply of a clock signal to the memory card when a data amount transferred from the memory card as a result of the transfer operation reaches a data amount specified by an nth command received from the host device. The memory card controller resumes supply of the clock signal to the memory card if a subsequent command received with supply of the clock signal to the SD card in a suspended state specifies an address consecutive to an end address of data transfer requested by the nth command as a start address.

Abstract: A method, apparatus and program storage device for managing dataflow through a processing system is disclosed. A buffer monitor maintains and monitors a buffer full threshold to control the write throughput to a data bus.

Abstract: A system and method for determining media to be exported out of a media library is described. In some examples, the system determines a media component to be exported, determines the media component is in the media library for a specific process, and exports the media component after the process is completed.

Abstract: Various apparatuses, methods and systems for specifying memory transaction sizes on a PCI bus are disclosed herein. For example, some embodiments of the present invention provide apparatuses for transferring data including a PCI bus, a memory map for memory transactions performed on the PCI bus, and at least one set of control registers adapted to establish at least one window within the memory map. The set of control registers contains an address range for the at least one window within the memory map and a burst transfer size for memory transactions taking place on the PCI bus that are addressed within the address range.

Abstract: Timing of a write and read strobes for a memory having a double data rate (DDR) interface are automatically adjusted using write-read operations. A first and a second value of the write and read strobes are determined for a first write-read operation having the read data match the write data. A second write-read operation is performed for each of a plurality of third values for the write strobe at the second value for the read strobe set. A center of the third values having the read data match the write data is determined. A third write-read operation is performed for each of a plurality of fifth values for the read strobe at the fourth value of the write strobe. A center of the fifth values having the read data match the write data is determined. The timing of the write and read strobes are set to the centers.

Abstract: A method, system and connector interface for transferring stored data between a media player and an accessory is disclosed. The method and system comprises obtaining by one of the media player and the accessory a unique identifier for a particular file stored in the other of the media player and the accessory; and returning the unique identifier with the stored file data to the one of the media player and the accessory. The system and method includes utilizing the stored file by the one of the media player or the accessory. In the method, system and connector interface in accordance with the present invention, accessories and media players are able to retrieve and store data utilizing an arbitrary format. This data is opaque to any protocol used by the media player and requires no parsing or interpretation. To provide this facility, a plurality of commands allows both media players and accessories to present a simple file system. The plurality of commands could be utilized in a variety of environments.

Abstract: One embodiment of the present invention includes a communication system. The system comprises a communications controller configured to control transmission and reception of communications data in a network. The system also comprises a memory configured to store configuration data associated with the communications controller and application parameters associated with each of a plurality of communications applications. The system further comprises an interface converter interconnecting the communications controller and the memory and configured to convert a first bus interface protocol associated with the communications controller to a second bus interface protocol for providing read and write data transfer of the configuration data and the application parameters between the communications controller and the memory.

Abstract: One or more external control pins and/or addressing pins on a memory device are used to set one or both of a burst length and burst type of the memory device.

Abstract: One or more external control pins and/or addressing pins on a memory device are used to set one or both of a burst length and burst type of the memory device.

Abstract: Skip logic is provided in a storage controller that informs a direct memory access (DMA) context list manager of consecutive ones and zeroes in a skip mask table. The DMA context list manager then manages data counters and location pointers based on the number of consecutive ones and the number of consecutive zeroes. For writes and non-cached reads, the number of zeroes is used to adjust a logical sector address without actually moving data. For cached reads, the number of zeroes is used to adjust the logical sector address and a host address pointer. The DMA context list manager also determines an instruction length based on a number of consecutive ones and issues one or more instructions for each group of consecutive ones and subtracts the instruction lengths from the overall transfer length until the transfer is complete.

Abstract: To include an address generating unit that generates a series of access destination addresses at a time of performing a burst access to the external memory, starting from an initial address to be accessed, so that number of inverted bits along with the address change becomes smallest, and a data processing unit that reads data held in a data holding unit and writes the data in an external memory in order of the access destination addresses, or reads data from the external memory in order of the access destination addresses and writes the data in the data holding unit.

Abstract: Disclosed is a method for controlling a memory in a mobile communication system. The method includes receiving certain frame control information by a Data Receiver Block (DRB) from a MAP decoder, forming a burst descriptor by the DRB by using the frame control information, and transferring the burst descriptor to a Low Medium Access Control (LMAC), and allocating a memory by the LMAC based on bursts according to the burst descriptor.

Abstract: When data is transferred to an access destination in a different endian format, a transfer start address is aligned based on a transfer bus width, and a transfer size is adjusted according to the transfer bus width and a transfer address. Thus, it becomes possible to perform burst transfer in the access destination. Accordingly, in the case where burst transfer to an access destination in a different endian format is performed with a smaller data width than a transfer bus width, an inconvenience where burst transfer can not be performed because an address is converted and data access is no longer an ascending order access can be prevented.

Abstract: A memory system is provided that supports partial cache line write operations to a memory module to reduce write data traffic on a memory channel. The memory system comprises a memory hub device integrated in the memory module and a set of memory devices coupled to the memory hub device. The memory hub device comprises burst logic integrated in the memory hub device. The burst logic determines an amount of write data to be transmitted to the set of memory devices and generates a burst length field corresponding to the amount of write data. The memory hub also comprises a memory hub controller integrated in the memory hub device. The memory hub controller controls the amount of write data that is transmitted using the burst length field. The memory hub device transmits the amount of write data that is equal to or less than a conventional data burst amount.

Abstract: An encoding method and an encoder for encoding data transmitted in a manner of bursts via a parallel bus and a decoding method and a decoder. The encoding method includes organizing data of the bursts into matrixes, determining for each of the matrixes whether a transform mode capable of decreasing the bus transition number exists, determining that the matrix needs to be transformed, determining a transform mode for transforming the matrix, and replacing the initial matrix with the transformed matrix. Then, forming a new matrix to be transmitted from matrixes which do not need to be transformed and matrixes which have been transformed. Thereafter, first generating a transform information word indicating transform states of the respective matrixes and then attaching the transform information word to the matrix to be transmitted to form an encoded matrix for actual transmission.

Abstract: A method of transmitting data to a recipient comprising the steps of dividing the data into a plurality of groups, providing a synchronising means for each of the groups, using the synchronising means to synchronise the data in each group, and transmitting the data to a recipient characterised in that the data is divided in accordance with its synchronisation requirements with the recipient.

Abstract: A digital signal processing system comprises a programmable processor (PROC) and a peripheral device (PD, MEM) coupled to the programmable processor via a burst generation device (BG). The processor is arranged to communicate with the peripheral device using a read operation and a write operation, respectively, on a single data element. The burst generation device (BG) groups a plurality of read operations or a plurality of write operations in a single burst read operation or a single burst write operation, respectively.

Abstract: Methods and apparatuses are described for a communication system. The communication system comprises an initiator core supporting a first burst capability as well as a target core supporting a second burst capability. The supported burst features of the second burst capability differ from the supported burst features of the first burst capability. The communication system also comprises an agent coupled to the initiator core, which comprises logic to compute target-dependent burst support information across multiple groups of potential targets at the same time. The logic then selects the correct target-dependent information based upon a resulting address decode for the target selection.

Abstract: The method and system for data transfer between the master device and the slave device through the bus are presented.

Abstract: A transmit offload engine (TOE) such as an intelligent network interface device (INIC), video controller or host bus adapter (HBA) that can communicate data over transport protocols such as Transport Control Protocol (TCP) for a host. Such a device can send and receive data for the host to and from a remote host, over a TCP connection maintained by the device. For sending data, the device can indicate to the host that data has been transmitted from the device to a network, prior to receiving, by the device from the network, an acknowledgement (ACK) for all the data, accelerating data transmission. The greatest sequence number for which all previous bytes have been ACKed can be provided with a response to a subsequent command, with the host maintaining a table of ACK values to complete commands when appropriate.

Abstract: A system and method for determining media to be exported out of a media library is described. In some examples, the system determines a media component to be exported, determines the media component is in the media library for a specific process, and exports the media component after the process is completed.

Abstract: Integrity of data stored in a memory space associated with a vehicle-based control system (such as a traction enhancement system) is verified through the use of sub-module checksums. A checksum for one or more subsystem modules is initially calculated based upon a checksum routine and the values of data residing in the portions of the memory space associated with the subsystem of interest. A global checksum is also initially calculated based upon data associated with the entire memory space. If the global checksum matches an expected value, the subsystem checksum(s) are stored as expected subsystem checksums. During subsequent operation, a second subsystem checksum is calculated and compared against the expected checksum value for the subsystem to verify the integrity of data residing within the memory space associated with the subsystem.

Abstract: A transfer control device is arranged between a bus and a bus interface. The transfer control device includes a bus connecting unit that is connected to plural signal lines of the bus, an interface connecting unit that is connected to plural signal lines of the bus interface, and a connection control unit that connects, when a defective signal line exists in the plural signal lines of the bus, a signal line corresponding to the defective signal line out of the plural signal lines of the bus interface and a signal line other than the defective signal line out of the plural signal lines of the bus.

Abstract: Multiple data transfer requests can be merged and transmitted as a single packet on a packetized bus such as a PCI Express (PCI-E) bus. In one embodiment, requests are combined if they are directed to contiguous address ranges in the same target device. An opportunistic merging procedure is advantageously used that merges a first request with a later request if the first request and the later request are mergeable and are received within a holdoff period that is dynamically determined based on a level of bus activity; otherwise, requests can be transmitted without merging.

Abstract: The present invention includes a method and device for controlling the data length of read and write operations performed on a memory device. The method includes determining a first number of channels available to a memory controller operatively coupled to the memory device; determining a second number representative of the number of populated channels; calculating a burst length based on the first and second numbers; and programming the memory controller to use the burst length as the data length of read and write operations performed on the memory device.

Abstract: Input/output processing is facilitated by readily enabling access to information associated with input/output processing. This information includes status information and measurement data provided by a control unit executing input/output commands. The status and measurement data are provided in a status control block identified in a transport control word, which is further used to specify a location in memory that includes the input/output commands to be executed.

Abstract: A memory system is provided that supports partial cache line write operations to a memory module to reduce write data traffic on a memory channel. The memory system comprises a memory hub device integrated in the memory module and a set of memory devices coupled to the memory hub device. The memory hub device comprises burst logic integrated in the memory hub device. The burst logic determines an amount of write data to be transmitted to the set of memory devices and generates a burst length field corresponding to the amount of write data. The memory hub also comprises a memory hub controller integrated in the memory hub device. The memory hub controller controls the amount of write data that is transmitted using the burst length field. The memory hub device transmits the amount of write data that is equal to or less than a conventional data burst amount.

Abstract: A memory system is provided that supports partial cache line read operations to a memory module to reduce read data traffic on a memory channel. The memory system comprises a memory hub device integrated in the memory module and a set of memory devices coupled to the memory hub device. The memory hub comprises burst logic integrated in the memory hub device. The burst logic determines an amount of read data to be transmitted from the set of memory devices and generates a burst length field corresponding to the amount of read data. The memory hub also comprises a memory hub controller integrated in the memory hub device. The memory hub controller controls the amount of read data that is transmitted using the burst length field. The memory hub device transmits the amount of read data that is equal to or less than a conventional data burst amount of data.

Abstract: A method is provided that supports partial cache line read and write operations to a memory module to reduce read and write data traffic on a memory channel. In a memory hub controller integrated in the memory module determines an amount of data to be transmitted to or from a set of memory devices of the memory module, in responsive to an access request. The memory hub controller generates a burst length field corresponding to the amount of data. The memory controller controls the amount of data that is transmitted to or from the memory devices using the burst length field. The amount of data is equal to or less than a standard data burst amount of data for the set of memory devices.

Abstract: Input/output processing is facilitated by reducing communications between input/output communications adapters and control units during input/output processing. The number of exchanges and sequences between an input/output communications adapter and control unit is reduced by sending a plurality of commands from the adapter to the control unit as a single entity for execution by the control unit. The control unit executes the commands and provides the data, if any, in one sequence. The control unit relieves the adapter of the responsibility of tracking state of the individual commands and is able to calculate precise measurement data relating to execution of the commands.

Abstract: Methods and apparatuses are described for a communication system. The communication system may include one or more initiator agents, where each agent couples to its own Intellectual Property core. The communication system may also include two or more target agents, where each agent couples to its own Intellectual Property core. The communication system may also include an interconnect using an end-to-end width conversion mechanism. The conversion mechanism converts data widths between the initiator agent and a first target agent. Two or more branches of pathways in the interconnect exist between the initiator agent and the two or more target agents. The conversion mechanism to use a lookup table that includes data width information of the initiator agent and the two or more branches of pathways to the two or more target agents to concurrently pre-compute width conversion signals for each of the target agent branches.

Abstract: A DMA transfer control device for controlling a DMA transfer between a source and a destination is provided. The DMA transfer control device has: a buffer in which a transfer data is stored; and a bus cycle generation unit performing a burst transfer of the transfer data between the buffer and the source or the destination. The bus cycle generation unit performs an undefined-length burst transfer until an access address reaches a burst address boundary in the source or the destination. The bus cycle generation unit performs a fixed-length burst transfer after the undefined-length burst transfer until transfer of the transfer data is completed.

Abstract: A method and apparatus in a data controller in a storage drive for retrieving, evaluating, and processing a context that describes a direct memory access (DMA) request. The data controller includes a buffer for storing data transferred in response to execution of a DMA transfer request, a host address pointer pointing to a current location in the buffer, and a retrieval channel device. The retrieval channel device is configured to: fetch a context that describes a DMA transfer requested by a host computer, determine whether a current capacity of the buffer for transferring data exceeds a threshold, generate an instruction to transfer a second amount of data to complete at least a portion of the requested DMA transfer if the current capacity does exceed the threshold, assert the instruction generated by the retrieval channel device, and adjust the host address pointer by the second amount of data.

Abstract: A bus system, which may prevent data from being incorrectly transferred when an early termination occurs during a burst mode, may include a bus, for example, an advanced high-performance bus (AHB), at least one bus master device, a bus arbiter and at least one transfer mode selection circuit. The at least one bus master device may generate a burst cycle control signal, a transfer start signal and a bus control request signal for requesting control of the bus, and may be activated in response to a bus control grant signal, so as to exchange data via the bus. The bus arbiter may generate the bus control grant signal in response to the bus control request signal and provide the bus control grant signal to the bus master device. The at least one transfer mode selection circuit may convert a burst mode into a single mode to generate a selection signal, when the bus control grant signal is deactivated before a burst mode operation is completed.

Abstract: An object of the invention is to provide a transfer system, initiator device, and data transfer method that can improve data transfer-related performance by fully utilizing a high-speed interface even when transferring data between devices that execute data processing at different speed. The invention provides a transfer system including: an initiator device, plural target devices, and a switch for switching data transfer targets between the initiator device and target devices, wherein either the initiator device or the target devices are connected to the switch via a high-speed interface and the other is connected to the switch via a low-speed interface, and the initiator device has a control unit for determining the data transfer length of data transferred to a first target device in the target devices according to the status of data transfer to the other target device(s) when transferring data between the initiator device and the first target device.

Abstract: Apparatus and method for providing information to a cache module, the apparatus includes: (i) at least one processor, connected to the cache module, for initiating a first and second requests to retrieve, from the cache module, a first and a second data unit; (ii) logic, adapted to receive the requests and determine if the first and second data units are mandatory data units; and (iii) a controller, connected to the cache module, adapted to initiate a single fetch burst if a memory space retrievable during the single fetch burst comprises the first and second mandatory data units, and adapted to initiate multiple fetch bursts if a memory space retrievable during a single fetch burst does not comprise the first and the second mandatory data units.