Burst Data Transfer Patents (Class 710/35)
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Patent number: 8635386Abstract: A communication control device includes reception controllers capable of receiving data in a burst transfer mode in which packets are continuously transferred as one burst. There are dedicated buffers having a capacity of one packet for each of a plurality of endpoints and common buffers shared by the endpoints; a first packet of a burst transfer is stored in the dedicated buffer; and a common buffer is secured at the same time. The dedicated buffers and common buffers are controlled according to a transfer status.Type: GrantFiled: May 11, 2011Date of Patent: January 21, 2014Assignee: Renesas Electronics CorporationInventor: Fumio Takahashi
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Patent number: 8621100Abstract: A system improves bandwidth used by a data stream. The system receives data from the data stream and partitions the data into bursts. At least one of the bursts includes one or more idles. The system selectively removes the idles from the at least one burst and transmits the bursts, including the at least one burst.Type: GrantFiled: February 27, 2009Date of Patent: December 31, 2013Assignee: Juniper Networks, Inc.Inventors: Sharada Yeluri, Kevin Clark, Shahriar Ilislamloo, Chung Lau
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Patent number: 8583841Abstract: A video relay circuit is provided including an input channel to receive input video data packets; a first circuit to convert the input video data packets into data for a display device; a second circuit coupled to the first circuit to retime, recondition and re-drive the data channels; an output channel to couple the video data packets into an output stream. Also provided is a video data transmission link including a video relay circuit as above and a daisy chain of video display devices including a video source; a plurality of video display devices wherein a first video display device is coupled to the source of video data, and each further video display device receives the source signal from the previous display and provides the video signal to the next display; wherein at least one of the video display devices comprises a video relay circuit as above.Type: GrantFiled: October 15, 2010Date of Patent: November 12, 2013Assignee: Synaptics IncorporatedInventors: Henry Zeng, Ji Park
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Patent number: 8560742Abstract: A method of providing one or more computing devices with access to a plurality of resources. The plurality of resources are provided by at least one physical device. The method comprises, at a first control element receiving a data packet transmitted by one of said one or more computing devices, and determining whether said data packet comprises a command including a first logical identifier identifying one of said resources. If it is determined that said data packet comprises a command including a first logical identifier a second logical identifier is obtained, the second logical identifier being associated with said first logical identifier and identifying said one of said resources. A request including said second logical identifier is transmitted to a second control element, the second control element being arranged to identify a physical device associated with said second logical identifier and to forward said request to the identified physical device.Type: GrantFiled: June 9, 2009Date of Patent: October 15, 2013Assignee: Virtensys LimitedInventor: Yves Constantin Tchapda
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Patent number: 8539118Abstract: A system and method for determining media to be exported out of a media library is described. In some examples, the system determines a media component to be exported, determines the media component is in the media library for a specific process, and exports the media component after the process is completed.Type: GrantFiled: June 27, 2012Date of Patent: September 17, 2013Assignee: CommVault Systems, Inc.Inventors: Rajiv Kottomtharayil, Manoj K. Vijayan Retnamma
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Patent number: 8516167Abstract: A system includes master modules, at least one multiport slave module, and a scheduler connected by a system bus. The scheduler is configured to provide scheduling information to the multiport slave module. The scheduling information includes master categorization information and anticipated burst information. The anticipated burst information is based on a scheduler determination for an anticipated bus access by an anticipated master module. The master categorization information categorizes the anticipated master.Type: GrantFiled: August 3, 2011Date of Patent: August 20, 2013Assignee: Atmel CorporationInventor: Franck Lunadier
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Patent number: 8510482Abstract: In a data processing system having a processor, a DMA controller, a peripheral, and a memory, a method includes initiating a DMA transfer between the peripheral and the memory, wherein the DMA transfer comprises N subsets of data to be transferred between the peripheral and the memory, N having a value of two or more; asserting, by the peripheral, an event status indicator each time an event is completed by the peripheral; in response to each assertion of the event status indicator, the peripheral, based on a data request enable signal from the DMA controller, performing one of asserting a data request signal provided to the DMA controller or providing an interrupt request to the processor; and in response to each assertion of the data request signal, the DMA controller initiating transfer of a next subset of data of the N subsets of data between the memory and the peripheral.Type: GrantFiled: April 27, 2010Date of Patent: August 13, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Joseph C. Circello, John D. Mitchell, Sheilah C. Phan
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Patent number: 8478935Abstract: A path controller controls a plurality of paths, including switching between those paths in response to an error notice. Upon detection of a path connection timeout at the path controller, a target driver submits an I/O abort request to a disk array device. The target driver also forwards an error notice to the path controller when it is received. A Fiber Channel driver controls a Fiber Channel adapter. In response to an I/O abort request submitted by the target driver, the Fiber Channel driver blocks every operation on the disk array device, as well as sending an error notice to the target driver.Type: GrantFiled: March 25, 2009Date of Patent: July 2, 2013Assignee: Fujitsu LimitedInventor: Kazushige Kurokawa
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Patent number: 8473673Abstract: Systems, methodologies, media, and other embodiments associated with (de)compressing data at a time and in a location that facilitates increasing memory transfer bandwidth by selectively controlling a burst-mode protocol used to transfer data to and/or from a memory are described. One exemplary system embodiment includes a memory controller configured to (de)compress memory, to manipulate size data associated with compressed data, and to selectively manipulate a burst-mode protocol employed in transferring compressed data to and/or from random access memory.Type: GrantFiled: June 24, 2005Date of Patent: June 25, 2013Assignee: Hewlett-Packard Development Company, L.P.Inventors: Blaine Douglas Gaither, Russ Herrell, Judson Eugene Veazey
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Patent number: 8463956Abstract: In a data transfer control apparatus, a transfer start address and a transfer size are acquired from a peripheral circuit. A command is issued in response to an activation signal from the peripheral circuit. When data transfer is performed between the main memory unit and the peripheral circuit, completion of issuance of all of commands corresponding to the transfer start address and transfer size is detected. The transfer size is retained until the end of data transfer. A next command is issued prior to completion of data transfer for one command, and a next activation signal is received upon detection of completion of issuance of all of the commands corresponding to the one transfer start address and transfer size. Next transfer start address and transfer size are acquired upon detection of completion of issuance of all of the commands corresponding to the one transfer start address and transfer size.Type: GrantFiled: March 2, 2011Date of Patent: June 11, 2013Assignee: Ricoh Company, Ltd.Inventor: Atsushi Kawata
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Patent number: 8438320Abstract: Various methods and apparatus are described for a target with multiple channels. Address decoding logic is configured to implement a distribution of requests from individual burst requests to two or more memory channels making up an aggregate target. The address decoding logic implements a channel-selection hash function to allow requests from each individual burst request to be distributed amongst the two or more channels in a non-linear sequential pattern in channel round order that make up the aggregate target.Type: GrantFiled: October 5, 2009Date of Patent: May 7, 2013Assignee: Sonics, Inc.Inventors: Krishnan Srinivasan, Drew E. Wingard, Chien-Chun Chou
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Patent number: 8412891Abstract: Memory access arbitration allowing a shared memory to be used both as a memory for a processor and as a buffer for data flows, including an arbiter unit that makes assignment for access requests to the memory sequentially and transfers blocks of data in one round-robin cycle according to bandwidths required for the data transfers, sets priorities for the transfer blocks so that the bandwidths required for the data transfers are met by alternate transfer of the transfer blocks, and executes an access from the processor with an upper limit set for the number of access times from the processor to the memory in one round-robin cycle so that the access from the processor with the highest priority and with a predetermined transfer length exerts less effect on bandwidths for data flow transfers in predetermined intervals between the transfer blocks.Type: GrantFiled: November 1, 2010Date of Patent: April 2, 2013Assignee: International Business Machines CorporationInventors: Masayuki Demura, Hisato Matsuo, Keisuke Tanaka
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Patent number: 8412855Abstract: Systems and methods of processing write transactions provide for combining write transactions on an input/output (I/O) hub according to a protocol between the I/O hub and a processor. Data associated with the write transactions can be flushed to an I/O device without the need for proprietary software and specialized registers within the I/O device.Type: GrantFiled: January 19, 2010Date of Patent: April 2, 2013Assignee: Intel CorporationInventors: Kenneth C. Creta, Aaron T. Spink, Lance E. Hacking, Sridhar Muthrasanallur, Jasmin Ajanovic
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Patent number: 8412902Abstract: In a signal processor including storage sections, a start address for starting output of data from an external memory, is input from an external controller to the start address input section. The signal output section outputs a start signal based on a download start instruction from the external controller, and outputs an end signal when download is completed. The output instruction section outputs, based on the start signal, to the external memory a data output instruction of download data for a designated storage section, starting from the start address, and stops output of the data output instruction based on the end signal. The write instruction section outputs a write instruction to the storage sections that allows data writing only to the designated storage section, and the download data is written to the designated storage section when the start signal is input to the output instruction section.Type: GrantFiled: December 22, 2009Date of Patent: April 2, 2013Assignee: Oki Semiconductor Co., Ltd.Inventor: Kazutoshi Inoue
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Patent number: 8397233Abstract: A device includes an input processing unit and an output processing unit. The input processing unit dispatches first data to one of a group of processing engines, records an identity of the one processing engine in a location in a first memory, reserves one or more corresponding locations in a second memory, causes the first data to be processed by the one processing engine, and stores the processed first data in one of the locations in the second memory. The output processing unit receives second data, assigns an entry address corresponding to a location in an output memory to the second data, transfers the second data and the entry address to one of a group of second processing engines, causes the second data to be processed by the second processing engine, and stores the processed second data to the location in the output memory.Type: GrantFiled: May 23, 2007Date of Patent: March 12, 2013Assignee: Juniper Networks, Inc.Inventors: Raymond Marcelino Manese Lim, Stefan Dyckerhoff, Jeffrey Glenn Libby, Teshager Tesfaye
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Publication number: 20130060974Abstract: A memory stores data generated by a processor and a transferring unit burst transfers the data from the memory unit to a processing unit. Based on an access capability of the processor when accessing the memory, a prescribed value for a burst width and information concerning the time that the processing unit consumes to process the data are set in advance at the data transferring apparatus. When the transferring unit performs data transfer, the time allowed for data transfer is calculated based on the information concerning the time that the processing unit consumes to process the data, and the burst width is determined as a value greater than or equal to the prescribed value for the burst width and is as close as possible to the prescribed value for the burst width within a range in which data transfer can be finished within the allowed time.Type: ApplicationFiled: September 21, 2012Publication date: March 7, 2013Applicant: FUJITSU LIMITEDInventor: FUJITSU LIMITED
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Patent number: 8392689Abstract: In one embodiment, a data storage device comprises a buffer, a buffer manager, and a buffer client. The buffer client is configured to receive data to be stored in the buffer, to compute a difference between a bank boundary address of the buffer and a starting buffer address for the data, to generate a first data burst having a length equal to the computed difference and including a first portion of the data, and to send the first data burst to the buffer manager, wherein the buffer manager is configured to write the first data burst to the buffer.Type: GrantFiled: May 24, 2010Date of Patent: March 5, 2013Assignee: Western Digital Technologies, Inc.Inventor: Glenn A. Lott
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Patent number: 8364864Abstract: A network device includes a main storage memory and a queue handling component. The main storage memory includes multiple memory banks which store a plurality of packets for multiple output queues. The queue handling component controls write operations to the multiple memory banks and controls read operations from the multiple memory banks, where the read operations for at least one of the multiple output queues alternates sequentially between the each of the multiple memory banks, and where the read operations and the write operations occur during a same clock period on different ones of the multiple memory banks.Type: GrantFiled: March 17, 2010Date of Patent: January 29, 2013Assignee: Juniper Networks, Inc.Inventors: Anurag Agrawal, Philip A. Thomas
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Publication number: 20130007308Abstract: One embodiment provides a data transfer device, including: a register configured to set an upper limit value for a transfer data size; and a transfer size controller configured to compare the upper limit value and the transfer data size sent from an external device, and to reduce the transfer data size when the transfer data size is larger than the upper limit value.Type: ApplicationFiled: February 29, 2012Publication date: January 3, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Takeshi KIKUCHI
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Patent number: 8341322Abstract: A device and a method, the device has transaction scheduling capabilities, and includes: (i) a memory unit adapted to output data at a first data rate, (ii) a data transaction initiator adapted to receive data at a second data rate that is lower than the first data rate; (iii) a deep pipelined crossbar characterized by a latency; and (iv) a data rate converter connected between the deep pipelined crossbar and the data transaction initiator; wherein the data rate converter is adapted to schedule a transaction of data unit from the memory unit in response to the latency of the deep pipelined crossbar, the first data rate, the second data rate, and size of an available storage space, within the data rate converter allocated for storing data from the memory unit.Type: GrantFiled: March 7, 2007Date of Patent: December 25, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Dror Gilad, Ori Goren, Alon Shoshani
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Patent number: 8332550Abstract: A method of operating an input/output interface is described. The method comprises eliminating a current path into an output pin of an input/output interface while the input/output interface receives an operational power signal during a first mode of operation; and enabling the current path into the output pin of the input/output interface to limit a voltage magnitude externally applied to the output pin of the input/output interface during a second mode of operation.Type: GrantFiled: August 30, 2010Date of Patent: December 11, 2012Assignee: Xilinx, Inc.Inventors: Phillip A. Young, Honggo Wijaya
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Patent number: 8321605Abstract: Techniques are disclosed relating to detecting and interjecting a programmed input/output (PIO) operation into a direct memory access (DMA) operation. In one embodiment, an integrated circuit may include a DMA controller that may contain a control circuit, a DMA unit, and a PIO unit. The control circuit may be configured to detect a pending PIO operation during a DMA operation and interject the PIO operation onto a shared path during the same clock cycle as or the first clock cycle following the detection of the pending PIO operation. The DMA operation may consist of multiple single-clock-cycle beats. In one embodiment, a PIO operation may be interjected onto the shared path between beats of a DMA operation, on consecutive clock cycles. At the next clock cycle following the PIO operation, the control circuit may resume the next beat of the DMA operation.Type: GrantFiled: December 13, 2010Date of Patent: November 27, 2012Assignee: Apple Inc.Inventors: Joseph P. Bratt, Lakshmi Rao
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Patent number: 8307192Abstract: A system and related method of operation for migrating the memory of a virtual machine from one NUMA node to another. Once the VM is migrated to a new node, migration of memory pages is performed while giving priority to the most utilized pages, so that access to these pages becomes local as soon as possible. Various heuristics are described to enable different implementations for different situations or scenarios.Type: GrantFiled: October 11, 2011Date of Patent: November 6, 2012Assignee: VMware, Inc.Inventors: Vivek Pandey, Ole Agesen, Alexander Thomas Garthwaite, Carl A. Waldspurger, Rajesh Venkatasubramanian
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Patent number: 8285892Abstract: An apparatus comprising an arbiter circuit, a protocol engine circuit and a channel router circuit. The arbiter circuit may be configured to determine a winning channel from a plurality of channel requests based on a first criteria. Each of the plurality of channel requests may represent a burst of data having a fixed length aligned to an address boundary of a memory. The protocol engine circuit may be configured to receive a signal from the arbiter circuit indicating the winning channel. The protocol engine circuit may also be configured to perform a memory protocol at a granularity equal to the burst of data. The channel router circuit may be configured to present the plurality of channel requests to the arbiter circuit and the protocol engine circuit.Type: GrantFiled: August 17, 2010Date of Patent: October 9, 2012Assignee: LSI CorporationInventors: Eskild T. Arntzen, Sheri L. Fredenberg, Jackson L. Ellis, Robert W. Warren
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Patent number: 8281052Abstract: A microprocessor system having a microprocessor and a double data rate memory device having separate groups of external pins adapted to receive addressing, data, and control information and a memory controller adapted to set a burst type of the double data rate memory to interleaved or sequential by sending a signal through one of the external pins of the double data rate memory device, such that when a read command is sent by the controller, depending on the burst type set, the double data rate memory device returns interleaved or sequentially output data to the memory controller.Type: GrantFiled: April 9, 2012Date of Patent: October 2, 2012Assignee: Round Rock Research, LLCInventor: Christopher S. Johnson
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Patent number: 8275921Abstract: A method of accessing data in a device comprising: a first integrated circuit having a processor, a memory connected to the processor and a direct memory access engine operatively coupled to the memory and to the microprocessor; a second integrated circuit comprising storage means for holding data values in respective locations, the second integrated circuit being connected to the first integrated circuit via a serial link, the method comprising: the processor generating a plurality of memory access requests independent from one another and supplying a bundle of said independent memory access requests to the direct memory access engine, each memory access request comprising an address of a storage location in the storage means; the direct memory access engine sequentially supplying the memory access requests via the serial link to the second integrated circuit; the second integrated circuit returning a data value responsive to each memory access request and appending to the data value said address of the locaType: GrantFiled: April 17, 2009Date of Patent: September 25, 2012Assignee: Icera Inc.Inventors: Andy Bond, Chris Goodings
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Publication number: 20120221750Abstract: A data transfer circuit includes a serial-to-parallel converter configured to convert multi-bit data inputted in series into parallel data by controlling the number of bits of the parallel data and a conversion timing based on an operation mode, and a data transmission unit configured to transfer the parallel data to a first data path or a second data path based on the operation mode.Type: ApplicationFiled: December 19, 2011Publication date: August 30, 2012Inventors: Hyoung-Jun Na, Jae-Il Kim
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Patent number: 8244930Abstract: A first node includes a DMA engine for transferring data specified by a sequence of control blocks to a second node. When a control block does not require synchronization between memories, the DMA engine sends an end of transfer (EOT) message after the last datum, increments an EOT counter, and processes the next control block. When a control block requires synchronization and the EOT counter is at zero, the DMA engine sends an EOT with a flag after the last datum, increments the EOT counter, and waits for the EOT counter to return to zero before processing the next control block. A memory controller at the second node detects the EOT with or without a flag and generates an EOT acknowledgement with or without a flag. When a link interface at the second node detects the EOT acknowledgement with a flag, it sends an interrupt to a local processor complex.Type: GrantFiled: May 5, 2010Date of Patent: August 14, 2012Assignee: Hewlett-Packard Development Company, L.P.Inventors: Greg L. Dykema, David H. Bassett, Joel L. Lach
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Patent number: 8234417Abstract: A system and method for determining media to be exported out of a media library is described. In some examples, the system determines a media component to be exported, determines the media component is in the media library for a specific process, and exports the media component after the process is completed.Type: GrantFiled: December 17, 2010Date of Patent: July 31, 2012Assignee: CommVault Systems, Inc.Inventors: Rajiv Kottomtharayil, Manoj K. Vijayan Retnamma
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Patent number: 8225063Abstract: A memory interface allows access to SDRAM by receiving a column address for a data read or write of a burst of data units. Each data unit in the burst has an expected bit size. The interface generates n (n>1) column memory addresses from the received column address. The interface accesses the synchronous dynamic memory to read or write n bursts of data at the n column memory addresses. Preferably, the SDRAM is clocked at n times the rate of the interconnected memory accessing device, and the memory units. The data units in the n bursts preferably have one nth the expected bit size. In this way, SDRAM may be accessed with high memory bandwidth, without requiring an increase in the size of data units in the SDRAM, and the associated data bus. Conveniently, the interface may be operable in two separate modes or configurations. In one mode, SDRAM may be accessed through the interface in a conventional manner. In the second mode, SDRAM is accessed in multiple bursts for each received burst access.Type: GrantFiled: June 8, 2009Date of Patent: July 17, 2012Assignee: ATI Technologies ULCInventor: Richard K. Sita
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Patent number: 8200864Abstract: Transfer of data blocks between a host and a multi-media card (“MMC”) are performed in a pre-defined mode. In pre-defined mode, the host sets a pre-determined number of blocks, a “multiblock,” to be transferred. Use of pre-defined mode results in faster transfers than those performed using an open-ended mode incorporating a stop command. Furthermore, corruption errors resulting from delays in providing the stop command which may occur in an open-ended mode are avoided. Pre-defined multiblock transfers are supported by existing operating systems through trapping open-ended mode transfers in the MMC stack, leaving existing device drivers unaffected.Type: GrantFiled: March 2, 2010Date of Patent: June 12, 2012Assignee: Amazon Technologies, Inc.Inventors: Manish Lachwani, David Berbessou
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Patent number: 8195847Abstract: A storage control apparatus for transmitting data to and receiving data from a plurality of storage devices connected to the same interface, the storage control apparatus includes a memory configured to store a management table registering a burst transfer length of each of the plurality of storage devices, the plurality of storage devices including a first storage device having a first burst transfer length that is a minimum in the management table and a second device having a second burst transfer length; an adjusting controller configured to adjust the second burst transfer length in input and/or output processing if the second burst transfer length registered in the management table is different from the first burst transfer length; and a data transfer controller configured to issue a command for a data transfer to the second storage device on the basis of the adjusted second burst transfer length.Type: GrantFiled: March 16, 2011Date of Patent: June 5, 2012Assignee: Fujitsu LimitedInventors: Yuichi Ogawa, Tsukasa Makino, Tomoaki Tsuruta, Hiroaki Ochi, Marie Abe, Naohiro Takeda
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Patent number: 8180908Abstract: A business-to-vehicle platform functions as an information technology (IT) integration platform to support secure communication between a vehicle's onboard IT system and any offboard third-party IT system. In one embodiment, the a vehicle's communication hub is decoupled from all voice and data traffic to/from third-party service providers, such that the vehicles will “look and feel” like standard business IT devices to the third-party service providers. In certain embodiments, this decoupling enables the use of standardized business IT services in vehicles, rather than the traditional approach of requiring vehicle-specific embedded services.Type: GrantFiled: August 14, 2007Date of Patent: May 15, 2012Assignee: Bayerische Motoren Werke AktiengesellschaftInventors: Peter Zoller, Andreas Fritsch, Jens Peter Weiss, Klaus Kastenmeier
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Patent number: 8171186Abstract: A method for performing write transactions in an interconnect fabric is described. A burst write transaction is received by a bridge coupled to a master. The burst transaction is initiated by a command phase that includes a wait state attribute. The bridge is also coupled to a second bus that is coupled to a slave destination device or to another bridge. The bridge may initiate a cut-through transaction to the second bus when the wait state attribute indicates a master inserted wait state will not be incurred during the burst transaction.Type: GrantFiled: January 31, 2011Date of Patent: May 1, 2012Assignee: Texas Instruments IncorporatedInventors: Brian Jason Karguth, Denis Roland Beaudoin, Akila Subramaniam
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Patent number: 8159708Abstract: A graphic-drawing processing unit performs a rendering process of print data with respect to a band memory or a page memory. When there is a rendering engine that performs a memory access using a memory word width as a minimum unit as a rendering environment, an arbitrary-word-width drawing unit is configured to access an arbitrary-word-width having an arbitrary height, and a one-word width-limited drawing unit is configured to access a limited one-word width having an arbitrary height. The graphic-drawing processing unit performs a drawing process by switching the arbitrary-word-width drawing unit and the one-word-width-limited drawing unit as appropriate.Type: GrantFiled: April 27, 2007Date of Patent: April 17, 2012Assignee: Ricoh Company, Ltd.Inventor: Mikiya Ichikawa
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Patent number: 8156262Abstract: One or more external control pins and/or addressing pins on a memory device are used to set one or both of a burst length and burst type of the memory device.Type: GrantFiled: August 18, 2011Date of Patent: April 10, 2012Assignee: Round Rock Research, LLCInventor: Christopher S. Johnson
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Patent number: 8140713Abstract: A computer program product, apparatus, and method for facilitating input/output processing of a processing environment are provided.Type: GrantFiled: November 15, 2010Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: Daniel F. Casper, John R. Flanagan
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Publication number: 20120066434Abstract: A memory controller is provided. In response to a burst read command that includes a target address, the memory controller provides, to one or more busses, data stored in memory at the target address after dummy clock cycles have occurred. The memory controller also provides a preamble on the bus(ses) during some of the dummy clock cycles. The preamble includes a data training pattern.Type: ApplicationFiled: September 10, 2010Publication date: March 15, 2012Applicant: Spansion LLCInventor: Clifford Alan ZITLAW
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Patent number: 8108571Abstract: A channel-less system and method are provided for multithreaded communications with a direct memory access (DMA) controller. The method accepts a plurality of DMA command messages directed to a fixed port address. The DMA command messages are arranged in a first-in first-out (FIFO) queue, in the order in which they are received. The DMA command messages are supplied to a DMA controller from the FIFO queue, and in response to the DMA command message, data transfer operation are managed by the DMA controller. Following the completion of each data transfer operation, a transfer complete message indicating completion is sent. In one aspect, DMA command messages are arranged in a plurality of parallel FIFO queues, and CD sets are stored in a plurality of context memories, where each context memory is associated with a corresponding FIFO queue.Type: GrantFiled: September 17, 2010Date of Patent: January 31, 2012Assignee: Applied Micro Circuits CorporationInventor: Daniel L. Bouvier
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Patent number: 8103814Abstract: An electronic apparatus to allow data to be sent and received between a master unit and a slave unit through a peripheral component interconnect (PCI) bus is provided. Each of the master unit and the slave unit comprises a data interface having a plurality of pins through which request data is sent to and received from an external device, and additional pins through which size information of the request data is sent to and received from the external device. If the master unit sends address information and the size information of the request data to the slave unit through the plurality of pins and the additional pins, the slave unit processes data of an address corresponding to the received address information according to size corresponding to the size information.Type: GrantFiled: February 29, 2008Date of Patent: January 24, 2012Assignee: Samsung Electronics Co., Ltd.Inventor: Kyu-sung Kim
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Publication number: 20110302336Abstract: In an embedded system, there are a plurality of data requesting devices, a plurality of data sources and a bus fabric interconnecting the data requesting devices and the data sources, wherein the bus fabric comprises a plurality of bus components. Some or all of the data sources and arbitration devices associated with the bus components resolve contentions between data bursts by selecting a first one of the contending data bursts; determining a length of a critical section of the first selected data burst; and processing the critical section of the selected data burst. Then, a second one of the contending data bursts is selected, a length of a critical section of the second selected data burst is determined, and the critical section of the second selected data burst is processed before a non-critical section of the selected data burst.Type: ApplicationFiled: December 19, 2008Publication date: December 8, 2011Applicant: ST-ERICSSON SAInventor: Rowan Nigel Naylor
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Patent number: 8073992Abstract: There are provided a transfer request module 2 for interpreting a data transfer request received from outside; a transfer instruction module 1 including a receiving section 10 for receiving the data transfer request after interpretation by the transfer request module 2, a remaining data setting section 12 for setting a data volume to be transferred in accordance with the data transfer request after the interpretation the receiving section 10 receives, a remaining data retaining section 16 for holding the data volume set by the remaining data setting section 12, a remaining data reading section 13 for reading the data volume held in the remaining data retaining section 16, a counter setting section 14 for setting a limit of the number of times of transfer unit settings in accordance with the data transfer request after the interpretation the receiving section 10 receives, a counter 17 for holding the limit of the number of times of the settings carried out by the counter setting section 14 and for counting dowType: GrantFiled: June 23, 2008Date of Patent: December 6, 2011Assignee: Mitsubishi Electric CorporationInventor: Ryou Yoshii
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Patent number: 8072996Abstract: The present invention is a method and apparatus to buffer data. A buffer memory of a first type stores data associated with a connection identifier corresponding to a channel in a network. The data is organized into at least one chunk based on a linked list. The connection identifier identifies a connection in the channel. The data is part of a data stream associated with the connection. A packet memory of a second type provides access to the stored data when a transfer condition occurs.Type: GrantFiled: October 25, 2007Date of Patent: December 6, 2011Assignee: The United States of America as represented by the Secretary of the NavyInventor: Tam-Anh Chu
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Publication number: 20110289243Abstract: A communication control device includes reception controllers capable of receiving data in a burst transfer mode in which packets are continuously transferred as one burst. There are dedicated buffers having a capacity of one packet for each of a plurality of endpoints and common buffers shared by the endpoints; a first packet of a burst transfer is stored in the dedicated buffer; and a common buffer is secured at the same time. The dedicated buffers and common buffers are controlled according to a transfer status.Type: ApplicationFiled: May 11, 2011Publication date: November 24, 2011Inventor: Fumio TAKAHASHI
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Patent number: 8065448Abstract: A DMA control system includes: a plurality of DMA control units that are controlled in a manner that, while one of the plurality of DMA control units use a transmission path, the other DMA control units other than the one of the plurality of DMA control unit are prevented from using the transmission path; and a transfer instruction unit that defines transfer amounts of DMA transfers for the respective DMA control units and gives transfer instructions thereto. The transfer instruction unit, when the transfer instruction unit gives a transfer instruction to a first DMA control unit of the plurality of the DMA control units, defines a transfer amount for the first DMA control unit and gives the transfer instruction thereto in accordance with a state of utilizing a second DMA control units of the plurality of the DMA control units.Type: GrantFiled: November 26, 2008Date of Patent: November 22, 2011Assignee: Fuji Xerox Co., Ltd.Inventor: Takumi Kawahara
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Publication number: 20110276727Abstract: An apparatus comprising an arbiter circuit, a protocol engine circuit and a channel router circuit. The arbiter circuit may be configured to determine a winning channel from a plurality of channel requests based on a first criteria. Each of the plurality of channel requests may represent a burst of data having a fixed length aligned to an address boundary of a memory. The protocol engine circuit may be configured to receive a signal from the arbiter circuit indicating the winning channel. The protocol engine circuit may also be configured to perform a memory protocol at a granularity equal to the burst of data. The channel router circuit may be configured to present the plurality of channel requests to the arbiter circuit and the protocol engine circuit.Type: ApplicationFiled: August 17, 2010Publication date: November 10, 2011Inventors: Eskild T. Arntzen, Sheri L. Fredenberg, Jackson L. Ellis, Robert W. Warren
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Patent number: 8051419Abstract: A method of dynamically adjusting the number of task requests is provided, which is applicable to an Internet Small Computer System Interface (iSCSI) protocol. When a target receives a task request transmitted by an initiator or the target completes the task request, the number of transmissible tasks is calculated according to an average access data volume, an current access data volume, and an allowable access data volume in the target, and returned to the initiator, such that the number of the task requests transmitted simultaneously by the initiator does not exceed the number of transmissible tasks, thereby achieving flow control. The allowable access data volume is obtained through interactive and dynamic adjustment between the target and the initiator.Type: GrantFiled: February 26, 2007Date of Patent: November 1, 2011Assignee: Inventec CorporationInventors: Hong-Liang Liu, Ho Zhang, Tom Chen, Win-Harn Liu
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Patent number: 8046505Abstract: A memory controller including an address incrementer and a page crossing detect logic. The address incrementer may be configured to generate a next address in a burst from a current address in the burst. The page crossing detect logic may be configured to determine whether the burst will cross a memory page boundary based on the current address and the next address. The memory controller may be configured to automatically split bursts crossing page boundaries.Type: GrantFiled: August 27, 2010Date of Patent: October 25, 2011Assignee: LSI CorporationInventors: Frank Worrell, Keith D. Au
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Patent number: 8041855Abstract: A system for communicating with a processor within an integrated circuit can include a dual-bus adapter (115) coupled to the processor (105) through a first communication channel (110) and a second communication channel (120). The dual-bus adapter further can be coupled to a memory map interface (135) through which at least one peripheral device communicates with the processor. Single word operations can be exchanged between the processor and the dual-bus adapter through the first communication channel. Burst transfer operations can be performed by exchanging signaling information between the processor and the dual-bus adapter over the first communication channel and exchanging data words between the processor and the dual-bus adapter through the second communication channel.Type: GrantFiled: January 27, 2009Date of Patent: October 18, 2011Assignee: Xilinx, Inc.Inventors: Jingzhao Ou, Chi Bun Chan
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Patent number: 8037280Abstract: A system and related method of operation for migrating the memory of a virtual machine from one NUMA node to another. Once the VM is migrated to a new node, migration of memory pages is performed while giving priority to the most utilized pages, so that access to these pages becomes local as soon as possible. Various heuristics are described to enable different implementations for different situations or scenarios.Type: GrantFiled: June 11, 2008Date of Patent: October 11, 2011Assignee: VMware, Inc.Inventors: Vivek Pandey, Ole Agesen, Alex Garthwaite, Carl Waldspurger, Rajesh Venkatasubramanian