Abstract: A storage control apparatus for transmitting data to and receiving data from a plurality of storage devices connected to the same interface, the storage control apparatus includes a memory configured to store a management table registering a burst transfer length of each of the plurality of storage devices, the plurality of storage devices including a first storage device having a first burst transfer length that is a minimum in the management table and a second device having a second burst transfer length; an adjusting controller configured to adjust the second burst transfer length in input and/or output processing if the second burst transfer length registered in the management table is different from the first burst transfer length; and a data transfer controller configured to issue a command for a data transfer to the second storage device on the basis of the adjusted second burst transfer length.

Abstract: A memory system includes a memory controller coupled to at least one memory device via high-speed data and request links. The timing and voltage margins of the links are periodically calibrated to reduce bit error. The high-speed request links complicate calibration because commands issued over the uncalibrated request links can be erroneously interpreted by the memory device. Misinterpreted commands can disrupt the calibration procedure (e.g., a write command might be misinterpreted as a power-down command). The memory controller addresses this problem using a separate, low-speed control interface to issue a filter command that instructs the memory device to decline potentially disruptive requests when in a calibration mode.

Abstract: Provided are techniques for introducing a delay in responding to host write requests. A percentage of fullness of a write cache is determined. Based on the determined percentage of fullness of the write cache (f), a low cache threshold (L), alpha (?), and k, an amount of delay to introduce into responding to a host write request is determined. Techniques wait the amount of the delay before responding to the host write request although the host write request processing has completed.

Abstract: One or more external control pins and/or addressing pins on a memory device are used to set one or both of a burst length and burst type of the memory device.

Abstract: In a data transfer control apparatus, a transfer start address and a transfer size are acquired from a peripheral circuit. A command is issued in response to an activation signal from the peripheral circuit. When data transfer is performed between the main memory unit and the peripheral circuit, completion of issuance of all of commands corresponding to the transfer start address and transfer size is detected. The transfer size is retained until the end of data transfer. A next command is issued prior to completion of data transfer for one command, and a next activation signal is received upon detection of completion of issuance of all of the commands corresponding to the one transfer start address and transfer size. Next transfer start address and transfer size are acquired upon detection of completion of issuance of all of the commands corresponding to the one transfer start address and transfer size.

Abstract: A system balances bandwidth used by a data stream. The system receives data in the data stream and partitions the data into bursts. The system then identifies whether a size of a current one of the bursts is less than a size of a maximum burst associated with the data stream and schedules an additional burst in the data stream when the current burst size is less than the maximum burst size. The system transmits the current burst and the additional burst to balance bandwidth used by the data stream.

Abstract: Methods and a device for performing coherent access requests are disclosed. The methods include receiving a first address associated with a first write or read request. During a write operation, if the first address is associated with a coherent access register, data to be written is stored at a data latch that is connected to a plurality of coherent data access registers. A second address and second data associated with a second write request are received. If the second address matches the first address, the second data and the latched first data are written to the coherent access register. By latching the first data and simultaneously writing the latched first data and the second data, overall coherency of the written data is maintained.

Abstract: To provide a transceiving technology that controls the mounting area of a circuit pertaining to transmission and/or reception and where the utilization efficiency of a buffer is improved. In a transmission side circuit, there are disposed a transmission side first circuit component that generates a first packet that follows a request and a transmission side second circuit component that is a lower-level circuit component of the transmission side first circuit component, includes a transmission buffer and temporarily stores in the transmission buffer, and transmits, a second packet that includes the first packet. The second packet includes a second header portion and a second data portion. In the second data portion that the second packet that is transmitted from the transmission side second circuit component includes, there is included the first packet, and in the second header portion, there is included a predetermined value as a parameter value that represents the type of the second packet.

Abstract: Techniques for transferring stored data between a media player and an accessory. In one set of embodiments, one of the media player and the accessory can obtain a unique identifier for a particular file stored in the other of the media player and the accessory. The one of the media player and the accessory can then retrieve data from the stored file using the unique identifier. In certain embodiments, accessories and media players can retrieve and store data utilizing an arbitrary format. This data can be opaque to any protocol used by the media player or accessory and can require no parsing or interpretation. To provide this facility, a plurality of commands can allow both media players and accessories to present a simple file system. The plurality of commands can be utilized in a variety of environments.

Abstract: An information processing apparatus includes a communication unit that transmits/receives data to and from an external device; a detection unit that detects communication connection with the external device by the communication unit; an operation input unit that accepts an operation input; a command allocation unit that, when the detection unit detects communication connection with the external device, allocates a data transmission command with respect to a one-click operation to a symbol corresponding to a data storage place to be displayed on a display unit, which is accepted by the operation input unit; and a control unit that, when the operation input unit accepts the one-click operation to the symbol, in case the data transmission command is allocated with respect to the one-click operation, controls so that the communication unit transmits data stored in the data storage place corresponding to the symbol to the external device.

Abstract: One or more external control pins and/or addressing pins on a memory device are used to set one or both of a burst length and burst type of the memory device.

Abstract: A network device includes a port and a bus transmission calculation module. The port is connected to the network device to receive a data burst. The bus transmission calculation module connects to the port for calculating a first number of bytes to be transmitted from a first bus and a second number of bytes to be transmitted from a second bus. The first and second bus connect to the network device and transfer data from the network device.

Abstract: A memory controller has a control unit receiving a transfer data from a transmission circuit and executing a burst transfer of the transfer data to a reception circuit. The transmission circuit transmits a first data of a first bit length for a first burst times by a burst transmission. The amount of the transfer data is equal to a product of the first bit length and the first burst times. The reception circuit receives a second data of a second bit length for a second burst times by a burst reception. When the amount of the first data received by the control unit becomes equal to or more than a product of the second bit length and the second burst times, the control unit transfers the received first data as the second data to the reception circuit, regardless of the number of the first data received by the control unit.

Abstract: A method, apparatus, and computer instructions for transferring data from a memory to a network adapter in a data processing system. The frame size for a transfer of the data from the memory to the network adapter is identified. If the frame size is divisible by a cache line size without a remainder, a valid data length is set equal to the length field. However, if the frame size divided by the cache line size results in a remainder, the length field is set to align the data with the cache line size. The data transfer is then initiated using these fields.

Abstract: A method for expediting data access of a Universal Serial Bus (USB) storage device is disclosed. In a first embodiment, a data transmission procedure without the need of sending command block wrappers (CBW) is executed if a read command for reading data of a large memory space is received, and the addresses of the read commands are continuous. In a second embodiment, several write commands of continuous addresses are stored in a buffer area and combined into a larger single request command before sending to the USB storage device, so as to reduce the number of times of sending CBW and command status wrapper (CSW) required for the data transmission. In a third embodiment, more data are read and stored in a buffer area in advance when a read command is received, such that the next command can read data from the buffer area to improve the speed of reading data.

Abstract: The present invention relates to an asynchronous data buffer for transferring m data elements of a burst-transfer between two asynchronous systems. The asynchronous data buffer comprises a data memory for storing m data elements of a data burst and a valid bit memory for storing m input valid bits corresponding to the m data elements. Input control logic circuitry generates the m input valid bits and controls storage of the same and the m data elements. After storage of the m input valid bits an input control signal is provided for inverting the input valid bits of a following data burst. Therefore, after each burst-transfer of m data elements the input valid bit is inverted, automatically rendering all data elements of a previous burst-transfer invalid.

Abstract: A data transfer system is provided, in which divided data generated by data generation terminals are randomly transmitted to data transfer apparatuses by a host terminal, a parameter list controlling the order of transfer of divided data is generated by a parameter list generation part, and a transfer processing part transfers divided data transferred in a DMA mode to an electron beam drawing apparatus according to the parameter list through a general-purpose high-speed data transfer bus by bypassing a CPU.

Abstract: Described is a system to control a flow of packets to and from an electronic processor which includes a packet processor engine programmed to interpret the packets from a packet memory, and to perform switching between packet chains in response to events, a working chain pointer register of the packet processor engine, programmed to indicate progress in executing an active buffer chain, prioritized pointer storage registers of the packet processor engine, each of the registers being programmed to point to one of the active buffer chains, a control register of the packet processor engine having chain start bits and chain protect bits, the chain start bits identifying the chains that have been started and wsa status register of the packet processor engine, having a chain actives group identifying the chain that is currently running, a chain matches group, a chain stops group identifying the chains that have been stopped and a timer expirations group.

Abstract: A system and method for determining media to be exported out of a media library is described. In some examples, the system determines a media component to be exported, determines the media component is in the media library for a specific process, and exports the media component after the process is completed.

Abstract: A memory system is provided that supports partial cache line read operations to a memory module to reduce read data traffic on a memory channel. The memory system comprises a memory hub device integrated in the memory module and a set of memory devices coupled to the memory hub device. The memory hub comprises burst logic integrated in the memory hub device. The burst logic determines an amount of read data to be transmitted from the set of memory devices and generates a burst length field corresponding to the amount of read data. The memory hub also comprises a memory hub controller integrated in the memory hub device. The memory hub controller controls the amount of read data that is transmitted using the burst length field. The memory hub device transmits the amount of read data that is equal to or less than a conventional data burst amount of data.

Abstract: A memory controller including an address incrementer and a page crossing detect logic. The address incrementer may be configured to generate a next address in a burst from a current address in the burst. The page crossing detect logic may be configured to determine whether the burst will cross a memory page boundary based on the current address and the next address. The memory controller may be configured to automatically split bursts crossing page boundaries.

Abstract: A method for interfacing single transfer and burst transfer components, comprising: processing transfer completion of a byte in burst transfer as an interrupt; maintaining the current state of signal lines to prevent occurrence of next interrupt; copying the transferred byte from buffer to memory; and allowing next interrupt; and enabling sending of next byte in burst transfer. This invention interfaces incompatible signaling of the components, and solves the handshake, communication and buffering problems involved.

Abstract: Even after reading data from a memory in response to a read request received from a bus master and burst transferring the read data, the memory interface 100 continues to read and store data starting from an address that follows all of addresses of the read data. Upon receiving a new read request from the bus master within a predetermined time, the memory interface 100 determines whether a difference between the address specified by the previous read request and the address specified by the new read request falls within a predetermined range. If it is determined positively, the memory interface 100 successively transfers the stored data in response to the new read request. If it is determined negatively, or if the reception of the new read request is not performed within the predetermined time, the memory interface 100 terminates the continuous data read.

Abstract: The information processing device in the present invention includes a memory 1 which is a DRAM featuring a burst mode, and burst-transfers data at successive column addresses, masters (13), (14), and (15) which issue access requests, and a command processing unit (11) which converts an access address that is included in the access request issued from each master. One or more of the masters access an M×N rectangular area where M and N are integers, and the command processing unit (11) converts access addresses so that a column address of data at the (K+m)th column, where K and m are integers and m?M, of an Lth line, and a column address of data at a Kth column of an (L+n)th line, where L and n are integers and n?N, become successive.

Abstract: Input/output processing is facilitated by reducing communications between input/output communications adapters and control units during input/output processing. The number of exchanges and sequences between an input/output communications adapter and control unit is reduced by sending a plurality of commands from the adapter to the control unit as a single entity for execution by the control unit. The control unit executes the commands and provides the data, if any, in one sequence. The control unit relieves the adapter of the responsibility of tracking state of the individual commands and is able to calculate precise measurement data relating to execution of the commands.

Abstract: A system and method is disclosed for programming a field programmable gate array. The system involves the recognition of the next following bit sequence to be transmitted to the FPGA through a general purpose input output device. Once the bit sequence is identified, the data line is only changed at the GPIO in those instances in which the next succeeding data bit in the bit sequences is different from the preceding data bit. In those situations in which the next following bit sequence is not different, the clock line is triggered without the necessity of testing, and changing the logic level of the data line.

Abstract: A scalable first-in-first-out queue implementation adjusts to load on a host system. The scalable FIFO queue implementation is lock-free and linearizable, and scales to large numbers of threads. The FIFO queue implementation includes a central queue and an elimination structure for eliminating enqueue-dequeue operation pairs. The elimination mechanism tracks enqueue operations and/or dequeue operations and eliminates without synchronizing on the FIFO queue implementation.

Abstract: The invention relates to a method and to a system for transmitting data of a data type to be transmitted cyclically and of a data type which can be transmitted acyclically via a common transmission channel from a first participant unit connected to the transmission channel to at least one further participant unit connected to the transmission channel. The invention proposes to develop a method based on a protocol-specific cyclic transmission sequence of transmission messages for transmitting data of a data type to be transmitted cyclically via a transmission channel. When a particular type of impending transmission message is detected for which redundant data of the data type to be transmitted cyclically are provided without new information content, instead of these data, data of a data type which can be transmitted acyclically are inserted into the data area provided for data of this data type to be transmitted cyclically.

Abstract: A channel-less system and method are provided for multithreaded communications with a direct memory access (DMA) controller. The method accepts a plurality of DMA command messages directed to a fixed port address. The DMA command messages are arranged in a first-in first-out (FIFO) queue, in the order in which they are received. The DMA command messages are supplied to a DMA controller from the FIFO queue, and in response to the DMA command message, data transfer operation are managed by the DMA controller. Following the completion of each data transfer operation, a transfer complete message indicating completion is sent. In one aspect, DMA command messages are arranged in a plurality of parallel FIFO queues, and CD sets are stored in a plurality of context memories, where each context memory is associated with a corresponding FIFO queue.

Abstract: A mechanism is provided for transmitting data in a data network. A first processor of the data network receives data to be transmitted to a second processor within the data network. A determination is made if the data has previously been routed through an indirect communication link from a source processor, the indirect communication link being a communication link that does not directly couple the source processor to a final destination processor which is to receive the data. A communication link is selected over which to transmit the data from the first processor to the second processor based on results of determining if the data has previously been routed through an indirect communication link. Finally, the data is transmitted from the first processor to the second processor using the selected communication link.

Abstract: The invention discloses methods and apparatus for regulating the transfer of data bursts across a data network comprising electronic edge nodes interconnected by fast-switching optical core nodes. To facilitate switching at an electronic edge node, data bursts are organized into data segments of equal size. A data segment may include null data in addition to information bits. The null data are removed at the output of an edge node and the information data is collated into bursts, each carrying only information bits in addition to a header necessary for downstream processing. To ensure loss-free transfer of bursts from the edge to the core, burst transfer permits are generated at controllers of the optical core and sent to respective edge nodes based on flow-rate-allocation requests. Null-padding is not visible outside the edge nodes and only the information content is subject to transfer rate regulation to ensure high efficiency and high service quality.

Abstract: A method and apparatus is provided for a configurable input/output (I/O) interface within an integrated circuit to support a plurality of I/O standards. The configurable I/O interface exhibits a default operation that facilitates hot-swappability, which eliminates current paths within the I/O interface that may be created during plug-and-play operation of the I/O interface. The current paths are eliminated within the I/O interface even while the I/O interface is not receiving operational power, or while the I/O interface is in a power-on reset condition. A programmable option of the configurable I/O interface, on the other hand, alleviates over-voltage conditions while the I/O interface is tri-stated by activating shunt circuitry to conduct a clamp current during the over-voltage condition. The over-voltage condition is further alleviated by passively establishing current paths through existing circuitry within the I/O interface for the duration of the over-voltage condition.

Abstract: A system balances bandwidth used by a data stream. The system receives data in the data stream and partitions the data into bursts. The system then identifies whether a size of a current one of the bursts is less than a size of a maximum burst associated with the data stream and schedules an additional burst in the data stream when the current burst size is less than the maximum burst size. The system transmits the current burst and the additional burst to balance bandwidth used by the data stream.

Abstract: An interface includes a controller that divides a burst access command into a plurality of command cycles and supplies the plurality of command cycles to a storage device including a plurality of blocks, and a block address converter that outputs an address at a first command cycle of the plurality of command cycles. The address is obtained by shifting at least one bit of an external block address input in response to the burst access command. The address is supplied to the storage device at the first command cycle, and the external block address is supplied to the storage device at a command cycle other than the first command cycle.

Abstract: Methods, systems, and products are disclosed for chaining DMA data transfer operations for compute nodes in a parallel computer that include: receiving, by an origin DMA engine on an origin node in an origin injection FIFO buffer for the origin DMA engine, a RGET data descriptor specifying a DMA transfer operation data descriptor on the origin node and a second RGET data descriptor on the origin node, the second RGET data descriptor specifying a target RGET data descriptor on the target node, the target RGET data descriptor specifying an additional DMA transfer operation data descriptor on the origin node; creating, by the origin DMA engine, an RGET packet in dependence upon the RGET data descriptor, the RGET packet containing the DMA transfer operation data descriptor and the second RGET data descriptor; and transferring, by the origin DMA engine to a target DMA engine on the target node, the RGET packet.

Abstract: The process acquires data blocks in real-time with a fast scanner. The acquired data blocks are then transmitted to a computer system (23). The data blocks are then processed as a function of a frame burst ratio (N). The transmission of the acquired data blocks to the computer system is a function of the frame burst ratio (N). The frame burst ratio (N) may be either fixed or variable. In any case, optimal utilization of the computer system's (23) performance is important. The frame burst ratio (N) is selected by the user or by the computer system (23) itself as a function of the processing characteristics of the computer system (23).

Abstract: A method for transmitting and receiving digitally modulated wireless signals using an analog FM transceiver is provided. The analog FM transceiver has a transmit speech audio frequency band, a receive speech audio frequency band substantially equal to the transmit speech audio frequency band, a subaudible frequency band, a direct microphone audio input, and a direct speaker audio output. The method includes generating, in a baseband digital spectrum translator external to the analog FM transceiver, a baseband transmit signal occupying frequencies substantially within the transmit speech audio frequency band of the analog FM transceiver. The method also includes applying the generated baseband transmit signal to the direct microphone audio input to thereby transmit a digitally encoded RF TX signal having a constant envelope and using the analog FM transceiver to receive a digitally encoded RF RX signal with a constant envelope and to generate a baseband receive signal using the digitally encoded RF RX signal.

Abstract: A direct memory access controlling method includes checking a length value of remaining data corresponding to data remaining after transmission of the data stored in the source memory to the destination memory, and a currently set burst length value, comparing the length value of the remaining data with the currently set burst length value based on a result of the checking, and selectively changing the currently set burst length value based on a result of the comparing, and transmitting data to the destination memory.

Abstract: An arbitration device arbitrates among master devices such that each master device is allowed to access a shared memory at a predetermined bandwidth, and the arbitration device permits an access request in a first period that a designer has set as desired if the access request has been made by a specific master device beyond a bandwidth that has been allocated in advance. The arbitration device masks an access request from the specific master device in a second period that follows the first period.

Abstract: A direct memory access (DMA) circuit (200) includes a read port (202) and a write port (204). The DMA circuit (200) is a multithreaded initiator with “m” threads on the read port (202) and “n” threads on the write port (204). The DMA circuit (200) includes two decoupled read and write contexts and schedulers (302, 304) that provide for more efficient buffering and pipelining. The schedulers (302, 304) are mainly arbitrating between channels at a thread boundary. One thread is associated to one DMA service where a service can be a single or burst transaction. The multithreaded DMA transfer allows for concurrent channel transfers.

Abstract: In some embodiments, a chip includes a link interface, monitoring circuitry to provide an activity indicator that is indicative of activity of the chip, and scheduling circuitry to schedule commands. The chip also includes mode selection circuitry to select a first mode or a second mode for the scheduling circuitry depending on the activity indicator, wherein in the first mode the scheduling circuitry schedules certain commands as separate single commands and in the second mode the scheduling circuitry schedules at least one consolidated command to represent more than one of the separate single commands. Other embodiments are described.

Abstract: The DMA data transfer apparatus includes a memory, a communication controller, a DMA controller having a plurality of DMA engines each of which transfers data by DMA to the communication controller from the memory, and a DMA control unit. The DMA control unit determines a division size of transfer data such that the DMA engine can transfer the data, issues a data transfer directive by the DMA to the DMA controller, and controls data transfer by the DMA. The DMA control unit transmits the determination information for determination of the termination of data transfer to the communication controller. The communication controller determines the termination of data transfer based on the determination information transmitted from the DMA control unit.

Abstract: Data transmission systems and methods. The data transmission system comprises a bus, a slave, a master, and a master interface. The master transmits a request comprising transfer information comprising a start address and a length. The master interface receives the request from the master. The master interface determines a burst type of a first burst according to the transfer information, and transmits the first burst with the burst type to the slave via the bus, where the first burst is aligned to at least one address boundary of the slave. The master interface receives data corresponding to the first burst from the slave, and transmits the data to the master.

Abstract: Bus communication for components of a system on a chip. In one aspect of the invention, a system including bus communication to a slave includes a bridge operative to interface a first bus protocol to a bus matrix that uses a second bus protocol. A first serializer coupled to the bridge serializes information received from the bridge and sends the serialized information over a communication bus. A second serializer coupled to the communication bus receives the serialized information and deserializes the serialized information. A slave uses the first protocol and is coupled to the second serializer, where the deserialized information is provided to the slave, and the slave provides a response to the information from the bridge.

Abstract: Methods and a device for performing coherent access requests are disclosed. The methods include receiving a first address associated with a first write or read request. During a write operation, if the first address is associated with a coherent access register, data to be written is stored at a data latch that is connected to a plurality of coherent data access registers. A second address and second data associated with a second write request are received. If the second address matches the first address, the second data and the latched first data are written to the coherent access register. By latching the first data and simultaneously writing the latched first data and the second data, overall coherency of the written data is maintained.

Abstract: Various methods and processing systems are disclosed which include sending and receiving components communicating over a bus having first and second channels. The sending component may broadcast on the first channel a plurality of read and write address locations, a plurality of transfer qualifiers, and write data. The receiving component may store the write data broadcast on the first channel at the receiving component based on the write address locations and a first portion of the transfer qualifiers. The receiving component may also retrieve read data from the receiving component based on the read address locations and a second portion of the transfer qualifiers, and broadcast the retrieved read data on the second channel.

Abstract: A burst termination control circuit includes: a pull-up unit for pulling up a first node in response to a burst termination signal, a latch unit for latching a signal of the first node, a buffer for generating a first termination control signal for stopping data output operation by buffering an output signal of the latch unit, and a logic unit for generating a second termination control signal for stopping burst operation and generation of an output enable signal in response to an output signal of the latch unit.

Abstract: In a system where data is transmitted from a source device to a destination device via one or more buses, transmission mode selecting circuitry is provided to select one of a first transmission mode and a second transmission mode for the data in response to a mode selecting signal that indicates a latency requirement of the destination device. When data is sent using the second mode there is a lower latency between the destination device receiving the data and being able to process the data than when the first transmission mode is used.

Abstract: Command translation of burst commands is described. A slave processor local bus (“PLB”) bridge, part of a processor block core embedded in a host IC, has a data size threshold to allow access to a crossbar switch device. A master device, coupled to the slave PLB bridge, has any of a plurality of command bus widths. A burst command is issued via a command bus, having a command bus width of the plurality, from the master device for the slave PLB bridge. The burst command is converted to a native bus width of the slave processor logic block if the command bus width is not equal to the native bus width. The burst command is translated if execution of the burst command will exceed the data size threshold and passed without the translating if the execution of the burst command will not exceed the data size threshold.

Abstract: A data processing apparatus transmits and receives moving image data to and from an external device through a transmission path. A first pipe used for transferring the moving image data and a second pipe used for transferring timing information relating to the processing timing of the moving image data are provided on the transmission path. The moving image data is being transferred to the external device through the first pipe in parallel with the timing information relating to the moving image data being transferred through to the external device through the second pipe.