Abstract: A wire adapter in a Wireless Universal Serial Bus configuration includes endpoints bound to communication constructs for communicating with discrete identified endpoints of downstream devices. A Virtual Pipe system is provided for the wire adapter to manage the communications pathways between a host and a downstream device connected to the wire adapter. The system provides for establishing data pathways through previously unused endpoints in the wire adapter.

Abstract: Disclosed is a data transmission system in which a set of asymmetrical serial buses are formed by a set of multiplexed unidirectional buses and a reverse-direction sole serial bus. A synchronization signal is superimposed on the signal transmitted over each of the multiplexed unidirectional buses. The multiplexed unidirectional buses are used mainly for data transfer, and the reverse-direction sole serial bus is used for transmitting the control information, such as ACK response, to the data transfer.

Abstract: A bus system, which may prevent data from being incorrectly transferred when an early termination occurs during a burst mode, may include a bus, for example, an advanced high-performance bus (AHB), at least one bus master device, a bus arbiter and at least one transfer mode selection circuit. The at least one bus master device may generate a burst cycle control signal, a transfer start signal and a bus control request signal for requesting control of the bus, and may be activated in response to a bus control grant signal, so as to exchange data via the bus. The bus arbiter may generate the bus control grant signal in response to the bus control request signal and provide the bus control grant signal to the bus master device. The at least one transfer mode selection circuit may convert a burst mode into a single mode to generate a selection signal, when the bus control grant signal is deactivated before a burst mode operation is completed.

Abstract: The present invention relates to an asynchronous data buffer for transferring m data elements of a burst-transfer between two asynchronous systems. The asynchronous data buffer comprises a data memory for storing m data elements of a data burst and a valid bit memory for storing m input valid bits corresponding to the m data elements. Input control logic circuitry generates the m input valid bits and controls storage of the same and the m data elements. After storage of the m input valid bits an input control signal is provided for inverting the input valid bits of a following data burst. Therefore, after each burst-transfer of m data elements the input valid bit is inverted, automatically rendering all data elements of a previous burst-transfer invalid.

Abstract: When a first mode (with-SOF mode) has been set, data transfer is performed while SOF packets are transferred at frame periods, and when a second mode (non-SOF mode) has been set and also non-periodic (bulk) transfer is being performed, the periodic transfer of SOF packets is disabled and non-periodic data is transferred. If there is no non-periodic data to be transferred, a SOF packet is transferred in the frame period, even if the second mode has been set. During host operation with USB on-the-go (OTG), pipe regions are allocated to the packet buffer, and non-periodic data is transferred automatically to or from end points while the periodic transfer of SOF packets is disabled. When all of the automatic transfer instruction signals of the pipe regions are inactive, SOF packets are transferred periodically even if the second mode has been set.

Abstract: A method, apparatus and program storage device for managing dataflow through a processing system is disclosed. A buffer monitor maintains and monitors a buffer full threshold to control the write throughput to a data bus.

Abstract: Method and system for optimizing DMA request processing is provided. The system includes a HBA that uses a dynamic DMA maximum write burst count sizing to optimize processing of write and read requests, wherein the HBA includes a DMA optimizer module that selects a certain write burst size to adjust performance when read and write DMA requests are being utilized. The DMA optimizer module can toggle between write and read request priority based on a maximum write request burst size. A shorter maximum write burst size provides more opportunity to issue read requests and a larger maximum burst size provides a better write request performance. The method includes, evaluating a read request throughput rate; evaluating a write request throughput rate; evaluating a read request utilization rate; evaluating a write request utilization rate; and adjusting a maximum write burst size.

Abstract: A memory device and a method of providing the memory device. The method includes providing the memory device with a memory array arrangement of width N and providing a first configuration of the memory device and a second configuration of the memory device. Providing the first configuration of the memory device includes providing the memory device with a data pin output of width N/M and a burst length of M, where M is less than N. Providing the second configuration of the memory device comprises providing a data pin output of width N/P and a burst length of P, where P is less than M, wherein M, N, and P are all integers.

Abstract: A semiconductor apparatus comprises a data processing unit for processing data, a buffer for temporarily storing the data processed by the data processing unit, and a buffer control unit for causing the data stored in the buffer to be burst-transferred to a data storage unit. The buffer control unit allows burst-transfer of the data stored in the buffer to be started before full amount of data to be transferred in a single burst-transfer is stored in the buffer.

Abstract: In accordance with one embodiment of the present invention, a method of applying an action initiated for a portion of a plurality of devices to all of the plurality of devices is provided. The method comprises establishing a status block for a plurality of devices that are implemented on a system, and initiating an action for a portion of the plurality of devices. The method further comprises writing information to the status block identifying that the action was initiated, and based at least in part on the information written to the status block, applying the action to all of the plurality of devices.

Abstract: Provided are a method and apparatus for controlling direct memory access. In the method, data to be transmitted are read and stored in response to a direct memory access controller (DMAC) operation request, and a portion of the data corresponding to an initial burst size is first transmitted to a data destination. After resetting a burst size according to a state of the data destination, another portion of the data corresponding to the reset burst size is second-transmitted to the data destination. If all the data are not transmitted through the first-transmission and the second-transmission, the second-transmission is repeated until all the data are transmitted. If all the data are transmitted through the first-transmission and the second-transmission, an interrupt signal is generated. Therefore, interrupt signals can be less generated, and thus the processor can access an external memory less frequently, thereby increasing system performance.

Abstract: A DMA channel data quantity setting section sets a data transfer quantity of each of a plurality of DMA channels in accordance with a data quantity or a ratio in advance. A channel select control circuit determines whether each DMA channel is active. A data transfer control circuit transfers the data of the DMA channel determined to be active by the channel select control circuit in accordance with the data transfer quantity of each DMA channel set by the DMA channel data quantity setting section. By doing so, a plurality of DMA requests are accepted per bus hold request, and the number of bus management right arbitration procedures and the latency between the channels are decreased.

Abstract: A method, apparatus, and computer instructions for transferring data from a memory to a network adapter in a data processing system. The frame size for a transfer of the data from the memory to the network adapter is identified. If the frame size is divisible by a cache line size without a remainder, a valid data length is set equal to the length field. However, if the frame size divided by the cache line size results in a remainder, the length field is set to align the data with the cache line size. The data transfer is then initiated using these fields.

Abstract: A system-on-chip (100) includes a 16-bit DSP (102), a 16-bit data bus (202) coupled to the DSP, at least one 32-bit-only peripheral (110), a 32-bit data bus (212) coupled to the peripheral, and a bridge (108), including a write merge system (200), coupled between the 16-bit and 32-bit buses. A method of the write merge system includes pre-storing addresses of peripherals in a memory map structure (220 and 221), receiving 16-bit data and a write transaction from the DSP for modifying sixteen bits of a 32-bit data location of the peripheral; reading 32-bit contents of the data location of the peripheral; multiplexing the received 16-bit data with the read 32-bit contents; and writing a new 32-bit word, including the modified sixteen bits and an unmodified sixteen bits, to the data location of the peripheral, without any intervention from the DSP subsequent to receiving the write transaction.

Abstract: A digital television system, a memory controller, and a method for data access are provided. The digital television system comprises a memory and the memory controller. The memory controller writes a data packet to or reads a data packet from the memory. The memory controller comprises a register, a data packet adjuster, a burst length determination unit, and a frequency determination unit. The register sets a data bus width. The data packet adjuster adjusts the data packet according to the data bus width. The burst length determination unit determines a burst length according to the data bus width. The frequency determination unit determines an operating frequency of the memory controller according to the data bus width. The memory controller writes or reads the adjusted data packet in response to the burst length and the operating frequency.

Abstract: Disclosed are interface buses that facilitate communications among two or more electronic devices in standard mode and burst mode, and bus bridges from such buses to a memory unit of such a device. In one aspect, interface buses group the data lines according to groups of bits, and include group-enable lines to convey a representation of which groups of data lines are active for each data transfer operation. In another aspect, exemplary interface buses include burst-length lines to convey a representation of the number of data bursts in a burst sequence, thereby obviating the need to provide sequential addresses over the bus. Exemplary bus bridges are capable of interpreting the signals on the interface bus and transferring data bursts between the interface bus and one or more memory units within the device.

Abstract: Multiple burst memory access handling protocols may be implemented at the hardware level or evaluated and selected during design of the hardware. The appropriate burst protocol may be selectable based on burst characteristics such as burst types and the identity of the current bus master. This allows, for example, the ability for a slave to support multiple error protocols in a multi-master system on a chip (SoC), or to design slaves capable of interfacing with a variety of masters which use different burst handling protocols. Inputs such as a programmable control register or configuration pins or variables may be provided to as part of the slave or slave interface block (e.g., a memory controller) to facilitate the implementation of alternate burst protocols. When a burst request is received from a master, a burst characteristic corresponding to the requested burst is determined and one of a plurality of burst error protocols is selected based on the burst characteristic.

Abstract: An RPO algorithm in a HDD coalesces LBA-sequential XOR commands in pipes, and passes the pipes to a lower level execution engine. The execution engine executes XOR reads and write separately to optimize performance using head and/or cylinder skew information to approach the nominal disk data rate.

Abstract: A JTAG-compliant device is configured to receive data through the control (TMS) line in addition to being configured to receive data through the input (TDI) line. A burst-write instruction is made the active instruction, extending the capability of the test access protocol (TAP) controller such that the TAP controller can receive data into a data register while the TAP controller is in certain states. In some states, the TAP controller receives and stores a bit only from the input line. In other states, the TAP controller receives and stores a bit from the input line, and in addition, the TAP controller receives and stores a bit from the control line. The TAP controller may store the received bits by shifting the received bits into the least significant bit of a data register.

Abstract: Decimation of data from a fixed length queue retaining a representative sample of the old data. Exponential decimation removes every nth sample. Dithered exponential decimation offsets the exponential decimation approach by a probabilistic amount. Recursive decimation selects a portion of the queue and removes elements.

Abstract: An access control method and a memory interface which enable access without a redundant bus cycle even to a burst memory having an addressing function different from the system side. A state machine is provided so that addressing mode information of a memory is read from a system internal register, and if burst access is performed at a system address by a predetermined addressing scheme of a bus master, when the addressing scheme of the memory internal address differs from a predetermined addressing scheme of the bus master, at an address transition position where there is a mismatch between the memory internal address and the system address, burst access is first terminated, burst transfer is resumed from an aligned address, and the remaining data are then accessed.

Abstract: In order to reduce overhead of a CPU, a relay apparatus for relaying communication from a CPU to a peripheral device includes communication information holding sections for holding information required for communication with the peripheral devices inside the relay apparatus; and command holding sections, which are provided adjacent to the communication information holding section, for holding commands used to communicate desired information inside the communication information holding section to the peripheral device. The CPU writes desired information in the communication information holding section and the command holding section inside the relay apparatus by burst-mode communication, and the relay apparatus performs communication with the peripheral devices in accordance with instructions from the command holding section after the writing of the desired information in the communication holding section and the command holding section is completed.

Abstract: A data processor including a central processing unit and a data transfer control unit is disclosed. The data transfer control unit has an address register for storing a transfer address. The data transfer control unit transfers data according to a transfer unit size selected from a plurality of transfer unit sizes. If the address register contains an odd address as an initial value, the data transfer control unit transfers data according to a different transfer unit size that is smaller than the selected transfer unit size. If the data transfer control unit determines that a remaining quantity of data to be transferred is smaller than the selected transfer unit size, the selected transfer unit size is switched to a smaller transfer unit size selected from the plurality of transfer unit sizes.

Abstract: The present invention is a method and apparatus to buffer data. A buffer memory of a first type stores data associated with a connection identifier corresponding to a channel in a network. The data is organized into at least one chunk based on a linked list. The connection identifier identifies a connection in the channel. The data is part of a data stream associated with the connection. A packet memory of a second type provides access to the stored data when a transfer condition occurs.

Abstract: Methods and associated structure for utilizing multiple ports or PHYs comprising a SAS wide port to improve transmission bandwidth utilization for a single large I/O request. In one aspect hereof, a large I/O request is broken into a plurality of smaller I/O requests to be distributed over multiple PHYs or ports of a configured wide SAS port. The number of smaller I/O requests may be any number up to the maximum number of PHYs or ports comprising the SAS wide port. In another aspect hereof, the size of a large I/O request may be compared against a threshold value to determine whether the large request should be broken into smaller requests. The threshold value may be determined in accordance with features and aspects hereof either statically or dynamically based on workloads assigned to, and utilization of, the configured SAS wide port.

Abstract: In order to perform functional packet copying to read a large amount of data of an unspecified length from a memory at high speed and to prevent the packet copying operation from affecting other packet flow, a self-synchronous transfer control circuit having a function of controlling transfer operation is used, by which the number of packet copies output from a data holding register is managed by a counter, and the number of copies represented by the copy request packet and the counter count value are compared by a comparator, to determine completion of the packet copying operation.

Abstract: A bus architecture includes master devices that are each capable of initiating a data transfer procedure by generating a bus request signal. Each of the master devices is arranged to transmit an address signal to an address input of a multiplexer, to transmit a data signal to a data input of the multiplexer, and to transmit a control signal to a control input of the multiplexer. The control signals may include burst type control signals. The multiplexer is capable of selectively coupling a selected master device chosen from the group consisting of the master devices to a bus. The bus architecture further includes an arbiter arranged to receive the bus request signals as first inputs and arranged to receive the burst type control signals as second inputs, where the burst type control signals are received from an ingress side of the multiplexer.

Abstract: For one or more disclosed embodiments, a plurality of rows of memory cells in a memory bank are activated, and a column of memory cells in the memory bank is selected to select memory cells common to activated rows and the selected column. At least one of the selected memory cells common to activated rows and the selected column is selectively accessed. The selecting and the selectively accessing are repeated to access memory cells common to activated rows and a plurality of selected columns.

Abstract: A bus master 2, 4 sends write transactions to a bus slave 8 which include separate write addresses AW and write data WD. Write transaction identifiers AWID, WID are associated with these write addresses and write data. The bus slave can accept multiple write addresses such that there can be copending write transactions to the same bus slave. The bus slave uses the write transaction identifiers to correlate interleaved write data for the co-pending write transactions with their write addresses.

Abstract: Data not stored in the DRAM array of a SDRAM module is read from the SDRAM module in a synchronous data transfer. The data transfer, referred to as register read command/operation, resembles a read command/operation directed to data stored in the DRAM array in timing and operation. The register read command is distinguished by a unique encoding of the SDRAM control signals and bank address bits. In one embodiment, the register read command comprises the same control signal states as a MSR or EMSR command, with the bank address set to a unique value, such as 2?b10. The register read command may read only a single datum, or may utilize the address bus to address a plurality of data not stored in the DRAM array. The register read operation may be a burst read, and the burst length may be defined in a variety of ways.

Abstract: Data not stored in the DRAM array of a SDRAM module is read from the SDRAM module in a synchronous data transfer. The data transfer, referred to as register read command/operation, resembles a read command/operation directed to data stored in the DRAM array in timing and operation. The register read command is distinguished by a unique encoding of the SDRAM control signals and bank address bits. In one embodiment, the register read command comprises the same control signal states as a MSR or EMSR command, with the bank address set to a unique value, such as 2'b10. The register read command may read only a single datum, or may utilize the address bus to address a plurality of data not stored in the DRAM array. The register read operation may be a burst read, and the burst length may be defined in a variety of ways.

Abstract: Enhancing the throughput rate of a memory access system by using store and forward buffers (SFB) in combination with a DMA engine. According to an aspect of the present invention, the worst case throughput rate (without use of SFBs) is computed, and maximization factor equaling a desired throughput rate divided by the worst case throughput rate is computed. A number of SFBs is determined as equaling one less than the maximization factor. By placing the SFBs at appropriate locations in the data transfer path, the desired throughput rate may be attained when transferring large volumes of data.

Abstract: The invention describes a modification of FIFO hardware to allow improved use of FIFOs for burst reading from or writing to a processor direct memory access unit via either an expansion bus or an external memory interface using FIFO flag initiated bursts. The hardware and FIFO signal modifications make the FIFO-DMA interface immune to deadlock conditions and generation of spurious interrupt events in the process of initiating burst transfers. The FIFO function is modified to synchronize the frame transfer on the digital signal processor even if the digital signal processor lacks this functionality. By delaying the programmable flag assertions within the FIFO until after the current burst is complete the DSP-FIFO interface may be made immune to deadlock conditions and generation of spurious events.

Abstract: A data transferring apparatus for transferring liquid ejection data has a decoding unit having a decode circuit, which can perform hardware development on liquid ejection data, a line buffer for storing the liquid ejection data developed by a word unit and a compressed data inputting unit for transferring the liquid ejection data from an external part to the decode circuit.

Abstract: Column addresses are generated by a burst controller that includes respective latches for the three low-order bits of a column address. The two higher order bits of the latched address bits and their compliments are applied to respective first multiplexers along with respective bits from a burst counter. The first multiplexers apply the latched address bits and their compliments to respective second multiplexers during a first bit of a burst access, and bits from a burst counter during the remaining bits of the burst. The second multiplexers are operable responsive to a control signal to couple either the latched address bits or their compliments to respective outputs for use as an internal address. The control signal is generated by an adder logic circuit that receives the two low-order bits of the column address.

Abstract: Compressed recording data is DMA-transferred to a receiving buffer unit via a system bus one word each. It is DMA-transferred from the receiving buffer unit to a DECU via the system bus. It is developed based on hardware by a decode circuit in the DECU, and stored in a line buffer. It is DMA-transferred to a local memory via a local bus when it reaches predetermined bytes. The recording data stored in the local memory is DMA-transferred to the DECU via the local bus, DMA-transferred to a head controlling unit and DMA-transferred to a recording head.

Abstract: In a transaction system, a dynamic batching process enables efficient flushing of data in a data buffer to a stable storage device. The transaction system uses constant values and dynamic values and a system performance history to adjust the rate of flushing data and also to adjust the amount of data flushed in each flush operation. The transaction system is able to respond to both spikes in rate of received transactions as well as more gradual changes in the rate of received transactions and to automatically adapt to stable storage device performance variations.

Abstract: Provided are a method, system, and program for managing requests to an Input/Output (I/O) device. The I/O requests directed to the I/O device are queued and a determination is made as to whether a number of queued I/O requests exceeds a threshold. If the number of queued I/O requests exceeds the threshold, then a coalesce limit is calculated. A number of queued I/O requests not exceeding the calculated coalesce limit are coalesced into a coalesced /O request and the coalesced I/O request is transmitted.

Abstract: A direct memory access (DMA) descriptor table to control DMA of information in a memory is disclosed. The DMA descriptor table includes one or more DMA descriptor lists stored in the memory. Each DMA descriptor lists may include one or more pointers and information regarding the type of data being directly memory accessed. The pointers may point to a starting address in the memory from which to directly memory access data, prior state information, or program code from and to the memory.

Abstract: One or more external control pins and/or addressing pins on a memory device are used to set one or both of a burst length and burst type of the memory device.

Abstract: Memory apparatus and methods accumulate data between a data path and a memory device. A memory agent may have a data accumulator between a redrive circuit and a memory device or interface. The data accumulator may accumulate data to or from the redrive circuit. Other embodiments are described and claimed.

Abstract: In a multiprocessor system, comprising master and slave processors, a cache coherency controller, and address concentration devices; a method for improving coherent data transfers is described. A command transaction is generated, and a subsequent command from an initiator. Tags added to the responses or further request responses, stream on high-speed busses. Snoops and accumulated snoops expand on cacheline requests as each processor separates burst commands into multiple cacheline requests. Address concentrators containing a cacheline queue function, funnel transaction requests to a global serialization device, where a queuing process prioritizes indicia and coordinates the results among the processors. The cache issues a single burst command for each affected line. System coherency, performance, and latency improvements occur. Additional support for burst transfers between coherent processors is provided.

Abstract: A computer system having a plurality of parallel execution pipelines which may generate data for storing in a memory, data from the pipelines may be stored in a queue prior to accessing the memory and the system includes circuitry for reordering data from the different pipelines before inserting onto the queue.

Abstract: An expansion adapter is used to communicate both PCI and AGP devices to the north bridge chip of a computer. The expansion adapter includes a first AGP bus control module communicable with the north bridge chip via a first AGP bus, and a second AGP bus control module in communication with the first AGP bus control module, communicable with an AGP device via a second AGP bus. The identifying codes of the first and second AGP bus control modules are set to show no AGP device function in order to allow the AGP device to communicate with the north bridge chip via the expansion adapter. The expansion adapter further includes a PCI bus control module in communication with the PCI device and the first AGP bus control module for controlling data transmission between the first AGP bus control module and the PCI device.

Abstract: A method and apparatus for increasing the performance of communications between a host processor and an interconnected device is provided. The present invention allows data transfers to be performed without requiring frequent interrupts of the host processor by the adapter interconnecting the host processor to the device. In addition, the present invention allows the host to issue commands without writing extensive commands or data to the adapter. Instead, the host is merely required to increment a value held by a register, and to place commands in memory that is local to the host. Furthermore, the present invention allows direct memory access operations to commence even in the absence of receiving confirmation from the device that the device is ready to perform such operations. The present invention is suitable for interconnecting a host system to one or more devices, including in connection with the provisions of a redundant array of inexpensive disks.

Abstract: To optimize the performance of DSL modems in the same cable bundle, the size and position of the bandwidth used for transmission is intelligently selected when the bit rate necessary for making the transmission is less than the total available bandwidth. By intelligently selecting a minimum number of subcarriers for Digital Multi-tone (DMT) signal transmission, a reduction in line driver power consumption is effectuated. Additionally, by intelligently selecting the position of the used bandwidth within the total available bandwidth, near-end crosstalk (NEXT) noise within the cable bundle may be minimized.

Abstract: A Peripheral Component Interconnect (PCI) bridge between two buses prefetches read data into a cache. The number of cache lines to prefetch is predicted by a prefetch counter. One prefetch counter is kept for each type of memory-read command: basic memory-read (MR), memory-read-line (MRL) that reads a cache line, and memory-read-multiple (MRM) that reads multiple cache lines. For each type of read command, counters are kept of the number of completed commands, bus-disconnects (indicating under-fetch), and master-discard of data (indicating over-fetch). After a predetermined number of execution of each type of command, the command's prefetch counter is incremented if under-fetching occurred, or decremented if over-fetching occurred, as indicated by the disconnect and discard counters for that type of read command. The command's other counters are reset. Prefetching is optimized for each type of read command. MRM can prefetch more data than MRL or MR.

Abstract: A system on a chip (SOC) bus architecture may comprise a plurality of masters operable to request communications over a AMBA-type bus. An arbiter may receive requests and burst control signals directly from the masters. The arbiter may determine a burst length associated with a request and may also grant a master allowance to access the bus. The arbiter may configure a multiplexer to couple the granted master to the bus dependent on the determined burst length.

Abstract: An access control unit and method is proposed for use with an SDRAM (Synchronous Dynamic Random-Access Memory) device to control each round of burst-transfer type of access operation on the SDRAM device. The proposed access control unit and method is characterized by that the column-address strobe signal involved in each round of the burst-transfer access operation is continuously set at active state for a period of clock pulses equal in number to the specified burst length of the burst-transfer access operation, rather than just for a period of one pulse. This feature allows external circuitry to arbitrarily change the burst length, and also allows no use of burst-stop command or a precharge-interrupt method to stop each round of the burst-transfer access operation, allowing the access control logic circuit architecture to be more simplified than the prior art.

Abstract: A method of transferring data through a bus includes the steps of: occupying the bus by a first device serving as a bus master; transferring a first predetermined number of data items of all data items to be transferred while the first device is occupying the bus; determining if the first predetermined number of data items have been transferred; determining if the first device should release the bus based on whether or not there is a request from a second device after it is determined that the first predetermined number of data items have been transferred; and releasing the bus by the first deice when it is determined that the first device should release the bus.