Abstract: A semiconductor device includes a substrate, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer is disposed on the substrate, around a first metal interconnection. The second dielectric layer is disposed on the first dielectric layer, around a via and a second metal interconnection. The second metal interconnection directly contacts the first metal interconnection. The third dielectric layer is disposed on the second dielectric layer, around a first magnetic tunneling junction (MTJ) structure and a third metal interconnection. The third metal interconnection directly contacts top surfaces of the first MTJ structure and the second metal interconnection, and the first MTJ structure directly contacts the via.

Abstract: Techniques are provided for implementing garbage collection and bin synchronization for a distributed storage architecture of worker nodes managing distributed storage composed of bins of blocks. As the distributed storage architecture scales out to accommodate more storage and worker nodes, garbage collection used to free unused blocks becomes unmanageable and slow. Accordingly garbage collection is improved by utilizing heuristics to dynamically speed up or down garbage collection and set sizes for subsets of a bin to process instead of the entire bin. This ensures that garbage collection does not use stale information about what blocks are in-use, and ensures garbage collection does not unduly impact client I/O processing or conversely falls behind on garbage collection. Garbage collection can be incorporated into a bin sync process to improve the efficiency of the bin sync process so that unused blocks are not needlessly copied by the bin sync process.

Abstract: Techniques are provided for implementing garbage collection and bin synchronization for a distributed storage architecture of worker nodes managing distributed storage composed of bins of blocks. As the distributed storage architecture scales out to accommodate more storage and worker nodes, garbage collection used to free unused blocks becomes unmanageable and slow. Accordingly garbage collection is improved by utilizing heuristics to dynamically speed up or down garbage collection and set sizes for subsets of a bin to process instead of the entire bin. This ensures that garbage collection does not use stale information about what blocks are in-use, and ensures garbage collection does not unduly impact client I/O processing or conversely falls behind on garbage collection. Garbage collection can be incorporated into a bin sync process to improve the efficiency of the bin sync process so that unused blocks are not needlessly copied by the bin sync process.

Abstract: One example method includes ingesting data to a data protection system, separating, by the data protection system, the ingested data into groups according to Recovery Point Objective (RPO) such that each group is associated with a different respective RPO, storing the groups in respective storage pools, and each of the storage pools is associated with a respective one of the RPOs, and performing a respective garbage collection (GC) process at each storage pool.

Abstract: A serial data buffer integrated circuit comprises unidirectional host-side input and output ports, and unidirectional memory-side input and output ports. Scheduling logic generates memory device commands for writing to and reading from a memory device based on a set of host-side input packets received from a memory controller. A unidirectional serial host side input port receives host-side input packets from the memory controller. A unidirectional serial memory side output port transmits the memory device commands and the write data to the memory device based on the scheduled timing. A unidirectional serial memory side input port receives read data from the memory device in response to a read command, and a unidirectional serial host side output port transmits the read data to the memory controller within the timing constraints of the memory device.

Abstract: A method includes determining a respective number of and respective locations of valid data portions of a plurality of blocks of NAND memory cells, based on the respective locations of the valid data portions, determining respective dispersions of the valid data portions within the plurality of blocks of NAND memory cells, based at least on the respective dispersions, selecting a block of NAND memory cells from the plurality of blocks of NAND memory cells, and performing a folding operation on the selected block.

Abstract: A method and system for initiating a garbage collection request. Historical data representative of a level of initiated I/O requests is acquired. A first operational state and a second operational state are determined based on the historical data. The first operational state and second operational state are expressed in an indication of the level of initiated I/O requests to be processed. A number of currently initiated I/O requests is acquired. A determination is made as to whether the number of currently initiated I/O requests is indicative of the first operational state or the second operational state. If the computer system is in the first operational state, the garbage collection request is initiated.

Abstract: Methods, systems, apparatus, including computer programs encoded on computer storage media, for reclaiming storage space in a storage environment. In one aspect, the method includes actions of aggregating data that is indicative of access to one or more data objects, determining a future storage cost associated with each of a plurality of data objects, determining an access window for each of the plurality of data objects, identifying a data object based on (i) the future storage cost that satisfies a predetermined threshold and (ii) a data object access window, providing a notification to a user device that requests feedback from a user indicating whether the data object can be deleted, and in response to receiving data that indicates that the data object can be deleted, generating an instruction to cause deletion of the data object upon the expiration of the access window.

Abstract: Methods, systems, and devices for data movement based on address table activity are described. A memory system may support a first type of data movement operation and a second type of data movement operation. The memory system may select between the first type of data movement operation and the second type of data movement operation for a region based on address table activity for the region.

Abstract: Endurance mechanisms are introduced for memories such as non-volatile memories for broad usage including caches, last-level cache(s), embedded memory, embedded cache, scratchpads, main memory, and storage devices. Here, non-volatile memories (NVMs) include magnetic random-access memory (MRAM), resistive RAM (ReRAM), ferroelectric RAM (FeRAM), phase-change memory (PCM), etc. In some cases, features of endurance mechanisms (e.g., randomizing mechanisms) are applicable to volatile memories such as static random-access memory (SRAM), and dynamic random-access memory (DRAM). The endurance mechanisms include a wear leveling scheme that uses index rotation, outlier compensation to handle weak bits, and random swap injection to mitigate wear out attacks.

Abstract: A network interface controller (NIC) capable of efficient operation management for host accelerators is provided. The NIC can be equipped with a host interface and triggering logic block. During operation, the host interface can couple the NIC to a host device. The triggering logic block can obtain, via the host interface from the host device, an operation associated with an accelerator of the host device. The triggering logic block can determine whether a triggering condition has been satisfied for the operation based on an indicator received from the accelerator. If the triggering condition has been satisfied, the triggering logic block can obtain a piece of data generated from the accelerator from a memory location and execute the operation using the piece of data.

Abstract: Endurance mechanisms are introduced for memories such as non-volatile memories for broad usage including caches, last-level cache(s), embedded memory, embedded cache, scratchpads, main memory, and storage devices. Here, non-volatile memories (NVMs) include magnetic random-access memory (MRAM), resistive RAM (ReRAM), ferroelectric RAM (FeRAM), phase-change memory (PCM), etc. In some cases, features of endurance mechanisms (e.g., randomizing mechanisms) are applicable to volatile memories such as static random-access memory (SRAM), and dynamic random-access memory (DRAM). The endurance mechanisms include a wear leveling scheme that uses index rotation, outlier compensation to handle weak bits, and random swap injection to mitigate wear out attacks.

Abstract: Methods and systems for managing data in a distributed system are disclosed. The distributed system may include devices used by users (e.g., clients) and devices in which data is stored for future accessibility (e.g., storage providers). A data storage system may manage the data for the clients. To manage the data efficiently, the data storage system may perform an integrated process of both verifying that segments of files believed to be stored are actually stored and segments of files that no longer need to be stored are removed. The process may not be performed in real-time as files that no longer need to be stored are identified (e.g., as deletion requests are received). Rather, the integrated process may employ a garbage collection process where deletion conditions for segments are checked intermittently over time, and files are verified.

Abstract: Systems, architectures, devices, and methods for matching experimentally acquired mass spectrometry data with a peptide database are provided. The system architecture can include a host central processing unit (CPU) system, a bridge connecting the CPU system with a core control register (or registers), a plurality of processing elements (PEs), and a bus arbiter. The PEs can execute the computations in a parallel and asynchronous manner. The bus arbiter can be a first-come first-serve (FCFS)-based bus arbiter (i.e., can utilize an FCFS-based arbitration scheme).

Abstract: According to one embodiment, a memory system determines a write destination block and a write destination location in the write destination block to which write data is to be written, and notifies a host of an identifier of the write data, a block address of the write destination block, and an offset indicative of the write destination location. The memory system retrieves the write data from a write buffer of the host, and writes the write data to the write destination location. In a case where a read command to designate a physical address of first data is received before a write operation of the first data is finished, the memory system reads the first data from the write buffer of the host.

Abstract: Systems, architectures, devices, and methods for matching experimentally acquired mass spectrometry data with a peptide database are provided. The system architecture can include a host central processing unit (CPU) system, a bridge connecting the CPU system with a core control register (or registers), a plurality of processing elements (PEs), and a bus arbiter. The PEs can execute the computations in a parallel and asynchronous manner. The bus arbiter can be a first-come first-serve (FCFS)-based bus arbiter (i.e., can utilize an FCFS-based arbitration scheme).

Abstract: A controller of a memory sub-system can, responsive to providing a command completion signal to a host, mark a portion of a plurality of commands that are addressed to a same logical block of the memory devices, reorder the marked portion of the plurality of commands, wherein write commands from the marked portion of the plurality of commands are given priority over read commands from the marked portion of the plurality of commands, execute a newest write command from the marked portion of the plurality of commands prior to executing read commands, addressed to the same logical block, from the marked portion of the plurality of commands, and execute read commands from the marked portion of the plurality of commands in on an order in which the read commands were received and after the execution of the newest write command, wherein the read commands are executed responsive to an execution of the newest write command.

Abstract: The described technology is generally directed towards fine-grained data event expiration in a streaming data storage system. An event to append is given an expiration period, and the expiration time for the events in a data stream or segment of a data stream is the largest expiration time among events in the data stream or segment. Different segments can have different expiration times for their events. In a segment comprising a group of events, a subgroup of expired events prior to a stream cut are deleted by an expiration task. For a subgroup of unexpired events prior to a stream cut, the expiration task retains (does not delete) the subgroup of events. If a scaling operation is performed on a segment, the new successor segment or segments inherit the largest expiration time of the predecessor segment or segments.

Abstract: Embodiments are directed to a cost-aware object selection for cloud garbage collection that deletes completely dead objects and also selects low-live objects up to a carefully selected liveness threshold value. This threshold is dynamically chosen per cloud garbage collection cycle by balancing costs including egress, input/output operations (IOPs), storage cost of cleaning partial live objects, and the storage cost incurred by leaving behind dead data by not cleaning the object. The threshold value is dynamically calculated to accommodate different cost models for different cloud providers and also caters to different costs for different storage tiers.

Abstract: A product, system, and/or method of managing memory media that includes: determining whether the memory system is low on one or more ready-to-use (RTU) Block Stripes needed to form a RTU Block Stripe Set, wherein the memory media has a plurality of Planes in each Die, all the memory media Blocks in each Block Stripe are from the same Die #and the same Plane #, each Block Stripe Set is formed of a plurality of Block Stripes all from the same Die #, and all the Blocks in each RTU Block Stripe Set have been subject to the removal process and the erasure process. The product, system, and/or method includes: establishing a pending request for a removal process and/or an erasure process for one or more determined Die #/Plane #combinations; and prioritizing in the one or more determined Die #/Plane #combinations one or more memory media Blocks for the removal and/or erasure process.

Abstract: A storage device includes: a memory device including a plurality of system blocks for storing system data; and a memory controller configured to control the memory device to store cyclic system data that is cyclically provided from a host, in an open system block among the plurality of system blocks, and control the memory device to perform a garbage collection operation on the plurality of system blocks, when a size of data stored in the open system block reaches a predetermined size. The cyclic system data may include a plurality of data slices provided from the host at predetermined cycles. The predetermined size may be determined based on size of the cyclic system data provided for a period of time corresponding to a common multiple of the predetermined cycles.

Abstract: Disclosed herein is an integrated circuit including multiple magnetic tunneling junction (MTJ) cells coupled to a static random access memory (SRAM). In one aspect, the integrated circuit includes a SRAM having a first port and a second port, and a set of pass transistors coupled to the first port of the SRAM. In one aspect, the integrated circuit includes a set of MTJ cells, where each of the set of MTJ cells is coupled between a select line and a corresponding one of the set of pass transistors.

Abstract: A storage control system maintains a write cache in a non-volatile memory device of primary memory of a storage node. The write cache comprises a cyclic buffer and pointers to manage the write cache and track a tail location and head location of the write cache. The storage control system receives a write request from a host system, which comprises a data item to be written to primary storage. The received data item is written together with an associated metadata item at the head location of the write cache. The items in the write cache are arranged in a cyclic write order from the tail location to the head location. The storage control system sends an acknowledgment to the host system that the data item is successfully written to the primary storage, in response to the received data item and the associated metadata item being stored in the write cache.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The data storage device supports zoned namespace. The controller is configured to maintain a zone timestamp table that includes a corresponding timestamp for each zone and add a timestamp to each garbage collection block of the memory device. The controller is further configured to scan a garbage collection block from a last physical block address (PBA) entry to a first PBA entry, determine a zone timestamp for the scanned PBA entry, and compare the zone timestamp to a timestamp of the garbage collection block. The controller is further configured to create and maintain a zone timestamp table and create and maintain a zone based defragmentation table.

Abstract: According to one embodiment, a buffer stores first hash values and first complementary data. A first conversion unit converts consecutive characters in a second character string into second hash values and second complementary data. A search unit searches for consecutive first hash values from the buffer, and output a pointer. A selection unit selects consecutive first hash values and pieces of first complementary data from the buffer. A second conversion unit converts the consecutive first hash values into a third character string using the pieces of first complementary data. A comparison unit compares the second character string with the third character string to acquire a matching length. An output unit output the matching length with the pointer.

Abstract: Systems, apparatuses, and methods related to a selectively operable memory device are described. An example method corresponding to a selectively operable memory device can include receiving, by a resistance variable memory device, a command to operate the resistance variable memory device in a first mode or a second mode and operating the resistance variable memory device in the first mode or the second mode based, at least in part, on the received command to perform, in the first mode, a read operation or a write operation, or both, or, in the second mode, a compute operation. The method can further include performing, using a processing unit resident on the resistance variable memory device, the compute operation, the testing operation, or both based, at least in part, on a determination that the resistance variable memory device is operating in the second mode.

Abstract: A method includes determining a respective number of and respective locations of valid data portions of a plurality of blocks of NAND memory cells, based on the respective locations of the valid data portions, determining respective dispersions of the valid data portions within the plurality of blocks of NAND memory cells, based at least on the respective dispersions, selecting a block of NAND memory cells from the plurality of blocks of NAND memory cells, and performing a folding operation on the selected block.

Abstract: A technique performs Redundant Array of Independent Disks (RAID) transformation. The technique involves performing a garbage collection operation on a first uber within a storage array, the garbage collection operation freeing a set of disk slices of the first uber. The technique further involves, upon completing the garbage collection operation, reallocating storage of the set of disk slices from the first uber to a second uber within the storage array. The technique further involves, after the storage of the set of disk slices is reallocated from the first uber to the second uber, storing data within the second uber. Such leveraging of garbage collection when performing RAID transformation reduces overhead and wear without not negatively affecting system performance.

Abstract: A semiconductor device includes a plurality of input/output (I/O) pads; a serial input pad; a serial output pad; a plurality of interface circuits respectively corresponding to the I/O pads; and a plurality of option setting circuits respectively corresponding to the interface circuits, suitable for setting options of the respective interface circuits, wherein the serial input pad, the interface circuits, the option setting circuits, and the serial output pad configure a serial chain.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The data storage device supports zoned namespace. The controller is configured to maintain a zone timestamp table that includes a corresponding timestamp for each zone and add a timestamp to each garbage collection block of the memory device. The controller is further configured to scan a garbage collection block from a last physical block address (PBA) entry to a first PBA entry, determine a zone timestamp for the scanned PBA entry, and compare the zone timestamp to a timestamp of the garbage collection block. The controller is further configured to create and maintain a zone timestamp table and create and maintain a zone based defragmentation table.

Abstract: Embodiments of the present subject matter provide a local profile management method, an embedded universal integrated circuit card, and a terminal. The embedded universal integrated circuit card (eUICC) includes a primary platform and at least one installed bundle. The primary platform is a hardware platform. Each bundle includes at least one profile and an operating system (OS). The primary platform includes a processing module, which is configured to: receive a first message sent by a local profile assistant (LPA), where the first message is an operation instruction entered by a user; and separately send a second message to at least one OS corresponding to the at least one bundle, where the second message is used by the at least one OS to perform a corresponding operation. Local management of profiles of different OSs is implemented by using the processing module disposed on the primary platform of the eUICC.

Abstract: A method and apparatus for sustaining performance of a data storage device by predictively determining resource needs and executing processes to meet those needs before the resources are actually needed. According to certain embodiments, a controller collects commands coming from a host and provides these to a machine learning model such as a recurrent neural network (RNN). The RNN is trained using this data, and output of the trained model is used to predict future commands. As future commands are developed by the RNN, resource allocation processes such as garbage collection may be initiated prior to the actual need, during times when processing cycles in the data storage device are available. By operating the garbage collection when the device has available processing may mitigate transition to an urgent mode.

Abstract: A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.

Abstract: A memory device includes a plurality of groups of memory blocks, each group including a plurality of blocks, and each block including a plurality of memory units. A memory controller for the memory device performs operations including maintaining a count of valid memory units in the group for each group and maintaining a count of valid memory units in each block of the memory device. The operations further include selecting a first group based on a count of valid memory units and the first group including a target plurality of blocks. The operations further include selecting a first target block from the target plurality of blocks, determining whether the first target block is to be erased, and erasing the first target block in response to determining that the first target block is to be erased.

Abstract: Distributing multiply-accumulate currents across segment mirrors by providing a circuit including an array of resistive elements, the array including rows and columns and first stage current mirrors, each of the first stage current mirrors being electrically coupled to a segment, wherein the segment comprises a columnar subset of the resistive elements, providing, by the array, a vector of current outputs equal to an analog vector-matrix product between a vector of voltage inputs to the array and a matrix of analog resistive weights within the array, wherein the voltage inputs encode a vector of analog input values, wherein each row of resistive elements corresponds to a specific voltage input, determining a score for each of the rows, determining a ranking of the rows of the array according to the score of each row, and mapping each row to a segment according to the ranking.

Abstract: During TRIM processing, an apparatus cannot read/write data from/to a semiconductor storage device, and thus cannot perform processing using the device. If the TRIM processing is executed irrespective of a user's intention, the user is to wait for completion of the TRIM processing before performing a desired function of the apparatus. The apparatus includes a nonvolatile storage unit having semiconductor areas, a control unit configured to count a value of at least one type of data, an execution unit configured to execute TRIM processing that notifies the storage unit of an unused area among the semiconductor areas and performs wear leveling on an area in use among the semiconductor areas, and a notification unit configured to provide a notification prompting the execution of the TRIM processing when the counted value of the data satisfies a condition for a threshold.

Abstract: A key-value storage device includes a non-volatile memory (NVM) divided into blocks, and a data buffer including a key buffer, a value buffer and a mapping buffer, and a controller including a key-value manager. The key-value manager receives a command and key-pairs including keys and values respectively corresponding to the keys, separates the keys from the values, store the keys in the key buffer and store the values in the value buffer, generates a value stream by combining a set of values stored in the key buffer, generates a key stream by combining a set of keys and merging indices for values respectively corresponding to the keys in the set of keys, and updates a key matrix stored in the mapping buffer and indicating whether an index among the indices of the key stream is related to each one of the blocks of the NVM.

Abstract: Embodiments of the present disclosure relate to a method, an electronic device, and a computer program product for storage management. According to an example implementation of the present disclosure, a method for storage management includes: acquiring, at a host, a target response entry from a response queue, wherein the response queue includes at least one response entry associated with at least one storage device in a storage system which has been accessed by the host, and the target response entry records information about a target response of a target storage device in the at least one storage device to an access operation initiated by the host; determining, based on the target response entry, whether a failure associated with the target response occurs; and acquiring the target response based on the target response entry if it is determined that no failure occurs. Therefore, the storage performance can be improved.

Abstract: The present disclosure includes apparatuses and methods to change data category values. An example is a memory device that includes an array having a plurality of sequences of memory cells, where each of the respective sequences of memory cells includes a plurality of designated subsets of memory cells, and the array includes a counter corresponding to one of the plurality of designated subsets of memory cells. The memory device is configured to receive input corresponding to a data batch, where the input includes a designation that corresponds to the one of the plurality of designated subsets of memory cells to be conditionally updated, and to change a numerical value stored by the counter corresponding to the one of the plurality of designated subsets of memory cells.

Abstract: A memory device and an operation method thereof are provided. The memory device includes an input/output data latch circuit and a bit line sensing amplifier circuit. The input/output data latch circuit is coupled between a main input/output line pair and a local input/output line pair. The local input/output line pair is coupled to a plurality of bit line pairs through the bit line sensing amplifier circuit. The memory device performs a two-stage operation to input or output data of a selected bit line pair among the bit line pairs. The selected bit line pair connects to the local input/output line pair only during one stage operation of the two-stage operation. Further, during the other stage operation of the two-stage operation, the data of the selected bit line pair latched in the input/output data latch circuit is transmitted to the main input/output line pair.

Abstract: Devices and techniques for memory controller implemented error correction code (ECC) memory are disclosed herein. ECC groups may be placed across banks of the memory. In some examples, an ECC group is a collection of bytes equal to one row in one bank. Also, the placement may restrict a given bank to a single member of the ECC group. A memory operation can be received and executed using the ECC groups.

Abstract: A memory system is disclosed in the present disclosure. The memory system may include at least one first type of memory configured on at least one first rank and to operate at a first frequency, and at least one second type of memory configured on at least one second rank and to operate at a second frequency. The memory system may also include a physical block (PHY) configured to generate a first clock at the first frequency and a second clock at the second frequency.

Abstract: Disclosed are various embodiments for performing a join operation using a graphics processing unit (GPU). The GPU can receive input data including sequences or tuples. The GPU can initialize a histogram in a memory location shared by threads. The GPU can build the histogram of hash values for the sequences. The GPU can reorder the sequences based on the histogram. The GPU can probe partitions and store the results in a buffer pool. The GPU can output the results of the join.

Abstract: A data arrangement method of a flash memory, a flash memory storage device, and a flash memory control circuit unit are provided. The method may be applied to a flash memory, an embedded memory device, or a solid-state disk having a three-dimensional (3D) structure. The method includes: executing a background garbage collection operation in a background mode; receiving at least one write command from a host when the background garbage collection operation is not completed to suspend the background garbage collection operation and exit the background mode; executing the at least one write command; and entering the background mode and continuing the execution of the background garbage collection operation after the at least one write command is completed. Therefore, execution efficiency of the write command in a foreground mode may be optimized.

Abstract: Examples of the present disclosure provide apparatuses and methods related to generating and executing a control flow. An example apparatus can include a first device configured to generate control flow instructions, and a second device including an array of memory cells, an execution unit to execute the control flow instructions, and a controller configured to control an execution of the control flow instructions on data stored in the array.

Abstract: A valid data merging method, a memory storage device and a memory control circuit unit are provided. The method includes: collecting a first valid data in a source unit according to a first logical-to-physical address mapping table recorded in a candidate information, and determining whether a first data amount of the first valid data is same as a second data amount of a valid data corresponding to a valid count of the source unit; in response to determining that they are the same, copying the first valid data to a target unit; and in response to determining that they are not the same, obtaining one or more second logical-to-physical address mapping table according to a management information of the source unit to collect a second valid data in the source unit, and copying the second valid data to the target unit.

Abstract: A memory macro system may be provided. The memory macro system may comprise a first segment, a second segment, a first WL, and a second WL. The first segment may comprise a first plurality of memory cells. The second segment may comprise a second plurality of memory cells. The first segment may be positioned over the second segment. The first WL may correspond to the first segment and the second WL may correspond to the second segment. The first WL and the second WL may be configured to be activated in one cycle.

Abstract: A method may include transferring data between a host and a first storage device through a first storage interface, transferring data between the host and a second storage device through a second storage interface, and transferring data between the first storage device and the second storage device through a peer-to-peer channel. A storage system may include a host interface, a first storage device having a first storage interface coupled to the host interface, a second storage device having a second storage interface coupled to the host interface, and a peer-to-peer bus coupled between the first and second storage devices. A storage device may include a storage medium, a storage device controller coupled to the storage medium, a storage interface coupled to the storage device controller, and a peer-to-peer interface coupled to the storage device controller.

Abstract: Technologies for directly performing read and write operations on matrix data in a data storage device are disclosed. The data storage device receives a request to perform a read or write operation on matrix data stored in one or more memory units of the data storage device. Each memory unit is associated with a column address for the matrix data. The data storage device determines whether the request specifies to read or write a column or a row in the matrix data. The data storage device performs, in response to a determination that the request specifies to read or write a column in the matrix data, the read or write operation on the matrix data on the column.

Abstract: An information handling system (IHS) unambiguously addresses networked devices connected by a local area network (LAN) based network interface controller (NIC) by detecting a device descriptor of LAN-based NIC, determining that the device descriptor indicates a capability for assigning a reserve media access control (MAC) address to the networked device, writing the reserve MAC address in the LAN-based NIC of the networked device, and associating the reserve MAC address with the networked device in an inventory data structure for the IHS.