Abstract: A flash controller for managing at least one MLC non-volatile memory module and at least one SLC non-volatile memory module. The flash controller is adapted to determine if a range of addresses listed by an entry and mapped to said at least one MLC nonvolatile memory module fails a data integrity test. In the event of such a failure, the controller remaps said entry to an equivalent range of addresses of said at least one SLC non-volatile memory module. The flash controller is further adapted to determine which of the blocks in the MIX and SLC nonvolatile memory modules are accessed most frequently and allocating those blocks that receive frequent writes to the SLC non-volatile memory module and those blocks that receive infrequent writes to the MLC non-volatile memory module.

Abstract: The invention introduces a method for performing data writes into a flash memory, at least including the steps: determining whether at least one host write command that requires to process immediately is presented in a submission queue (SQ) before performing a portion of a Host-Flash mapping (H2F) table update or a GC process; and executing the host write command that requires to process immediately in a batch and then performing the portion of the H2F table update or the GC process when the determination is positive.

Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.

Abstract: Techniques including a memory controller with a set of memory channel queues, wherein memory channel queues of the set of memory channel queues correspond to memory channels to access a set of memory modules, a first arbitration module, and a second arbitration module. The memory controller is configured to receive a first memory request from the peripheral and place one or more portions of the first memory request in the memory channel queues of the set of memory channel queues. The first arbitration module is configured to determine an arbitration algorithm, select a first memory channel queue based on the arbitration algorithm, present the one or more portions of the first memory request in the selected first memory channel queue to the second arbitration module, and output the presented one or more portions of the first memory request based on a selection by the second arbitration module.

Abstract: Systems and methods are provided for master-to-master OT-based artifact peering. A “master-to-master” architecture for artifacts is implemented in a network comprising a plurality of nodes and clients, where no node is designated a “master” or “primary” for a given artifact. A first node receives a subset of remote proposed operations from a second node and determines if a conflict exists between the received subset of remote proposed operations and at least one of a plurality of locally-proposed operations. The first node resolves the conflict based on a total-ordering agreed upon between the first node and the second node. The first node transforms at least one operation, either received or locally-proposed, based on the resolved conflict. The first node than updates a local log to include the transformed operation.

Abstract: Embodiments of the present disclosure relate to a system and an operating method of the system. Based on some embodiments of the disclosed technology, the system may include a random access memory structured to include memory cells to store data, a cache memory configured to cache at least part of the data, and a processor in communication with the random access memory and the cache memory to access at least part of the data from the random access memory or cache memory. The system may determine a cache hit ratio for the cache memory, and may set an operating frequency of the random access memory based on the cache hit ratio.

Abstract: Methods, systems, and devices for strategic power mode transition in a multi-memory device are described. A controller may receive, from a host device, a command indicating that the controller is to transition a volatile memory and a non-volatile memory from respective deep sleep modes. In a first example, the controller may respond to the command by transitioning the volatile memory to a standby power mode for the volatile memory and transitioning the non-volatile memory to an intermediate power mode for the non-volatile memory that consumes less power than a standby mode for the non-volatile memory. In a second example, the controller may respond to the command by transitioning the volatile memory to the standby power mode for the volatile memory and maintain the non-volatile memory in the deep sleep mode until a condition, such as a miss, occurs.

Abstract: Various examples are directed to devices and methods involving a host device and a memory system, the memory system comprising a memory controller and a plurality of memory locations. The memory system may send to the host device a first message describing background operations to be performed at the memory system. The memory system may receive from the host device a second message indicating permission to execute the background operations and may begin to execute at least one background operation.

Abstract: Systems and methods for managing multiple voice assistants are disclosed. Audio input is received via one or more microphones of a playback device. A first activation word is detected in the audio input via the playback device. After detecting the first activation word, the playback device transmits a voice utterance of the audio input to a first voice assistant service (VAS). The playback device receives, from the first VAS, first content to be played back via the playback device. The playback device also receives, from a second VAS, second content to be played back via the playback device. The playback device plays back the first content while suppressing the second content. Such suppression can include delaying or canceling playback of the second content.

Abstract: Methods, systems, and devices for monitoring and reporting a status of a memory device are described. A memory device may include monitoring circuitry that may be configured to monitor health and wear information for the memory device. A host device may write to a dedicated register of the memory device, to configure the memory device with health status information reporting parameters. The memory device may monitor and report the health status information of the memory device based on the received reporting configuration or based on a default configuration, and may write one or more values indicative of the health status information to a dedicated register. The host device may perform a read on the readout register to obtain the health status information, as indicated by the one or more values, and may adjust operating procedures or take other actions based on the received health status information.

Abstract: A priority queue including an order of local data relocation operations to be performed by a plurality of solid-state storage devices is maintained. An indication of a new local data relocation operation is received from a solid-state storage device of the plurality of solid-state storage devices for data stored at the solid-state storage device, the indication including information associated with the data. The new local data relocation operation is inserted into a position in the order of the priority queue based on the information associated with the data.

Abstract: Various implementations described herein are directed to device having a memory array that operates with an applied core voltage. The device includes a power gating switch that receives a core supply voltage and provides the applied core voltage to the memory array. The device includes a biasing stage that selectively activates the power gating switch based on sensing a changing voltage level of the applied core voltage.

Abstract: A method includes receiving a write request to a write queue of a host having the write queue and a read queue; initiating a write queue timer upon receiving the write request to the write queue of the host, wherein the write queue timer has a write queue timer expiry threshold value; and executing one or more write requests when the write queue timer reaches the write queue timer expiry threshold value.

Abstract: A storage device comprising: a nonvolatile memory device including a plurality of memory blocks; and a device controller configured to control the nonvolatile memory device to determine a memory block to perform a refresh operation and to control the memory block to perform the refresh operation to recover data of the memory block.

Abstract: A storage unit has one or more processing devices, a solid-state drive and an open blocks cache memory. The open blocks cache memory holds open blocks of data or metadata and holds closed blocks of data or metadata pending writing to the solid-state drive. Closed blocks of data or metadata are written to the solid-state drive and open blocks of data or metadata are written to the open blocks cache memory. Values for open blocks in the open blocks cache memory are tracked. The values are adjusted in a first direction when an open block is written to the open blocks cache memory, and the values are adjusted in a second direction when an open block in the open blocks cache memory is closed and written from the open blocks cache memory to the solid-state drive.

Abstract: An operating method of a storage device is provided. The operating method includes: receiving a host read command from a host device; identifying whether a read path corresponding to the host read command corresponds to a first direct memory access (DMA) read path; and directly outputting, by a host DMA manager, read data stored in an output buffer of an error correction circuit to the host device based on the read path corresponding to the first DMA read path.

Abstract: An electronic device includes circuitry and a plurality of ports. The plurality of ports includes an input port and an output port, configured to communicate data units with one or more other devices across a fabric of a System on a Chip (SoC), the data units include N data bits, N being an integer larger than 1. The circuitry is configured to receive an input data unit via the input port, to make a random decision of whether to invert the N data bits in the input data unit, to produce an output data unit by retaining or inverting the N data bits of the input data unit based on the random decision, and to send the output data unit via the output port.

Abstract: A memory system includes a first volatile memory having an access unit of a first bit width; a second volatile memory having an access unit of the first bit width and having a capacity larger than the first volatile memory; and a controller connected to the first and second volatile memories. The controller allocates a first address space having the first bit width as a unit to the first volatile memory, allocates a second address space having the first bit width as a unit to the second volatile memory, selects at least one of the first and second volatile memories based on a first address indicating a position in a third address space having a second bit width as a unit, calculates a second address in the address space allocated to the selected volatile memory, and accesses a position corresponding to the second address of the selected volatile memory.

Abstract: A cache includes an upstream port, a cache memory for storing cache lines each having a line width, and a cache controller. The cache controller is coupled to the upstream port and the cache memory. The upstream port transfers data words having a transfer width less than the line width. In response to a cache line fill, the cache controller selectively determines data bus inversion information for a sequence of data words having the transfer width, and stores the data bus inversion information along with selected inverted data words for the cache line fill in the cache memory.

Abstract: Techniques for sending Compute Express Link (CXL) packets over Ethernet (CXL-E) in a composable data center that may include disaggregated, composable servers. The techniques may include receiving, from a first server device, a request to bind the first server device with a multiple logical device (MLD) appliance. Based at least in part on the request, a first CXL-E connection may be established for the first server device to export a computing resource to the MLD appliance. The techniques may also include receiving, from the MLD appliance, an indication that the computing resource is available, and receiving, from a second server device, a second request for the computing resource. Based at least in part on the second request, a second CXL-E connection may be established for the second server device to consume or otherwise utilize the computing resource of the first server device via the MLD appliance.

Abstract: A method and memory device of controlling a plurality of low power states are provided. The method includes: entering a low power mode state, in which memory cell rows of the memory device are refreshed and power consumption is lower than in a self-refresh mode state, in response to a low power state entry command; and exiting the low power mode state based on a low power mode exit latency time that is set in a mode register of the memory device or at least one of an alarm signal and a low power mode exit command.

Abstract: A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount of data being less than a product of the external signal path bandwidth and the minimum access time interval.

Abstract: Various embodiments provide for one or more processor instructions and memory instructions that enable a memory sub-system to copy, move, or swap data across (e.g., between) different memory tiers of the memory sub-system, where each of the memory tiers is associated with different memory locations (e.g., different physical memory locations) on one or more memory devices of the memory sub-system.

Abstract: The present disclosure includes apparatuses and methods related to performing background operations in memory. A memory device can be configured to perform background operations while another memory device in a memory system and/or on a common memory module is busy performing commands received from a host coupled to the memory system and/or common memory module. An example apparatus can include a first memory device, wherein the first memory device can include an array of memory cells and a controller configured to perform a background operation on the first memory device in response to detecting a command from a host to a second memory device.

Abstract: An information processing apparatus includes a detection unit and first and second classification units. The detection unit detects an event which causes a state of at least one bank constituting dynamic random access memory (DRAM) to transition. The first classification unit classifies the at least one bank state based on the detected event. The second classification unit classifies a DRAM state based on the at least one bank state. Statistical information that is based on the at least one bank or DRAM state is displayed with respect to a predetermined unit time. The at least one bank state and the DRAM state each includes at least one of the following: an operating state, in which data is being transferred, an inoperative state, in which data transfer is not possible due to a predetermined constraint, or a pause state, in which, although there is no constraint, data is not being transferred.

Abstract: Methods, apparatuses, and systems for in- or near-memory processing are described. Strings of bits (e.g., vectors) may be fetched and processed in logic of a memory device without involving a separate processing unit. Operations (e.g., arithmetic operations) may be performed on numbers stored in a bit-serial way during a single sequence of clock cycles. Arithmetic may thus be performed in a single pass as numbers are bits of two or more strings of bits are fetched and without intermediate storage of the numbers. Vectors may be fetched (e.g., identified, transmitted, received) from one or more bit lines. Registers of the memory array may be used to write (e.g., store or temporarily store) results or ancillary bits (e.g., carry bits or carry flags) that facilitate arithmetic operations. Circuitry near, adjacent, or under the memory array may employ XOR or AND (or other) logic to fetch, organize, or operate on the data.

Abstract: The present disclosure includes apparatuses and methods for cache operations. An example apparatus includes a memory device including a plurality of subarrays of memory cells, where the plurality of subarrays includes a first subset of the respective plurality of subarrays and a second subset of the respective plurality of subarrays. The memory device includes sensing circuitry coupled to the first subset, the sensing circuitry including a sense amplifier and a compute component. The first subset is configured as a cache to perform operations on data moved from the second subset. The apparatus also includes a cache controller configured to direct a first movement of a data value from a subarray in the second subset to a subarray in the first subset.

Abstract: A data accessing method using dynamic speed adjustment with aid of a thermal control unit, and associated apparatus such as memory device, memory controller, etc. are provided. The data accessing method includes: utilizing a thermal control unit to start monitoring temperature at a predetermined intra-controller location of the memory controller; in response to at least one accessing request from a host device, controlling a transmission interface circuit to perform data transmission between the host device and the memory controller at an original communications speed, for accessing data in the NV memory; in response to the temperature being greater than a first temperature threshold, detecting an increment of the temperature between a first start time point and a first end time point; based on at least one first predetermined rule, determining a first communications speed according to the increment; and switching from the original communications speed to the first communications speed.

Abstract: An information processing apparatus which implements a rebuild process for restoring a mirroring state even when each of a plurality of connected external storage devices is configured to input and output data to and from a host controller by accessing a storage area of the host controller. When the host controller has issued an instruction to carry out the rebuild process in which data in one of the external storage devices is copied to the other one, one of the external storage devices which is about to write data to the storage area of the host controller for the rebuild process is caused to write the data to the buffer provided in the bridge device, and the other one which is about to read data from the storage area of the host controller for the rebuild process is caused to read the data from the buffer.

Abstract: An example method includes determining a time between writes in place to a particular memory cell, incrementing a disturb count corresponding to a neighboring memory cell by a particular count increment that is based on the time between the writes to the particular memory cell, and determining whether to check a write disturb status of the neighboring memory cell based on the incremented disturb count.

Abstract: Examples disclosed herein are relevant to systems, methods, and other technology for determining furniture compatibility. For example, graph neural networks (GNNs) that leverage relational information between furniture items in a set may be used as models to predict a compatibility score indicative of visual compatibility of furniture items across the set. In one implementation, the GNN-based model can extend the concept of a siamese network to multiple inputs and branches and use a generalized contrastive loss function. In another implementation, the GNN-based model learns both an edge function and the function that generates the compatibility score. The predicted compatibility score can be used for a variety of purposes, including furniture item recommendations.

Abstract: A semiconductor memory device includes a plurality of memory bank groups configured to be accessed in parallel; an internal memory bus configured to receive external data from outside the plurality of memory bank groups; and a first computation circuit configured to receive internal data from a first memory bank group of the plurality of memory bank groups during each first period of a plurality of first periods, receive the external data through the internal memory bus during each second period of a plurality of second periods, the second period being shorter than the first period, and perform a processing in memory (PIM) arithmetic operation on the internal data and the external data during each second period.

Abstract: A system for performing cascading search includes an associative memory array, a controller, a similarity search processor and an exact match processor. The associative memory array stores a plurality of multiportion data vectors stored in at least one column of the associative memory array. Each vector has a first portion and a second portion which are aligned to each other in the column. The controller controls the associative memory array to perform a similarity search of a similarity query on the first portion and an exact search of an exact query on the second portion. The similarity match processor generates a match row including match bit indications aligned with each similarity matched column. The match row indicates which columns have first portions which match to the similarity query. The exact match processor outputs exact match columns from among the similarity matched columns which have second portions which match the exact query.

Abstract: A memory controller includes a memory channel controller that uses multiple groups of command queue and arbiter pairs. Each arbiter is coupled to a respective command queue to select memory access commands from each command queue according to predetermined criteria. Each arbiter selects from among the memory access requests in each command queue independently based on the predetermined criteria and sends selected memory access requests to a selector that serves as a second level arbiter which sends the request to a memory subchannel.

Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.

Abstract: Methods, systems, and devices for reset verification in a memory system are described. In some examples, a memory device may perform a reset operation and set a mode register to a first value based on performing the reset operation. The first value may be associated with a successful execution of the reset command. The memory device may transmit an indication to a host device based on determining the first value. The host device may determine from the received indication or from the first value stored in the mode register that the first value is associated with the successful execution of the reset command. Thus, the memory device, or the host device, or both may be configured to verify whether the reset operation is successful.

Abstract: A garbage collection assisted deduplication process determines whether or not data segments should be deduplicated or not based on the liveness of segment data in a region, and the number of segments subject to deduplication in the region. Ingested data is divided into a plurality of segments, and a fingerprint is calculated for each segment. An index table entry maps a fingerprint to a region and container ID, and a perfect hash vector is setup for this mapping. A percentage of live segments in the region relative to a liveness threshold is determined, as is a number of segments in the region subject to deduplication relative to a deduplication threshold. If a region is sufficiently live, deduplication is performed, but if the region is dead, deduplication is not performed. For a live region, if the number of deduplicated segments is too low, deduplication is not performed.

Abstract: A transaction-based hybrid memory device includes a host memory controller to control operation of the device. A hybrid memory controller is coupled to the host memory controller over a memory bus. The hybrid memory controller includes non-volatile memory control logic to control operation of non-volatile memory devices and cache control logic to accelerate cache operations, a direct memory access (DMA) engine to control volatile cache memory and to transfer data between non-volatile memory, and cache memory to off load host cache managements and transactions. A host interface couples the host memory controller to the memory bus.

Abstract: A memory processor-based multiprocessing architecture and an operation method thereof are provided. The memory processor-based multiprocessing architecture includes a main processor and a plurality of memory chips. The memory chips include a plurality of processing units and a plurality of data storage areas. The processing units and the data storage areas are respectively disposed one-to-one in the memory chips. The data storage areas are configured to share a plurality of sub-datasets of a large dataset. The main processor assigns a computing task to one of the processing units of the memory chips, so that the one of the processing units accesses the corresponding data storage area to perform the computing task according to a part of the sub-datasets.

Abstract: A data storage apparatus is provided to include a storage including a main data region for storing first data and a spare region for storing second data indicating attributes of the first data; and a controller in communication with a host and configured to control the storage based on a request from the host, wherein the controller comprises: a first error check and correction (ECC) engine configured to perform an error correction on the first data stored in the main data region of the storage; and a second ECC engine configured to perform an error correction on the second data stored in the spare region of the storage.

Abstract: Methods, systems, and apparatuses related to runtime selection of memory devices and storage devices in a disaggregated memory system are described. For example, a controller can be coupled to a plurality of memory device and a plurality of storage devices. The controller can receive signaling indicative of a memory request corresponding to execution of an application. Responsive to receiving the signaling indicative of the memory request, the controller can select a memory device or a storage device, or both, selecting from the plurality of memory devices or the plurality of storage devices, or both, to perform a memory operation associated with the memory request. Responsive to receiving the memory request and selecting the memory device or the storage device, or both, the controller can perform the memory operation using the selected memory device or the selected storage device, or both.

Abstract: Technologies for secure device configuration and management include a computing device having an I/O device. A trusted agent of the computing device is trusted by a virtual machine monitor of the computing device. The trusted agent securely commands the I/O device to enter a trusted I/O mode, securely commands the I/O device to set a global lock on configuration registers, receives configuration data from the I/O device, and provides the configuration data to a trusted execution environment. In the trusted I/O mode, the I/O device rejects a configuration command if a configuration register associated with the configuration command is locked and the configuration command is not received from the trusted agent. The trusted agent may provide attestation information to the trusted execution environment. The trusted execution environment may verify the configuration data and the attestation information. Other embodiments are described and claimed.

Abstract: Memory controller systems, methods and apparatus for memory access and scheduling are herein disclosed. In some aspects, a memory controller includes a clock, a first interface to be coupled with a first memory device via a common memory channel, and a second interface to be coupled with a second memory device via the common memory channel. The memory controller also includes a register to store data to store data to indicate an access scheme to process access requests to the first memory device according to a first timing scheme and issue access requests to the second memory device according to a second timing scheme. The memory controller further includes logic to cause the access scheme to be implemented in order to issue access requests to the first memory device or to issue access requests to the second memory device via the common memory channel.

Abstract: Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s).

Abstract: A method of transferring data between a memory controller and at least one memory module via a primary data bus having a primary data bus width is disclosed. The method includes accessing a first one of a memory device group via a corresponding data bus path in response to a threaded memory request from the memory controller. The accessing results in data groups collectively forming a first data thread transferred across a corresponding secondary data bus path. Transfer of the first data thread across the primary data bus width is carried out over a first time interval, while using less than the primary data transfer continuous throughput during that first time interval. During the first time interval, at least one data group from a second data thread is transferred on the primary data bus.

Abstract: Examples relate to a processor apparatus, device, method and computer program, to a memory performance controller apparatus, device, method and computer program and to a memory controller apparatus, device, method and computer program. The processor apparatus comprises interface circuitry for communicating with other components of the computer system. The processing circuitry is configured to provide an interface for controlling a memory performance requirement of a data structure stored within a memory of the computer system. The memory performance requirement is a percentile-based memory performance requirement comprising at least a first memory performance requirement valid for a first portion of access operations and a second memory performance requirement valid for a second portion of access operations.

Abstract: A method for accessing a dynamic memory module, the method may include (i) receiving, by a memory controller, a set of access requests for accessing the dynamic memory module; (ii) converting the access requests to a set of commands, wherein the set of commands comprise (a) a first sub-set of commands that are related to a first group of memory banks, and (b) a second sub-set of commands that are related to a second group of memory banks; (iii) scheduling, by a scheduler of the memory controller, an execution of the first sub-set; (iv) scheduling an execution of the second sub-set to be interleaved with the execution of the first sub-set; and (v) executing the set of commands according to the schedule.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for staggering the timing of targeted refresh operations. A memory device may include a number of memory banks, at least some of which may be simultaneously entered into a refresh mode. A given memory bank may perform an auto-refresh operation or a targeted refresh operation, which may draw less power than the auto-refresh operation. The timing of the targeted refresh operations may be staggered between the refreshing memory banks, such that a portion of the refreshing memory banks are performing a targeted refresh operation simultaneously with a portion of the refreshing memory banks performing an auto-refresh operation.

Abstract: An information processing system, a computer readable storage medium, and a computer-implemented method, collect tables from a corpus of documents, convert the collected tables to flattened table format and organized to be searchable by schema-less queries. A method collects tables, extracts feature values from collected table data and collected table meta-data for each collected table. A table classifier classifies each collected table as being a type of table. Based on the classifying, the collected table is converted to a flattened table including table values that are the table data and the table meta-data of the collected table. Dependencies of the data values are mapped. The flattened table and mapped dependencies are stored in a triple store searchable by schema-less queries. The table classifier learns and improves its accuracy and reliability. Dependency information is maintained among a plurality of database tables. The dependency information can be updated at variable update frequency.

Abstract: For one or more stages of execution of a software application at a first processor, a remap vector of a second processor is reconfigured to represent a dynamic mapping of virtual address groups to physical address groups for that stage. Each bit position of the remap vector is configured to store a value indicating whether a corresponding virtual address group is actively mapped to a corresponding physical address group. Address translation operations issued during a stage of execution of the software application are selectively processed based on the configuration of the remap vector for that stage, with the particular value at the bit position of the remap vector associated with the corresponding virtual address group controlling whether processing of the address translation operation is continued to obtain a virtual-to-physical address translation sought by the address translation operation or processing of the address translation operation is ceased and a fault is issued.