Abstract: A memory device including: a memory cell array including memory cell rows; and a control logic circuit to perform a row, write, read, or pre-charge operation on the memory cell rows in response to an active, write, read, or pre-charge command, wherein the control logic circuit is further configured to: calculate a first count value by counting the active command and a second count value by counting the write command or the read command, with respect to a first memory cell row, during a row hammer monitor time frame; determine a type of row hammer of the first memory cell row based on a ratio of the first count value to the second count value; and adjust a pre-charge preparation time between an active operation and the pre-charge operation, by changing a pre-charge operation time point according to the determined type of row hammer.

Abstract: A memory device includes a memory cell array including a plurality of memory cells connected to a plurality of wordlines and a plurality of bitlines, a target row refresh logic circuit configured to select a target row address from among a plurality of target row addresses as a refresh row address based on victim point values, and perform a refresh operation on first memory cells of the plurality of memory cells connected to a wordline of the plurality of wordlines indicated by the refresh row address, a victim point table configured to store the victim point values for the target row addresses, and a victim point accumulator configured to receive a first row address from an external device, and accumulate a first victim point value for at least one target row address corresponding to the first row address during a unit time period.

Abstract: A memory adaptive temperature controlling method, a storage device, and a control circuit unit are provided. In this exemplary embodiment, the temperature value is obtained according to the temperature measured by the thermal sensor, and the access speed to be reached is calculated according to the temperature change rate within the specific time range and the adjustment percentage when it is determined that the speed-down or speed-up operation is required to be performed. By adjusting the access speed of the memory storage device in a stepwise manner, the temperature of the memory storage device may be stabilized, thereby striking the balance between the temperature stability and the system performance of the memory storage device.

Abstract: A memory control apparatus controls access to a DRAM having a plurality of banks. The apparatus comprises a first generating unit configured to generate an access command in accordance with an access request for the DRAM and store the access command in a buffer; a second generating unit configured to generate a bank-designated refresh request for the DRAM; and an issuing unit configured to issue a DRAM command to the DRAM based on an access command stored in the buffer and a refresh request generated by the second generating unit. The second generating unit determines a bank for which the refresh request is generated, based on an access time for each bank of the DRAM by not less than one access command stored in the buffer.

Abstract: A semiconductor memory apparatus includes a first memory cell array, a second memory cell array, and a hammering control circuit. The first memory cell array includes a first row hammer memory cell. The second memory cell array includes a second row hammer memory cell. The hammering control circuit controls the number of active operations on a first word line to be stored in the second row hammer memory cell and controls the number of active operations on a second word line to be stored in the first row hammer memory cell.

Abstract: A memory controller includes: a security level setting circuit suitable for setting a security level by monitoring a risk of a row hammer attack; and a refresh management command control circuit suitable for controlling the number of times that a refresh management command is to be applied to a memory per unit time according to the security level.

Abstract: A memory system includes: a normal memory area suitable for storing normal data; a security memory area suitable for storing security data; a first row hammer detection circuit suitable for sampling and counting a portion of rows that are activated in the normal memory area to select first rows that need to be refreshed; and a second row hammer detection circuit suitable for counting all rows that are activated in the security memory area to select second rows that need to be refreshed.

Abstract: Apparatuses, systems, and methods for refresh modes. A memory may need to perform targeted refresh operations to refresh the ‘victim’ word lines which are near to frequently accessed ‘aggressor’ word lines. To refresh the victims at a high enough rate, it may be desirable to refresh multiple victims as part of the same refresh operation. However, certain word lines (e.g., word lines in a same section or adjacent sections of the memory) cannot be refreshed together. The memory may have a section comparator, which may check stored aggressor addresses and may provide a signal if there are not two stored addresses which can be refreshed together. Based, in part, on the signal, the memory may activate one of several different refresh modes, which may control the types of refresh operation performed responsive to a refresh signal.

Abstract: A memory controller interfaces with a random access memory over a memory channel. A refresh control circuit monitors an activate counter which counts a rolling number of activate commands sent over the memory channel to a memory region of the memory. In response to the activate counter being above an intermediate management threshold value, the refresh control circuit only issue a refresh management (RFM) command if there is no REF command currently held at the refresh command circuit for the memory region.

Abstract: A method of operating a memory device includes; receiving a refresh command, performing a refresh operation on a target row of a bank memory array, and providing status information to a memory controller for an adjacent row, relative to the target row, during a refresh operation period defining a refresh operation performed by the memory device.

Abstract: A method and system for memory attack mitigation in a memory device includes receiving, at a memory controller, an allocation of a page in memory. One or more device controllers detects an aggressor-victim set within the memory. Based upon the detection, an address of the allocated page is identified for further action.

Abstract: A semiconductor memory device having a flexible refresh skip area includes a memory cell array including a plurality of rows to store data, a row decoder connected to the memory cell array, a refresh area storage unit to store a beginning address and an end address of a memory area that is to be refreshed in which the memory area that is to be refreshed does not include a refresh skip area having a size is selectively and/or adaptively changed, and a refresh control circuit connected to the row decoder and the refresh area storage unit. The refresh control circuit controls a refresh operation for the area that is to be refreshed and not for the refresh skip area.

Abstract: A memory controller may include: a request checker identifying memory devices corresponding to requests received from a host among the plurality of memory devices and generating device information on the identified memory devices to perform operations corresponding to the requests; a dummy manager outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse. A memory controller may include an idle time monitor outputting an idle time interval of the memory device and a clock signal generator generating a clock signal based on the idle time interval and outputting the clock signal to the memory device through the channel to perform a current operation.

Abstract: A memory controller interfaces with a dynamic random access memory (DRAM). The memory controller selectively places memory commands in a memory interface queue and transmits the memory commands from the memory interface queue to a memory channel coupled to at least one dynamic random access memory (DRAM). An activate counter is maintained related to a number of activate commands sent over the memory channel to a memory region of the DRAM. In response to the activate counter being at or above a designated threshold, an arbiter is signaled that a refresh command should be sent to the memory region. In response to a designated condition, a value of the activate counter is adjusted by a total number based on a first fixed number and second varying number selected with one of random selection and pseudo-random selection.

Abstract: An electronic device includes a memory device and a timing controller configured to output control signals, which are generated using a first clock signal, to the memory device, generate first captured data by capturing data, which is output from the memory device, using the first clock signal in response to the control signals, and generate control signals using a second clock signal and output the control signals to the memory device when the first captured data is not valid data.

Abstract: Methods, apparatuses, and systems related to managing operations performed in response to refresh management (RFM) commands. A controller generates the RFM command for coordinating a refresh management operation targeted for implementation at an apparatus. The apparatus tracks refresh target set that includes refresh management target locations within the apparatus. According to the tracked refresh management target set, the apparatus selectively implements the targeted refresh management operation and/or a response operation in addition to or as a replacement for the targeted refresh management operation.

Abstract: A memory controller for a (DRAM) memory processes an (access) command for a target row in the memory, increments a count value for each victim row associated with the target row, and issues a (dummy activate) command for a victim row whose count value reaches a specified threshold. By tracking victim rows instead of target rows, the memory controller can thwart both single-sided and double-sided row-hammer attacks. The memory controller maintains the victim-row addresses and corresponding command counts in a TCAM memory to detect rows that may be prone to row-hammer attacks. If so, then the memory controller issues dummy activate commands to the corresponding memory rows to thwart such row-hammer attacks.

Abstract: A system and method of indexing documents to support frequent field updates without reindexing may include receiving, from an indexing application, first fields from a document to be indexed. The method may also include receiving, from the indexing application, second fields from the document to be indexed. The first fields are to an index file associated with the indexing application. The index file comprises a directory wrapper around at least a portion of a file system for the indexing application, wherein the wrapper (i) provides indications of when the in-memory file is flushed to the file system, and (ii) controls synchronization of the file system and a data store. The method may further include writing the second fields to a reverse index.

Abstract: A computer-implemented method of managing online bookings for transportation services inventory is provided. The computer-implemented method links, via a computerized network, each item in the transportation services inventory with one of a plurality of online distributions channels by allocating the item to the respective online distribution channel. Furthermore, the computer-implemented method receives, from each of a plurality of online distribution channels in real time via the computerized network, sale data pertaining to the online bookings for the items in the transportation services inventory allocated to the respective online distribution channel. The computer-implemented method processes the sale data by carrying out calculations to obtain a performance rating for each of the respective online distribution channels.

Abstract: The present disclosure includes apparatuses and methods related to refresh circuitry. An example apparatus can include a memory array including a main portion and a redundant portion. The apparatus can include refresh circuitry configured to, responsive to a determination of a hammering event, refresh at least a portion of the redundant portion.

Abstract: Apparatuses and methods related to row hammer mitigation in, for example, a memory device or a computing system that includes a memory device. Data from a group of memory cells of a memory array can be latched in sensing circuitry responsive to a determination of a hammering event associated with the group of memory cells. Thereafter, the data can be accessed from the sensing circuitry.

Abstract: A power control circuit includes a power control signal generation circuit configured to generate a voltage control signal according to a deep sleep command for operating a semiconductor apparatus in a deep sleep mode; a voltage divider circuit having a division ratio that is changed according to the voltage control signal, and configured to generate a divided voltage by dividing an internal voltage at the changed division ratio; a comparator configured to generate a detection signal by comparing a reference voltage to the divided voltage; an oscillator configured to generate an oscillation signal according to the detection signal; and a pump configured to generate the internal voltage according to the oscillation signal.

Abstract: A memory controller may control a memory device. The memory device may be coupled to the memory controller through a channel. The memory controller may include an idle time monitor and a clock signal generator. The idle time monitor may output an idle time interval of the memory device. The idle time interval may be between an end time of a previous operation of the memory device and a start time of a current operation. The clock signal generator may generate a clock signal based on the idle time interval and output the clock signal to the memory device through the channel to perform a current operation.

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells and, more particularly, a temperature update for a memory device are described. A memory array may be operated according to a timing cycle that includes a first interval for performing a first type of operation and a second interval for performing a second type of operation, where a duration of the first interval is greater than a duration of the second type of interval. A temperature related to a temperature of at least a portion of the memory array may be sampled during an interval of the second type, and the memory array may be reconfigured based at least in part on a sampled temperature. The first type of operation may then be performed on a reconfigured memory array during an interval of the first type.

Abstract: A method and apparatus physically partitions clean and dirty cache lines into separate memory partitions, such as one or more banks, so that during low power operation, a cache memory controller reduces power consumption of the cache memory containing the clean only data. The cache memory controller controls a refresh operation so that a data refresh does not occur for the clean data only banks or the refresh rate is reduced for the clean data only banks. Partitions that store dirty data can also store clean data; however, other partitions are designated for storing only clean data so that the partitions can have their refresh rate reduced or refresh stopped for periods of time. When multiple DRAM dies or packages are employed, the partition can occur on a die or package level as opposed to a bank level within a die.

Abstract: A memory controller interfaces with a dynamic random access memory (DRAM) over a memory channel. A refresh control circuit monitors an activate counter which counts a rolling number of activate commands sent over the memory channel to a memory region of the DRAM. In response to the activate counter being above an intermediate management threshold value, the refresh control circuit only issue a refresh management (RFM) command if there is no REF command currently held at the refresh command circuit for the memory region.

Abstract: Methods, systems, and devices for staggered refresh counters for a memory device are described. The memory device may include a set of memory dies each coupled with a common command and address (CA) bus and each including a respective refresh counter. In response to a refresh command received over the CA bus, each memory die may refresh a set of memory cells based on a value output by the respective refresh counter for the memory die. The refresh counters for at least two of the memory dies of the memory device may be offset such that they indicate different values when a refresh command is received over the CA bus, and thus at least two of the memory dies may refresh memory cells in different sections of their respective arrays. Offsets between refresh counters may be based on different fuse settings associated with the different memory dies.

Abstract: An information handling system includes a memory subsystem; a processor; and a link connecting the processor and memory subsystem, the processor having a memory controller to manage load instructions; a data cache to hold data for use by the processor; a load store unit to execute load instructions; an instruction fetch unit to fetch load instructions and a cache line utility tracker (CUT) table having a plurality of entries, each entry having a utility field to indicate the portions of a cache line of the load instruction that were used by the processor. The system configured to: determine whether the load instruction is in the CUT Table and in response determine from the CUT Table whether to request a partial cache line; and in response to the data not being in the data cache, transmit a memory request for a partial cache line.

Abstract: Various implementations described herein are directed to an integrated circuit having a cache with memory components that store data with multiple addresses. The integrated circuit may include a controller that communicates with the cache to provide directives to the cache. The integrated circuit may include a refresh circuit that interprets the directives received from the controller to generate interpretation information based on determining one or more particular addresses of the multiple addresses that no longer need refreshing. The refresh circuit may further employ the interpretation information to skip the need for refreshing the one or more particular addresses pointing to the memory components in the cache that no longer need refreshing.

Abstract: The address of victim rows may be determined based on rows that are accessed in a memory. The victim addresses may be stored and associated with a count for every time a victim row is “victimized.” When the count for a victim row reaches a threshold, the victim row may be refreshed to preserve data stored in the row. After the victim row has been refreshed, the count may be reset. When a victim row is accessed, the count may also be reset. The counts may be adjusted for closer victim rows (e.g., +/?1) at a faster rate than counts for more distant victim rows (e.g., +/?2). This may cause closer victim rows to be refreshed at a higher rate than more distant victim rows.

Abstract: Apparatuses and methods for generating multiple row hammer address refresh sequences. An example apparatus may include an address scrambler and a refresh control circuit. The address scrambler may receive a first address, output a second address in response to a first control signal, and output a third address in response to a second control signal. The second address may physically adjacent to the first address and the third address may physically adjacent to the second address. The refresh control circuit may perform a refresh operation on the second address when the first control signal is active and perform the refresh operation on the third address when the second control signal is active.

Abstract: A memory device may include a memory medium and a memory controller. The memory medium may be configured to perform a self-refresh operation and an auto-refresh operation in response to a self-refresh signal and an auto-refresh control signal, respectively. The memory controller may be configured to control the auto-refresh operation by transmitting the auto-refresh control signal to the memory medium. The memory medium includes a self-refresh controller. The self-refresh controller may be configured to control the self-refresh operation based on a self-refresh cycle varying according to an internal temperature of the memory medium and transmit the self-refresh signal to the memory controller. The memory controller may be configured to generate the auto-refresh control signal based on an auto-refresh cycle. The auto-refresh control signal may be determined by the self-refresh signal transmitted from the memory medium.

Abstract: Provided is a bit error rate equalizing method of a memory device. The memory device selectively performs an error correction code (ECC) interleaving operation according to resistance distribution characteristics of memory cells, when writing a codeword including information data and a parity bit of the information data to a memory cell array. In the ECC interleaving operation according to one example, an ECC sector including information data is divided into a first ECC sub-sector and a second ECC sub-sector, the first ECC sub-sector is written to memory cells of a first memory area having a high bit error rate (BER), and the second ECC sub-sector is written to memory cells of a second memory area having a low BER.

Abstract: Devices and methods include organizing memory units of a memory device into a number of groups. The devices and methods also include self-refreshing each group of memory units on different corresponding sequential clock pulses of a self-refresh clock. Specifically, at least one of each group of memory units counts pulses of a self-refresh clock and invokes a self-refresh after every nth pulse of a cycle of pulses while not invoking a self-refresh on all other pulses of the cycle of pulses.

Abstract: A memory controller may control a memory device. The memory device may be coupled to the memory controller through a channel. The memory controller may include an idle time monitor and a clock signal generator. The idle time monitor may output an idle time interval of the memory device. The idle time interval may be between an end time of a previous operation of the memory device and a start time of a current operation. The clock signal generator may generate a clock signal based on the idle time interval and output the clock signal to the memory device through the channel to perform a current operation.

Abstract: An apparatus may include multiple address registers each storing an address signal and multiple counter circuits each storing a count value corresponding to an associated one of the address registers. The apparatus may include a first circuit cyclically selecting one of the address registers in response to a first signal, a second circuit selecting one of the address registers based on the count value of each of the counter circuits, and a third circuit activating a second signal when the first and second circuits select the same one of the address registers.

Abstract: The present disclosure provides a method for refreshing a memory array. The method includes the following steps: generating a plurality of target row records respectively for a plurality of banks; generating a plurality of row address records based on the plurality of target row records; and performing a row-hammer-refreshing process based on the plurality of row address records.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for staggering the timing of skipped refresh operations on a memory. Memory cells of memories may need to periodically perform refresh operations. In some instances, auto-refresh operations may be periodically skipped when charge retention characteristics of the memory cells of the memory exceed the auto-refresh frequency. To reduce peak current draw during refresh operations, the skipped refresh operations may be staggered across different portions of the memory. In one example, the skipped refresh operation may be staggered in time among memory dies of the memory to limit a number of memory dies that are performing an auto-refresh operation to a maximum number. In another example, the skipped refresh operation may be staggered in time among memory banks of a single memory array to limit a number of memory banks that are performing an auto-refresh operation to a maximum number.

Abstract: A semiconductor memory device includes a first count circuit suitable for counting a first clock signal which continuously toggles in each burst refresh cycle, and generating a first count code signal, based on a burst refresh command signal; a cycle guide circuit suitable for generating a second clock signal which toggles once in each burst refresh cycle, based on the burst refresh command signal and a precharge signal; a second count circuit suitable for counting the second clock signal and generating a second count code signal; and a control circuit suitable for generating a latch control signal for latching a target address in each burst refresh cycle, based on the first count code signal and the second count code signal.

Abstract: A semiconductor memory device includes a first count circuit suitable for counting a first clock signal which continuously toggles in each burst refresh cycle, and generating a first count code signal, based on a burst refresh command signal; a cycle guide circuit suitable for generating a second clock signal which toggles once in each burst refresh cycle, based on the burst refresh command signal and a precharge signal; a second count circuit suitable for counting the second clock signal and generating a second count code signal; and a control circuit suitable for generating a latch control signal for latching a target address in each burst refresh cycle, based on the first count code signal and the second count code signal.

Abstract: Exemplary methods, apparatuses, and systems include a controller to manage memory proximity disturb. The controller identifies a first memory location in response to an access of a second memory location, the first memory location storing a first value. The controller updates a first disturb value by a first amount, the first disturb value representing a cumulative disturb effect on the first value in the first memory location by accesses to a first plurality of memory locations proximate to the first memory location, the first plurality of memory locations including the second memory location.

Abstract: A common memory device shared by a first processor and a second processor is provided. The common memory device includes a memory cell array including a first memory region allocated for the first processor and a second memory region allocated for the second processor, a refresh masking information storage circuit configured to store refresh masking information indicating whether a refresh is performed on at least one of the first and second memory regions, and a refresh circuit configured to selectively perform the refresh on the first memory region and the second memory region according to the refresh masking information.

Abstract: A data storage device is disclosed comprising a head actuated over a disk comprising a plurality of data tracks, including a first data track and a second data track. In connection with writing to at least part of the first data track, a quality metric is measured for at least part of the first data track. In connection with writing to at least part of the second data track, a refresh metric is updated based on the write to at least part of second data track and the quality metric measured for the first data track, and at least the first data track is refreshed based on the refresh metric.

Abstract: A semiconductor memory device may include a plurality of banks; a plurality of address storage circuits respectively corresponding to the plurality of banks, and suitable for storing refresh addresses of corresponding banks; an output control circuit suitable for, based on a refresh command signal and a test mode signal, generating an output clock and selectively outputting, as output data, a refresh address outputted from any one of the address storage circuits or bank data provided from the banks; an output buffer suitable for outputting the output data to a plurality of data input/output pads based on the output clock; and a strobe signal generation circuit suitable for generating a data strobe signal based on the output clock and outputting the data strobe signal through a data strobe pad.

Abstract: A system and method for dynamically sizing system memory for a computing device using firmware and NVDIMMs is discussed. Additionally techniques for allocating between system memory and non-volatile storage on one or more NVDIMMs are discussed.

Abstract: Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.

Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.

Abstract: A delay-locked loop circuit includes a delay line and a control unit. The delay line functions to delay an input signal to generate a first delay signal. The control unit receives the input signal, an access start signal and an access end signal, and functions to generate a control signal according to the input signal, the access start signal and the access end signal, wherein the control signal functions to control the delay line between two read operations.

Abstract: A target row refresh method includes: providing first table having M entries each capable of storing information of target row address; providing second table having K entries respectively capable of storing information of different/identical candidate row addresses; determining whether an input address in an input address register matches address information recorded in the first table; when not match, determining whether to update information of a target row latch by using the input address in the input address register according to a sample policy so as to determine whether to compare the input address with address information recorded in the second table to determine a target row address; and performing a target row refresh operation to refresh a memory device's row(s) adjacent to a target row corresponding to the target row address.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for data rewrite operations. A non-volatile memory device comprises a non-volatile memory medium. A non-volatile memory device is configured to determine an error metric for a non-volatile memory medium in response to a read request for the non-volatile memory medium. A non-volatile memory device is configured to receive a refresh command from a controller over a bus. A non-volatile memory device is configured to rewrite data from a non-volatile memory medium during a predefined time period after receiving a refresh command in response to an error metric satisfying an error threshold.