Abstract: A method includes: executing a first process includes receiving an entry that includes a kay and a value, selecting a first list from among a plurality of lists in accordance with a first hash value, adding, to the selected first list, a first identifier in association with the received entry, and storing the received entry in any of a first memory device and a second memory device that is greater in latency than the first memory device; and executing a second process that includes receiving a searching request for a value, selecting the first list based on the first hash value derived from the searching key in the received searching request, obtaining the first identifier from the first list selected in the second process, obtaining the entry associated with the first identifier obtained in the second process, and outputting the value in the entry obtained in the second process.

Abstract: Methods, systems, and devices for hardware-based coherency checking techniques are described. A memory sub-system with hardware-based coherency checking can include a coherency block that maintains a coherency lock and releases coherency upon completion of a write command. The coherency block can perform operations to lock coherency associated with the write command, monitor for completion of the write to the memory device(s), release the coherency lock, and update one or more records used to monitor coherency associated with the write command. A coherency command and coherency status can be provided through a dedicated hardware bridge, such as a bridge through a level-zero cache coupled with the coherency hardware.

Abstract: Various systems, processes, and products may be used to filter multicast messages in virtual environments. In one implementation, a multicast filtering address is received by a network adapter. A frequency of use of the multicast filtering address is determined and, based on the frequency of use of the multicast filtering address, the multicast filtering address is stored in either a multicast filtering store of the network adapter or a local filtering store of a respective virtual machine.

Abstract: Method and apparatus are disclosed for cache control in a parallel processing system. The apparatus includes a plurality of application specific engines configured to generate a plurality of commands, a cache array configured to store the plurality of commands, and a cache command controller configured to receive a command asynchronously from an application specific engine in the plurality of application specific engines, update the cache array to include the received command, and validate the updated cache array while maintaining parallel accessing of the cache array by the plurality of application specific engines.

Abstract: An apparatus comprises a set-associative cache comprising a plurality of sets of cache entries, and cache replacement policy storage circuitry to store a plurality of local replacement policy entries. Each local replacement policy entry comprises local replacement policy information specific to a corresponding set of the set-associative cache. Cache control circuitry controls replacement of cache entries of the set-associative cache based on the local replacement policy information stored in the cache replacement policy storage circuitry. The cache replacement policy storage circuitry stores local replacement policy entries for a proper subset of sets of the set-associative cache.

Abstract: An apparatus includes a processing device comprising a processor coupled to a memory. The processing device is configured, in conjunction with synchronous replication of at least one logical storage volume between first and second storage systems, to receive a synchronous write request comprising a data page to be written to the logical storage volume, to determine a content-based signature for the data page, and to send the content-based signature from the first storage system to the second storage system. Responsive to receipt in the first storage system of an indication from the second storage system that the data page having the content-based signature is not already present in the second storage system, the processing device is further configured to send the data page from the first storage system to the second storage system. The processing device in some embodiments implements a distributed storage controller of a content addressable storage system.

Abstract: In an example embodiment, a distributed storage system includes a service tier including a service node to receive a request for a logical object comprising binary data and metadata describing the binary data, and a storage tier including a plurality of storage nodes, wherein one or more of the storage nodes is to store the metadata describing the binary data. The distributed storage system also includes a coordination tier to store mapping information identifying the one or more of the storage nodes storing the metadata. The service node is also to receive the mapping information from the coordination tier, to access the metadata describing the binary data from one of the one or more of the storage nodes based on the mapping information, and to return the metadata describing the binary data in a response to the request.

Abstract: Method and apparatus implementing smart store operations with conditional ownership requests. One aspect includes a method implemented in a multi-core processor, the method comprises: receiving a conditional read for ownership (CondRFO) from a requester in response to an execution of an instruction to modify a target cache line (CL) with a new value, the CondRFO identifying the target CL and the new value; determining from a local cache a local CL corresponding to the target CL; determining a local value from the local CL; comparing the local value with the new value; setting a coherency state of the local CL to (S)hared when the local value is same as the new value; setting the coherency state of the local CL to (I)nvalid when the local value is different than the new value; and sending a response and a copy of the local CL to the requester. Other embodiments include an) apparatus configured to perform the actions of the methods.

Abstract: In various embodiments, an ordered atomic operation enables a parallel processing subsystem to executes an atomic operation associated with a memory location in a specified order relative to other ordered atomic operations associated with the memory location. A level 2 (L2) cache slice includes an atomic processing circuit and a content-addressable memory (CAM). The CAM stores an ordered atomic operation specifying at least a memory address, an atomic operation, and an ordering number. In operation, the atomic processing circuit performs a look-up operation on the CAM, where the look-up operation specifies the memory address. After the atomic processing circuit determines that the ordering number is equal to a current ordering number associated with the memory address, the atomic processing circuit executes the atomic operation and returns the result to a processor executing an algorithm.

Abstract: Embodiments of the present invention are directed to a computer-implemented method for controller address contention assumption. A non-limiting example computer-implemented method includes a shared controller receiving a fetch request for data from a first requesting agent, the receiving via at least one intermediary controller. The shared controller performs an address compare using a memory address of the data. In response to the memory address matching a memory address stored in the shared controller, the shared controller acknowledges the at least one intermediary controller's fetch request, wherein upon acknowledgement, the at least one intermediary controller resets. In response to release of the data by a second requesting agent, the shared controller transmits the data to the first requesting agent.

Abstract: A storage system comprises multiple storage nodes each comprising at least one storage device. Each of the storage nodes further comprises a set of processing modules configured to communicate over one or more networks with corresponding sets of processing modules on other ones of the storage nodes. The sets of processing modules of the storage nodes each comprise at least one data module and at least one control module. The storage system is configured to assign portions of a content-based signature space of the storage system to respective ones of the data modules, and to assign portions of a logical address space of the storage system to respective ones of the control modules. The assignment of portions of the logical address space to the control modules is configured to at least partially offset an unbalanced condition between local physical storage capacities of the data modules.

Abstract: A method for an associative memory array includes storing each column of a matrix in an associated column of the associative memory array, where each bit in row j of the matrix is stored in row R-matrix-row-j of the array, storing a vector in each associated column, where a bit j from the vector is stored in an R-vector-bit-j row of the array. The method includes simultaneously activating a vector-matrix pair of rows R-vector-bit-j and R-matrix-row-j to concurrently receive a result of a Boolean function on all associated columns, using the results to calculate a product between the vector-matrix pair of rows, and writing the product to an R-product-j row in the array.

Abstract: A method includes receiving, at a content provisioning system from one or more client devices, one or more requests for file digests stored in respective data stores of a plurality of data stores in a distributed file system. The file digests are distributed across different ones of the plurality of data stores in the distributed file system. The method also includes determining a location of a given one of the requested file digests in one or more of the plurality of data stores and retrieving the given file digest from the determined location. The method further includes shuffling the distribution of the file digests across the plurality of data stores in the distributed file system.

Abstract: Disclosed is a method for accessing a code Static Random Access Memory (SRAM) and an electronic device. The method is applied to an electronic device including a first controller, a code SRAM and an in circuit emulator (ICE); and the method includes: receiving, by the ICE, a first address at which the first controller accesses the code SRAM; transmitting, by the ICE, a first code to the first controller if the first address is the same as a second address, where the second address is an address corresponding to an abnormal address cell in the code SRAM, and the first code is a correct code of the abnormal address cell; or obtaining, by the ICE, a second code corresponding to the first address from the code SRAM, and transmitting the second code to the first controller, if the first address is different from the second address.

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream. An address generator produces virtual addresses of data elements. An address translation unit converts these virtual addresses to physical addresses by comparing the most significant bits of a next address N with the virtual address bits of each entry in an address translation table. Upon a match, the translated address is the physical address bits of the matching entry and the least significant bits of address N. The address translation unit can generate two translated addresses. If the most significant bits of address N+1 match those of address N, the same physical address bits are used for translation of address N+1. The sequential nature of the data stream increases the probability that consecutive addresses match the same address translation entry and can use this technique.

Abstract: Disclosed herein are methods, systems, and apparatus, including computer programs encoded on computer storage media, for communicating and sharing blockchain data. One of the methods includes sending current state information associated with a current block of a blockchain to one or more shared storage nodes of the blockchain network; sending a hash value to the one of the one or more shared storage nodes for retrieving an account state stored in the historic state tree; receiving the account state in response to sending the hash value; and verifying, by the consensus node, that the account state is part of the blockchain based on the hash value.

Abstract: A semiconductor memory device includes a memory cell including a first memory unit and a second memory unit which are coupled to a complementary bit line pair, an operation controller configured to successively select the first memory unit and the second memory unit, during a read operation which reads data from the memory cell, a first readout unit coupled to one of the bit line pair, and configured to judge a logical value of the data read from the selected first memory unit onto the one of the bit line pair, and a second readout unit coupled to the other of the bit line pair, and configured to judge a logical value of the data read from the selected second memory unit onto the other of the bit line pair.

Abstract: Aspects include a computer-implemented method that includes receiving an instruction at a processor to perform an operation on a memory block having an address and accessing a state indicator by the processor without altering a value of the state indicator. The state indicator is stored in a memory location independent of the memory block, and accessing includes sending a request to an operator to return the value of the state indicator to the processor. The method also includes determining based on the value of the state indicator whether the memory block is in a pre-defined state.

Abstract: Aspects include a computer-implemented method includes receiving an instruction at a processor to perform an operation on a memory block having an address and accessing a state indicator by the processor without altering a value of the state indicator. The state indicator is stored in a memory location independent of the memory block, and accessing includes sending a request to an operator to return the value of the state indicator to the processor. The method also includes determining based on the value of the state indicator whether the memory block is in a pre-defined state.

Abstract: In an example, a method may include comparing input data to stored data stored in a memory cell and determining whether the input data matches the stored data based on whether the memory cell snaps back in response to an applied voltage differential across the memory cell.

Abstract: An apparatus for providing fault resilience has storage for providing a plurality of compare data blocks, and processing circuitry that performs, for each compare data block, a processing operation using the input data and the compare data block to produce a match condition indication for that compare data block. Performance of the processing operation for each compare data block should result in only one match condition indication indicating a match. Evaluation circuitry evaluates the match condition indications produced for the plurality of compare data blocks and is arranged, in the presence of only one match condition indication indicating a match, to perform a false hit check procedure in order to check for presence of a false hit. In the presence of the false hit, the evaluation circuitry produces an error indication as the outcome indication, but otherwise produces a hit indication as the outcome indication.

Abstract: Various exemplary embodiments relate to a patch module connected between a data bus and a ROM memory controller. The patch module may include: at least one patch address register configured to store a ROM address; a patch data register corresponding to each patch address register, each patch data register configured for storing an instruction; an address comparator configured to compare an address received on the data bus with an address stored in each patch address register and output a first signal identifying a matching patch address register and a second signal indicating whether there is a matching address; and a first multiplexer configured to select the patch data register corresponding to the matching patch address register and output the contents of the patch data register to the data bus.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for a system to create and employ associative memory maps for analysis of security file and/or logs are disclosed. In one aspect, a method includes the actions of receiving, from an external application, a request for a recommended action; extracting information regarding the entities and relationships between the entities from a data source; constructing an associative memory map from the extracted information; selecting a subgraph from the associative memory map based on a result of employing a vector to search nodes in the associative memory map; identifying the nodes most relevant to the requested recommend action base on a shortest paths of traversal in the selected subgraph of nodes; determining the requested recommended action based on an event identified in the relationships between the identified most relevant nodes; and transmitting the recommended action to the external application.

Abstract: Certain hash-based operations in network devices and other devices, such as mapping and/or lookup operations, are improved by manipulating a hash key prior to executing a hash function on the hash key and/or by manipulating outputs of a hash function. A device may be configured to manipulate hash keys and/or outputs using manipulation logic based on one or more predefined manipulation values. A similar hash-based operation may be performed by multiple devices within a network of computing devices. Different devices may utilize different predefined manipulation values for their respective implementations of the manipulation logic. For instance, each device may assign itself a random mask value for key transformation logic as part of an initialization process when the device powers up and/or each time the device reboots. In an embodiment, described techniques may increase the entropy of hashing function outputs in certain contexts, thereby increasing the effectiveness of certain hashing functions.

Abstract: A hash content addressable memory system includes a hash content addressable memory block (HCB) that is a physical subsystem of the hash content addressable memory system. The first HCB include first bus select logic. The first bus select logic is connected to a plurality of key buses and to a plurality of operation buses. Each key bus from the plurality of key buses and each operation bus from the plurality of operation buses is connected to one and only one client in a plurality of clients. Every client in the plurality of clients is connected to only one key bus from the plurality of key buses and is connected to only one operation bus from the plurality of operation buses.

Abstract: The life cycle of one or more containers related to one or more containerized applications is managed by determining that a predefined retention time for a first container of the plurality of containers has elapsed; in response to the determining, performing the following honeypot container creation steps: suspending new session traffic to the first container; maintaining the first container as a honeypot container; and identifying communications sent to the honeypot container as an anomalous communication. Alert notifications are optionally generated for the anomalous communication.

Abstract: A method for operating a memory device includes initiating an access operation to a corresponding row of an array of bit cells of the memory device. Responsive to an expansion mode signal having a first state, the method further includes dynamically operating each column of a plurality of columns of the array to access each bit cell of a corresponding row within the plurality of columns during the access operation. Alternatively, responsive to the expansion mode state signal having a second state different than the first state, the method includes dynamically operating each column of a first subset of columns of the plurality of columns to access each bit cell of a corresponding row within the first subset of columns during the access operation, and maintaining each column of a second subset of columns of the plurality of columns in a static state during the access operation.

Abstract: In shared-memory computer systems, threads may communicate with one another using shared memory. A receiving thread may poll a message target location repeatedly to detect the delivery of a message. Such polling may cause excessive cache coherency traffic and/or congestion on various system buses and/or other interconnects. A method for inter-processor communication may reduce such bus traffic by reducing the number of reads performed and/or the number of cache coherency messages necessary to pass messages. The method may include a thread reading the value of a message target location once, and determining that this value has been modified by detecting inter-processor messages, such as cache coherence messages, indicative of such modification. In systems that support transactional memory, a thread may use transactional memory primitives to detect the cache coherence messages. This may be done by starting a transaction, reading the target memory location, and spinning until the transaction is aborted.

Abstract: One embodiment of the present invention sets forth a technique for compressing a forwarding table. The technique includes selecting, from a listing of network prefixes, a plurality of network prefixes that are within a range of a subnet. The technique further includes sorting the plurality of network prefixes to generate one or more subgroups of network prefixes and selecting a first subgroup of network prefixes included in the one or more subgroups of network prefixes. The technique further includes generating a synthetic supernet based on the first subgroup of network prefixes.

Abstract: Described herein are various embodiments of a network element comprising a network port to receive a unit of network data and a data plane coupled to the network port. In one embodiment the data plane includes a ternary content addressable memory (TCAM) module to compare a first set of bits in the unit of network data with a second set of bits in a key associated with a TCAM rule. The second set of bits includes a first subset of bits and a second subset of bits and the TCAM module includes first logic to compare one or more bits in the first set of bits against the second set of bits, and second logic to select an action or a result using bits from either the second subset of bits, from the unit of network data, or from meta data associated with the unit of network data. Other embodiments are also described.

Abstract: In an example, a method includes receiving input data and dividing the input data into a plurality of data portions, wherein the size of each data portion is based on a significance level. The input data may be assigned to at least one resistive memory array. Assigning the input data to at least one resistive memory array may comprises at least one of (i) assigning at least one data portion of the input data to be represented by a resistive memory array representing a number of bits, wherein the number of bits represented within the resistive memory array is based on the size of the at least one data portion; and (ii) processing each data portion of the input data with at least one resistive memory array.

Abstract: A processor includes a plurality of memory units, each of the memory units including a plurality of memory cells, wherein each of the memory units is configurable to operate as memory, as a computation unit, or as a hybrid memory-computation unit.

Abstract: A method and system for steering bidirectional network traffic to a same service device. Specifically, the disclosed method and system entail the maintaining and synchronization of link aggregation group (LAG) tables tied to a pair of LAG ports instantiated on a network element directly connected to a pair of peer linking service devices. Network traffic (i.e., MAC frames) arriving at the network element, from a first host and intended for a second host (e.g., indicative of a first direction of the network traffic), may be steered towards one of the pair of service devices based on hashing of information included in a received MAC frame in conjunction with the LAG table tied to the LAG port (of the pair of LAG ports) that which received the MAC frame.

Abstract: External memory protection may be implemented for content addressable memory (CAM). Memory protection data, such as duplicate values for entries in a CAM or error detection codes generated from values of the entries in a CAM, may be stored in a random access memory that is separate from the CAM. When an entry in the CAM is accessed to perform a lookup or scrubbing operation, the memory protection data may be obtained from the RAM. A validation of the value of the entry may then be performed according to the memory protection data to determine whether the value is valid.

Abstract: A computer-implemented method comprising: receiving, by a computing device, biometrics data of a user via a user device as part of a request to access a secure device; applying, by the computing device, a non-invertible function to the biometrics data to scramble the biometrics data; determining, by the computing device, whether the scrambled biometrics data matches a pre-registered version of the scrambled biometrics data; and providing, by the computing device, an authentication message to the secure device requesting authentication of the user based on determining that the scrambled biometrics data matches the pre-registered version of the scrambled biometrics data, wherein the providing the authentication message provides a user of the user device with access to the secure device.

Abstract: Aspects of the present disclosure involve systems for providing multiple egress routes from a telecommunications network for a client of the network. In general, the system provides for a client of the network to receive intended packets of information through multiple connections to the network such that load balancing and failover services for traffic to the customer are provided. The process and system allows for telecommunications network to utilize a common next-hop value of announced border gateway protocol (BGP) routes to advertise multiple routes to reach a destination customer network or address. By utilizing a common next-hop value in the announced BGP information, the devices of the network may load balance communication packets to the destination customer or address among the multiple egress locations from the network, as well as providing fast failover to alternate routes when a failure at the network or customer occurs.

Abstract: Pre-processing before precise pattern matching of a target pattern from a stream of patterns. Including acquiring occurrence numbers of target elements in the target pattern, initializing the buffer, the buffer indicating a section in the stream of patterns, determining whether occurrence numbers of the target elements in the buffer reach the occurrence numbers of the target elements in the target pattern, updating the buffer and then returning to the determining step, in response to determining that the occurrence numbers of the target elements in the buffer do not reach the occurrence numbers of the target elements in the target pattern, and outputting the elements in the buffer for subsequent processing, in response to determining that the occurrence numbers of the target elements in the buffer reach the occurrence numbers of the target elements in the target pattern.

Abstract: Examples relate to the configuration of network connections for computing devices. In some examples, a computing device determines that a network is inaccessible through a first network connection provided by a network access node. The computing device determines that the network is accessible through a first computing device that provides a second connection to the network. The computing device generates gateway configuration data for a second computing device based on an address for the first computing device. The computing device transmits the gateway configuration data to the second computing device to cause the second computing device to use the first computing device as a gateway.

Abstract: A data writing method, a valid data identifying method and a memory storage apparatus using the same are provided. The method includes receiving first data; using a first programming mode to write first sub-data of the first data into a first physical programmed unit of at least a first memory sub-module of a plurality of memory sub-modules, wherein a size of each of the first sub-data is the same as a preset size; and using a second programming mode to write remaining sub-data of the first data into a second physical programmed unit of a second memory sub-module of the plurality of memory submodules, wherein the size of the remaining sub-data is less than the preset size, and the second memory sub-module is different from a third memory sub-module of the first memory submodules which is a last memory sub-module for writing the first sub-data.

Abstract: Techniques are disclosed for faster loading of data for hardware accelerators. One technique includes after determining that an accelerator is not ready to perform a workload, identifying data associated with performing the workload and negotiating for the data on behalf of the accelerator. After the negotiation, a cache directory entry associated with the data is marked with a “claimed” state indicating that the accelerator has obtained ownership of the data but does not have possession of the data. After an indication that the accelerator is ready to accept the data for the workload is received, the data is moved from a previous owner that has possession of the data to the accelerator. Another technique includes requesting a processing unit to perform a workload. If the processing unit is not ready to perform the workload, a translation cache used by the processing unit is warmed up by another unit.

Abstract: Techniques are provided for providing a storage abstraction layer for a composite aggregate architecture. A storage abstraction layer is utilized as an indirection layer between a file system and a storage environment. The storage abstraction layer obtains characteristic of a plurality of storage providers that provide access to heterogeneous types of storage of the storage environment (e.g., solid state storage, high availability storage, object storage, hard disk drive storage, etc.). The storage abstraction layer generates storage bins to manage storage of each storage provider. The storage abstraction layer generates a storage aggregate from the heterogeneous types of storage as a single storage container. The storage aggregate is exposed to the file system as the single storage container that abstracts away from the file system the management and physical storage details of data of the storage aggregate.

Abstract: A system including first and second information handling systems may implement: a virtual bridge associated with a network information handling resource, a virtual machine to access the resources of the first information handling system; a virtualization environment to migrate the virtual machine from the first to the second information handling system using the virtual bridge; a first virtual function mapping the network information handling resource and the first information handling system; a second virtual function mapping the network information handling resource and the second information handling system; and a physical function mapping the network information handling resource and a chassis management controller. The physical function may be a Peripheral Component Interconnect Express (PCIe) I/O Virtualization (IOV) physical function.

Abstract: A scoped search engine is disclosed. The scoped search engine includes a memory unit storing reference data records. The scoped search engine also includes a data comparison unit that searches the reference data records using different searches. The scoped search engine further includes a match analysis unit that combines result data from the different searches and determines a scope for a subsequent search based on the combined result data.

Abstract: A processor is configured to store color component values associated with a first subset of vertices of a three-dimensional (3-D) look up table (LUT) in a first subset of memory elements. The color component values are defined according to a destination gamut. A data select module is configured to access the color component values from the first subset of the memory elements concurrently with the processor storing color component values associated with a second subset of the vertices of the 3-D LUT in a second subset of the memory elements. The data select module is configured to access the color component values from the first and second subsets of the memory elements in response to the processor storing the color component values associated with the second subset of the vertices of the 3-D LUT in the second subset of the memory elements. This process can be extended to additional subsets.

Abstract: The present disclosure relates to a system and methods of implementing an integer-value database using a single I/O operation. In particular, the present disclosure relates to methods of writing and reading information to a database using key/value pairs, including receiving, at a database management system, a value to be written to a database, the database including a plurality of segments stored on a storage medium, and assigning, by the database management system, an assigned key to the value based on keys previously used in the database. The method may further include storing, by the database management system, the assigned key and the value to a segment at a virtual end of the database, wherein the segment is identified in a mapping index by an offset and the mapping index identifies a first key in the segment, and returning the assigned key.

Abstract: A memory system and operating method thereof includes a semiconductor memory device, and a memory controller controlling actions of the memory device. The memory controller contains a processor executing instruction and programs stored in the memory controller, a memory characterizer characterizing the memory system, and generating an index decision table, an in-flight assessor assessing read command, and predicting a proposed error recovery action in accordance with the index decision table, and a selective decoder executing the proposed error recovery action.

Abstract: One embodiment performs longest prefix matching operations in one or more different manners that provides packet processing and/or memory efficiencies in the processing of packets. In one embodiment, a packet switching device determines a set of one or more mask lengths of a particular conforming entry of a multibit trie or other data structure that matches a particular address of a packet via a lookup operation in a mask length data structure. A conforming entry refers to an entry which has less than or equal to a maximum number of different prefix lengths, with this maximum number corresponding to the maximum number of prefix lengths which can be searched in parallel in the address space for a longest matching prefix by the implementing hardware. The packet switching device then performs corresponding hash table lookup operation(s) in parallel in determining an overall longest matching prefix for the particular address.

Abstract: A cache structure implemented in a microprocessor core include a set predictor and a logical directory. The set predictor contains a plurality of predictor data sets containing cache line information, and outputs a first set-ID indicative of an individual predictor data set. The logical directory contains a plurality of logical data sets containing cache line information. The cache structure selectively operates in a first mode such that the logical directory receives the first set-ID that points to an individual logical data set, and a second mode such that the logical directory receives a currently issued micro operational instruction (micro-op) containing a second set-ID that points to an individual logical data set. The logical directory performs a cache lookup based on the first set-ID in response to operating in the first mode, and performs a cache lookup based on the second set-ID in response to operating in the second mode.

Abstract: Disclosed is a system and method of providing transport-level identification and isolation of container traffic. The method includes receiving, at a component in a network, a packet having a data field, extracting, at a network layer, container identification data from the data field and applying a policy to the packet at the component based on the container identification data. The data field can include one of a header, an IPv6 extension header, a service function chaining container identification, a network service header, and an optional field of an IPv4 packet.

Abstract: A fault-tolerant failsafe computer voting system including a first voting module that generates a first key based on a comparison between a first data packet and a copy of a second data packet. The first voting module determines whether the first key and a second key are valid keys. The second data packet is a copy of the first data packet. A second voting module generates the second key based on a comparison between the second data packet and a copy of the first data packet. A processing module generates an outgoing data packet based on the first data packet in response to determining whether the first key and the second key are valid keys. The first voting module is inhibited from generating the second key and the second voting module is inhibited from generating the first key.