Abstract: An operation method of a controller for controlling a memory device includes: queuing an identifier of a logical address region associated with a read request from a host in a most recently used (MRU) entry of an internal logical address region queue; increasing a weighted value for a read count of the logical address region by a first value according to whether the identifier of the logical address region has been queued in the logical address region queue before being queued in the MRU entry; adding the weighted value to the read count of the logical address region; providing the host with a map segment corresponding to the logical address region according to a threshold of the read count; and controlling a read operation of the memory device based on a physical address according to whether the read request includes the physical address.

Abstract: A storage device includes a memory device including a plurality of zones, each of the plurality of zones having a plurality of memory blocks, a buffer memory device including a host buffer receiving write data to be stored in one of the plurality of zones, and a memory buffer temporarily storing the write data transmitted from the host buffer, a buffer controller configured to control the buffer memory device to transmit the write data to the memory device, and a write operation controller configured to control the memory device to store the write data in the one of the plurality of one zones. The write operation controller controls the memory device to obtain the previously stored data and a corrected write data and to store the previously stored data and the corrected write data in a second memory block group after the write operation controller detects an error in the write data.

Abstract: A memory device includes: in-memory operation units to perform in-memory processing of an operation pipelined in multi-pipeline stages; memory banks assigned to the plurality of in-memory operation units such that a set of n memory banks is assigned to each of the in-memory operation units, each memory bank performing an access operation of data requested by each of the plurality of in-memory operation units while the pipelined operation is performed, wherein n is a natural number; and a memory die in which the in-memory operation units, the memory banks, and command pads configured to receive a command signal from an external source are arranged. Each set of the n memory banks includes a first memory bank having a first data transmission distance to the command pads and a second memory bank having a second data transmission distance to the command pads that is larger than the first data transmission distance.

Abstract: According to one or more embodiments of the present invention, a computer implemented method includes enabling, by a secure interface control of a computer system, a non-secure entity of the computer system to access a page of memory shared between the non-secure entity and a secure domain of the computer system based on the page being marked as non-secure with a secure storage protection indicator of the page being clear. The secure interface control can verify that the secure storage protection indicator of the page is clear prior to allowing the non-secure entity to access the page. The secure interface control can provide a secure entity of the secure domain with access to the page absent a check of the secure storage protection indicator of the page.

Abstract: Provided is a method of performing an internal processing operation of a memory device in a system including a host device and the memory device. The memory device includes a memory cell array and a processor-in-memory (PIM) performing an internal processing operation. In an internal processing mode, by the PIM, the memory device performs the internal processing operation based on internal processing information stored in the memory cell array. When the internal processing information is an internal processing operation command indicating a type of the internal processing operation, the memory device outputs the internal processing operation command including an internal processing read command and an internal processing write command to the host device. The host device issues to the memory device a priority command determined from among a data transaction command and the internal processing operation command.

Abstract: A computer program product, system, and computer implemented method comprises a multi-layered approach to virtual IP address assignment, where a managing computing node may control the generation of virtual IP addresses and assignment thereof to respective computing nodes, and where each respective computing node can control the allocation and binding of those virtual IP addresses to applications for the virtual IP addresses assigned to that computing node. Furthermore, in some embodiments, the approach includes a process to re-allocate virtual IP addresses to rebalance resources already allocated to a computing node and to address changing conditions.

Abstract: A field programmable gate array (FPGA) dynamic reconfiguration method, apparatus, device and readable storage medium are provided.

Abstract: A method, an apparatus, a device, and a storage medium for managing an access request are provided. The method includes acquiring a group of access requests for performing data access to a storage device in a computing system, the group of access requests indicating access operations for a group of addresses in the storage device respectively; arranging an order of the group of addresses based on address ranges of the addresses of the group of addresses in the storage device; generating a merged request based on at least one part of the access requests with consecutive addresses among the group of access requests with the arranged addresses; and executing a data access operation on the storage device based on the merged request, the method being implemented in a driver of the storage device, and the driver being implemented in a user state of the computing system.

Abstract: A memory device includes a memory area configured to store data, a data input/output (I/O) part configured to receive and output data through an external bus, an I/O buffering part coupled between the memory area and the data I/O part to store data outputted from the memory area, and a first internal data transmission line providing a data transmission path between the memory area and the I/O buffering part and having a first bandwidth which is greater than a bandwidth of the external bus, Data transmission between the memory area and the I/O buffering part through the first internal data transmission line is executed using a portion of the first bandwidth in a first operation mode and is executed using all of the first bandwidth in a second operation mode.

Abstract: Three-dimensional (3D) memory devices are provided. An exemplary 3D memory device includes a 3D NAND memory array and an on-die data processing circuit coupled to the 3D NAND memory array on a same chip. The on-die data processing circuit is configured to receive, from an input/output (I/O) interface, control instructions for performing operations on data stored in the 3D NAND memory array. The on-die data processing circuit is also configured to retrieve the data from the 3D NAND memory array based on the control instructions and perform the operations on the retrieved data. Moreover, the on-die data processing circuit is configured to return a result of the operations to the I/O interface.

Abstract: A management device that may communicate with at least one devices is disclosed. The management device may include a communication logic to communicate with the devices over a communication channels about data associated with the devices. The management device may also include reception logic that may receive a query from a host. The query may request information from the management device about the devices. The management device may also include a transmission logic to send the data about the devices to the host. The host may be configured to send a message to the devices.

Abstract: A technique includes performing optimistic concurrency control to process a request associated with a transaction to change a schema of an object. Performing the optimistic concurrency control includes locally modifying the object to change the schema of the object based on the request; after locally modifying the object, locking a global catalog to block the object from being globally modified; validating the locally modified object based on the global catalog; and committing the modified object to a globally shared storage in response to the modified object being validated.

Abstract: The present invention relates to a system and method for predicting (simulating) at least one of a physical and chemical phenomenon on processors, each having computing cores. The system and method further includes a random-access memory including memory segments. The invention is based on the use of a table of numerical data that is stored in a single random-access memory segment that is “shared” between all of the cores.

Abstract: Embodiments of the present disclosure provide a method and a coroutine framework for processing parallel tasks, a device, a medium and an unmanned vehicle. The method includes: switching a current coroutine to a target coroutine in response to a task switching instruction, in which, the coroutine is created at a user layer for processing a task, and the coroutine at the user layer is executed by a thread at a kernel layer; and saving context of a task processed by the current coroutine, and reading context of a task processed by the target coroutine, such that the thread at the kernel layer corresponding to the target coroutine processes the task based on the context of the target coroutine when executing the target coroutine.

Abstract: There is provided a data processing apparatus comprising table circuitry to store a table that indicates, for a program counter value of an instruction that performs a memory access operation at a memory address, one or more offsets of the memory address and an associated confidence for each of the one or more offsets. Prefetch circuitry prefetches data based on each of the offsets in dependence on the associated confidence. Each of the offsets of the memory address is dynamically determined.

Abstract: A system includes a memory configured to store data, a first master configured to issue a first data transfer request to the memory, a division unit configured to divide the first data transfer request into a plurality of data transfer requests, and output the plurality of data transfer requests, and a second master configured to issue a second data transfer request to the memory.

Abstract: A building security system for a building includes one or more memory devices configured to store instructions. The instructions, when executed on one or more processors, cause the one or more processors to receive an access policy data structure for a building device, the access policy data structure indicating access policies for interactions of one or more other building devices with the building device, wherein the access policy data structure identifies the one or more other building devices with one or more building model queries, generate a dynamic access policy data structure for the building device by resolving the one or more building model queries with a building model to identify the one or more other building devices, wherein the dynamic access policy data structure comprises the access policies, and implement the access policies of the dynamic access policy data structure based on the one or more other building devices.

Abstract: A system includes a memory device with multiple memory dies and at least a spare memory die. A processing device is coupled to the memory device. The processing device is to track a value of a write counter representing a number of write operations performed at the multiple memory dies. The processing device is to activate the spare memory die in response to detection of a failure of a first memory die of the multiple memory dies. The processing device is to store an offset value of the write counter in response to the detection of the activation of the spare memory die, the offset value representing the value of the write counter upon activation of the first spare memory die.

Abstract: A management device that may communicate with at least one devices is disclosed. The management device may include a communication logic to communicate with the devices over a communication channels about data associated with the devices. The management device may also include reception logic that may receive a query from a host. The query may request information from the management device about the devices. The management device may also include a transmission logic to send the data about the devices to the host. The host may be configured to send a message to the devices.

Abstract: Example implementations described herein facilitate a drive unit to share physical mediums (e.g. solid state drives) among multiple storage controllers or storage nodes in a distributed storage system, while keeping them physically independent in a redundancy group to avoid single point of failure, by providing an interface to notify redundancy group to the drive unit.

Abstract: A memory system, a memory controller, and an operating method therefor. The memory system includes a first processor configured to determine a processor, among multiple processor including the first processor, to process read operations on logical addresses indicated by read commands, and process a write operation on a logical address indicated by a write command; and a second processor, among the multiple processors, configured to process a read operation on a target logical address selected by the first processor among the logical addresses. The first processor searches for mapping information on a logical address corresponding to a read or write operation to be processed by the first processor, by using a first map search engine, and the second processor searches for mapping information on the target logical address by using a second map search engine. It is possible to improve the performance of searching for mapping information in a read operation.

Abstract: Devices and techniques for memory access bounds checking for a programmable atomic operator are described herein. A processor can execute a programmable atomic operator with a base memory address. The processor can obtain a memory interleave size indicator corresponding to the programmable atomic operator and calculate a contiguous memory address range from the base memory address and the memory interleave size. The processor can then detect that a memory request from the programmable atomic operator is outside the contiguous memory address range and deny the memory request when it is outside of the contiguous memory address range and allow the memory request otherwise.

Abstract: Various embodiments described herein provide for using a prefetch buffer for a data interface bridge, which can be used with a memory sub-system to increase read access or sequential read access of data from a memory device coupled to the data interface bridge.

Abstract: A data linkage system and an API platform are capable of behaving according to a load of processing executed in response to a request for provision of an API. The data linkage system includes the API platform that provides the API for acquiring data, which is based on data collected by a data collection system and stored in a data storage system for storing data held by an information system, from the data storage system. The API platform determining whether the number of the data that has not been subjected to processing to acquire the data from the data storage system in response to a request for provision of the API satisfies a specific condition, and changing capacity of the processing according to a result of the determination.

Abstract: A management device that may communicate with at least one devices is disclosed. The management device may include a communication logic to communicate with the devices over a communication channels about data associated with the devices. The management device may also include reception logic that may receive a query from a host. The query may request information from the management device about the devices. The management device may also include a transmission logic to send the data about the devices to the host. The host may be configured to send a message to the devices.

Abstract: Examples relate to detection of anomalies in a network. Some examples determine a dictionary including a set of keys for a set of packet length values for a selected sequence of packets associated with a traffic flow over a network, each key represents a combination of two or more successive packet length values from the set of packet length values. An aggregated set of statistical features is determined based in part on the set of statistical features using a machine learning algorithm. Upon determining another set of packet length values for another selected sequence of packets, another set of statistical features for the other set of packet length values is determined. The other set of statistical features is compared with the aggregated set of statistical features. Based on the comparison, an indication that an anomaly has occurred in the traffic flow is transmitted to an administrator.

Abstract: In a computer system having multiple memory proximity domains including a first memory proximity domain with a first processor and a first memory and a second memory proximity domain with a second processor and a second memory, latencies of memory access from each memory proximity domain to its local memory as well as to memory at other memory proximity domains are probed. When there is no contention, the local latency will be lower than remote latency. If the contention at the local memory proximity domain increases and the local latency becomes large enough, memory pages associated with a process running on the first processor are placed in the second memory proximity domain, so that after the placement, the process is accessing the memory pages from the memory of the second memory proximity domain during execution.

Abstract: An apparatus and method are provided for controlling allocation of instructions into an instruction cache storage. The apparatus comprises processing circuitry to execute instructions, fetch circuitry to fetch instructions from memory for execution by the processing circuitry, and an instruction cache storage to store instructions fetched from the memory by the fetch circuitry. Cache control circuitry is responsive to the fetch circuitry fetching a target instruction from a memory address determined as a target address of an instruction flow changing instruction, at least when the memory address is within a specific address range, to prevent allocation of the fetched target instruction into the instruction cache storage unless the fetched target instruction is at least one specific type of instruction. It has been found that such an approach can inhibit the performance of speculation-based caching timing side-channel attacks.

Abstract: An operation method for a 3D NAND flash includes writing data into a WLn layer of the plurality of wordline layers of an unselect bit line of the plurality of bit lines in a write operation; and applying a first pass voltage on at least a first WL layer of the plurality of wordline layers of the unselect bit line of the plurality of bit lines and applying a second pass voltage on at least a second WL layer of the plurality of wordline layers of the unselect bit line of the plurality of bit lines; wherein the operation method is operated when a pre-pulse phase is removed from a verify phase.

Abstract: A system and method for transferring data between a user space buffer in the address space of a user space process running on a virtual machine and a storage system are described. The user space buffer is represented as a file with a file descriptor. In the method, a file system proxy receives a request for I/O read or write from the user space process without copying data to be transferred. The file system proxy then sends the request to a file system server without copying data to be transferred. The file system server then requests that the storage system perform the requested I/O directly between the storage system and the user space buffer, the only transfer of data being between the storage system and the user space buffer.

Abstract: In one embodiment, data communication apparatus includes a network interface including one or more ports for connection to a packet data network and configured to receive content transfer requests from at least one remote device over the network, a storage sub-system to be connected to local peripheral storage devices, and including at least one peripheral interface, and a memory sub-system including a cache and RAM, and processing circuitry to manage transfer of content between the remote device(s) and the local peripheral storage devices via the peripheral interface(s) and the cache, responsively to the content transfer requests, while pacing commencement of serving of respective ones of the content transfer requests responsively to a metric of the storage sub-system so that while ones of the content transfer requests are being served, other ones of the content transfer requests pending serving are queued in at least one pending queue.

Abstract: Methods and systems facilitate continuous processing of incoming data while one or more software components are updated and/or are temporarily unavailable. Computing tasks may be divided into idempotent steps with the computational state exchanged between steps saved in a persistent manner. In various embodiments, these steps are assembled into one or more computation pipelines.

Abstract: The embodiments described herein describe technologies for memory systems. One implementation of a memory system includes a motherboard substrate with multiple module sockets, at least one of which is populated with a memory module. A first set of data lines is disposed on the motherboard substrate and coupled to the module sockets. The first set of data lines includes a first subset of point-to-point data lines coupled between a memory controller and a first socket and a second subset of point-to-point data lines coupled between the memory controller and a second socket. A second set of data lines is disposed on the motherboard substrate and coupled between the first socket and the second socket. The first and second sets of data lines can make up a memory channel.

Abstract: A disclosed method may include (1) maintaining a set of fleeting contexts that represent a lockless data structure at different moments in time, (2) determining an oldest context within the set of fleeting contexts, (3) identifying, within a discard list of the oldest context, a reference to an object stored in shared memory, and then (4) reclaiming, in the shared memory, a memory location occupied by the object whose reference was identified within the discard list of the oldest context. Various other apparatuses, systems, and methods are also disclosed.

Abstract: A method for sharing data in a multi-tenant database includes generating a share object in a first account comprising a share role. The method includes associating one or more access rights with the share role, wherein the one or more access rights indicate which objects in the first account are accessible based on the share object. The method includes granting, to a second account, cross-account access rights to the share role or share object in the first account. The method includes receiving a request from the second account to access data or services of the first account. The method further includes providing a response to the second account based on the data or services of the first account.

Abstract: A method of sharing data in a multi-tenant database includes generating a share object in a first account comprising a share role. The method includes associating one or more access rights with the share role, wherein the one or more access rights indicate which objects in the first account are accessible based on the share object. The method includes granting, to a second account, cross-account access rights to the share role or share object in the first account. The method includes receiving a request from the second account to access data or services of the first account. The method further includes providing a response to the second account based on the data or services of the first account.

Abstract: A system and method for data deduplication is presented. Data received from one or more computing systems is deduplicated, and the results of the deduplication process stored in a reference table. A representative subset of the reference table is shared among a plurality of systems that utilize the data deduplication repository. This representative subset of the reference table can be used by the computing systems to deduplicate data locally before it is sent to the repository for storage. Likewise, it can be used to allow deduplicated data to be returned from the repository to the computing systems. In some cases, the representative subset can be a proper subset wherein a portion of the referenced table is identified shared among the computing systems to reduce bandwidth requirements for reference-table synchronization.

Abstract: Some embodiments provide a method for efficient data message transfer across a hypervisor, service DCN, and containers implementing partner network services. The method allocates memory to a service DCN that operates a set of containers for providing partner network services for data messages received by the service DCN. The service DCN and the containers share the allocated memory and the method stores data messages received by the service DCN in the allocated memory. The method then accesses the data message stored in the shared memory from a set of partner network service containers to perform the partner network services. In some embodiments, the host machine or a process of the host machine on which the service DCN executes also shares the allocated memory. The host machine process, in some embodiments is a kernel process.

Abstract: A method for managing a multi-system shared memory includes: upon receiving a data write instruction for writing data to the shared memory, acquiring a data size of to-be-written data that is to be written to the shared memory; judging whether the shared memory includes a data block that matches the data size and is idle; if the shared memory does not include the data block that matches the data size and is idle, acquiring a first data block that has a memory size greater than the data size and is idle, such that the to-be-written data is written to the first data block; acquiring a remaining idle space of the first data block after the to-be-written data is written to the first data block; and generating a new data block based on the remaining idle space.

Abstract: Techniques for configuring paths for transmitting I/O operations may include: configuring a first path over which logical devices are exposed over a first port of a data storage system to a second port of a host, wherein the logical devices include a first logical device having a first service level objective and a second logical device having a second service level objective denoting a lower service level than the first service level objective; determining whether there is a service level objective violation of the first service level for the first logical device; and responsive to determining there is a service level objective violation for the first logical device, performing first processing that exposes the first logical device and the second logical device over different ports of the data storage system. Masking information may indicate which logical devices are exposed over which data storage system ports to which host ports.

Abstract: Apparatuses and methods for performing data migration operations are disclosed. An apparatus may include at least two interfaces, a first interface supporting data migration operations and a second interface supporting access operations associated with a host device. In some cases, the access operations may be a signal or protocol according to an industry standard or specification (e.g., a DRAM interface specification). The second interface may facilitate supporting industry standard applications, while the first interface supporting data migration operations may provide improved bandwidth for migrating data within the apparatus. The apparatus may include a buffer coupled with the interface and a bank cluster including two or more banks of memory cells. When a host device addresses a bank of the bank cluster, the apparatus may perform one or more data migration operations using the buffer and a different bank of the bank cluster.

Abstract: The present disclosure provides a method and an apparatus for erasing or writing Flash data. The method includes: reading an instruction for erasing or writing the data, the instruction for erasing or writing the data carrying start address information and end address information of a Flash memory where an operation of the instruction is to occur; querying whether the start address information and the end address information are in an address information table including one or more address ranges; and processing the instruction based on a result of the querying.

Abstract: Systems and methods are disclosed for reducing interdependency among control plane on a block storage system. Embodiments described herein can implement a key-value data store on the data plane servers. In one embodiment, the key-value store stores data regarding placement constraints and enables the block storage system to make placement decisions without control plane dependencies. In another embodiment, the key-value store persisted by the data plane enable the block storage system to migrate volumes while maintaining performance settings.

Abstract: A data storage management system comprises enhanced capabilities for automatically discovering operational characteristics of data storage devices installed in the system. A user interface enables end-users to submit requests for storage resources ranging from a simple request for a certain amount of storage space to more complex requests that specify the type of storage technology, the manufacturer, the I/O speed of the storage device, etc. The end-user also may include an expiration timeframe for the requested storage space. The system identifies storage devices that are suitable to the end-user's request, automatically provisions the storage space (e.g., LUN), and assigns it to the requestor. The assigned storage space may automatically expire, based on user-requested or system-provided expiration timeframes. Expired storage space is returned to a logical pool of available resources so that it may be assigned in response to other requests.

Abstract: Aspects of the disclosure relate to scenario based multiple application display on-screen. An enterprise application management server may determine one or more of secondary applications associated with a primary application. The enterprise application management server may receive information associated with a triggering event that occurred in the primary application. The enterprise application management server may determine a particular secondary application from the one or more secondary applications based on the received information associated with the triggering event. Accordingly, enterprise application management server may cause to display the particular secondary application simultaneously with the primary application on the screen of the mobile device.

Abstract: An apparatus may include a heterogeneous computing environment that may be controlled, at least in part, by a task scheduler in which the heterogeneous computing environment may include a processing unit having fixed logical circuits configured to execute instructions; a reprogrammable processing unit having reprogrammable logical circuits configured to execute instructions that include instructions to control processing-in-memory functionality; and a stack of high-bandwidth memory dies in which each may be configured to store data and to provide processing-in-memory functionality controllable by the reprogrammable processing unit such that the reprogrammable processing unit is at least partially stacked with the high-bandwidth memory dies. The task scheduler may be configured to schedule computational tasks between the processing unit, and the reprogrammable processing unit.

Abstract: A storage system including a storage controller for compressing a data from a host and a plurality of nonvolatile memory drives for writing the compressed data. The storage controller provides the host with a first logical address space as a logical storage area and includes a plurality of first physical address spaces corresponding to the first logical address space and manages storage areas of the plurality of nonvolatile memory drives. Each of the plurality of nonvolatile memory drives includes a second physical address space that manages a physical storage area of the nonvolatile memory and a second logical address space that corresponds to the second physical address space and to each of the plurality of first physical address spaces. The second logical address spaces and the first logical address space are managed with a common size and a common management size, and leading addresses are aligned with the management size.

Abstract: An approach is disclosed that caches distant memories within the storage a local node. The approach provides a memory caching infrastructure that supports virtual addressing by utilizing memory in the local node as a cache of distant memories for data granules. The data granules are accessed along with metadata and an ECC associated with the data granule. The metadata is updated to indicate storage of the selected data granule in the cache.

Abstract: Systems, devices and automated processes reduce the effects of unwanted interruption during video encoding by reserving header space at the outset of video encoding. This reserved space can be progressively filled on any periodic or other basis as encoding continues so that a recent header is always available. If an interruption occurs, only the video content encoded after the last header write will be lost, thereby greatly reducing the effects of the interruption.

Abstract: A system and method for performing garbage collection. A system includes a storage medium, a first table including entries which map a virtual address to locations in the storage medium, and a second table with entries which include a reverse mapping of a physical address in a data storage medium to one or more virtual addresses. A storage controller is configured to perform garbage collection. During garbage collection, the controller is configured to identify one or more entries in the second table which correspond to a segment to be garbage collected. In response to determining the first table includes a valid mapping for a virtual address included in an entry of the one of the one or more entries, the controller is configured to copy data from a first location identified in the entry to a second location in the data storage medium, and reclaim the first storage location.