Entry Replacement Strategy Patents (Class 711/159)
  • Patent number: 8769231
    Abstract: A crossbar switch device for a processor block ASIC core and a method for a flush-posted-write(s)-before-read mode thereof are described. Operation for the flush-posted-write(s)-before-read mode is set in a first processor block interface coupled to programmable logic fabric. At least one write command is sent from a transaction initiating device instantiated using the programmable logic fabric to the first processor block interface. The at least one write command is posted in the first processor block interface. At least one write command received is stored in a command queue of the crossbar switch device. A read command initiated by a microprocessor is sent to the crossbar switch device. The at least one write command has an address overlap with the read command with respect to a destination target. The read command is temporarily blocked in the crossbar switch device until a command phase of the at least one write command is completed.
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: July 1, 2014
    Assignee: Xilinx, Inc.
    Inventors: Ahmad R. Ansari, Jeffery H. Appelbaum, Kunal R. Shenoy
  • Patent number: 8769220
    Abstract: A method and apparatus for mitigating the performance impact of background or idle time processing during interactive computing sessions. One embodiment of the present invention is a method for mitigating performance impact of background or idle time processing on interactive applications comprising identifying executable and data pages in physical memory that are associated with an interactive application that is temporarily unused and preventing any of the identified executable and data pages from paging out.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: July 1, 2014
    Assignee: Symantec Corporation
    Inventors: Bruce E. McCorkendale, Mark W. Spiegel, Paul Agbabian, Shaun Cooley
  • Publication number: 20140181432
    Abstract: Priority-based garbage collection utilizes attributes of data stored in the non-volatile memory array in order to improve efficiency of garbage collection and of the overall data storage system. A set of low priority data can be selectively evicted from a non-volatile memory array. This can, for example, reduce write amplification associated with garbage collection. Another set of low priority data can be regrouped or consolidated in a different region of the non-volatile memory array. In addition, flushing of data can be performed in order to enhance or optimize garbage collection. Performance and endurance can thereby be improved.
    Type: Application
    Filed: December 26, 2012
    Publication date: June 26, 2014
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: WESTERN DIGITAL TECHNOLOGIES, INC.
  • Publication number: 20140173226
    Abstract: The presently disclosed subject matter includes a method and system for enabling the deletion of logical objects characterized by an object identifier (OID). Upon restart following a system interruption, one or more logical objects are identified, each object being addressed by an interrupted delete request. For each identified logical object performing a deletion, the deletion including: reading one or more physical blocks stored in a physical storage space, wherein the one or more physical blocks were linked to the identified logical object before the system interruption, each of the physical blocks includes an OID stored therein indicating a logical object currently linked to the respective physical block; obtaining OIDs stored respectively in the one or more physical blocks; and freeing those physical blocks from among the one or more physical blocks, which store an OID identical to the respective OID of the identified logical object.
    Type: Application
    Filed: December 13, 2012
    Publication date: June 19, 2014
    Applicant: INFINIDAT LTD.
    Inventor: Israel GOLD
  • Publication number: 20140173228
    Abstract: In one example embodiment, a memory system includes a hierarchical first-in first-out (FIFO) memory configured to store data, and a FIFO controller configured to control inputting and outputting of data to and from the FIFO memory, wherein the FIFO memory includes a first layer. The first layer includes a high-speed input FIFO memory configured to receive data from an external device and a high-speed output FIFO memory configured to output data to the external device. The FIFO memory further includes a second layer. The second layer includes a main FIFO memory configured to receive data from the high-speed input FIFO memory and output data to the high-speed output FIFO memory.
    Type: Application
    Filed: November 5, 2013
    Publication date: June 19, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Han LEE, Jae-Sop KONG
  • Publication number: 20140173227
    Abstract: A method and apparatus for managing a memory in a portable terminal including a main memory, a secondary memory, and a plurality virtual machines allocated by partitioning the main memory are provided. The method includes generating, by the virtual machines, monitoring information by monitoring access to the main memory and the secondary memory and swapping out with respect to the secondary memory; determining memory allocation amounts for each of the virtual machines by using the monitoring information; and allocating the main memory to the virtual machines in a partitioning scheme based on the determined memory allocation amounts.
    Type: Application
    Filed: February 25, 2013
    Publication date: June 19, 2014
    Applicants: Sungkyunkwan University Foundation for Corporate Collaboration, Samsung Electronics Co., Ltd.
    Inventors: Changwoo MIN, Inhyeok KIM, Taehyoung KIM, Young Ik EOM
  • Patent number: 8756376
    Abstract: A method of operating a memory system is provided. The method includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: June 17, 2014
    Assignee: Spansion LLC
    Inventor: Tzungren Allan Tzeng
  • Patent number: 8756383
    Abstract: A mechanism for random cache line selection in virtualization systems is disclosed. A method includes maintaining a secondary data structure representing a plurality of memory pages, the secondary data structure indexed by a subset of each memory page, determining an index of a received new memory page by utilizing a subset of the new memory page that is a same size and at a same offset as the subset of each memory page, comparing the index of the new memory page with the indices of the secondary data structure for a match, utilizing a main data structure to perform a full page memory comparison with the new memory page if a match is found in the secondary data structure, and updating at least one of the size of the subset, the number of subsets, and the offsets of the subsets used to index the memory page.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: June 17, 2014
    Assignee: Red Hat Israel, Ltd.
    Inventor: Michael Tsirkin
  • Patent number: 8750144
    Abstract: Aspects of the invention provide for updating TCAMs while minimizing TCAM entry updates to add/delete ACL rules. For example, one aspect provides a method for minimizing updates in a router forwarding table, such as a TCAM, including a plurality of rules indexed by priority. This method comprises providing a proposed rule to be added to the router forwarding table, identifying a range of candidate entries in the router forwarding table for the proposed rule, determining a minimum set of rules to relocate, and creating an empty entry in the range of candidate entries based upon the minimum set of rules to relocate. The method may further comprise reallocating the minimum set of rules by, for example, shifting the minimum set of rules in sequence based on priority, and adding the proposed rule to the empty entry in the range of candidate entries.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: June 10, 2014
    Assignee: Google Inc.
    Inventors: Junlan Zhou, Zhengrong Ji
  • Patent number: 8751742
    Abstract: A method of extending memory card data storage capacity to a remote data store includes storing an initial data item received from a host device in a local memory cache, and wirelessly transmitting the initial data item from the local memory cache to the remote data store via a network interface that includes at least one wireless communication transceiver. The method also includes substituting a corresponding, smaller transcoded data item received from the remote data store for the initial data item in the local memory cache.
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: June 10, 2014
    Assignee: Telefonaktiebolaget L M Ericsson (Publ)
    Inventor: Johannes Wilke
  • Publication number: 20140149694
    Abstract: A system-on-chip is provided which includes a data producer; a FIFO buffer which stores data transferred from the data producer at a memory area corresponding to a write pointer; a first consumer which pops data of a memory area corresponding to a first read pointer of the FIFO buffer out; and a second consumer which pops data of a memory area corresponding to a second read pointer of the FIFO buffer out. The FIFO buffer requests a pop-out operation at the second consumer according to the difference between the write pointer and the first read pointer or overwrites data provided from the data producer at a memory area corresponding to the second read pointer.
    Type: Application
    Filed: November 21, 2013
    Publication date: May 29, 2014
    Inventors: Donghan Lee, Jaesop Kong, Keemoon Chun
  • Patent number: 8737417
    Abstract: A computer-implemented system and method for a lock-less, zero data copy messaging mechanism in a multi-core processor for use on a modem in a telecommunications network are described herein. The method includes, for each of a plurality of processing cores, acquiring a kernel to user-space (K-U) mapped buffer and corresponding buffer descriptor, inserting a data packet into the buffer; and inserting the buffer descriptor into a circular buffer. The method further includes creating a frame descriptor containing the K-U mapped buffer pointer, inserting the frame descriptor onto a frame queue specified by a dynamic PCD rule mapping IP addresses to frame queues, and creating a buffer descriptor from the frame descriptor.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: May 27, 2014
    Assignee: Alcatel Lucent
    Inventors: Mohammad R. Khawer, Lina So
  • Patent number: 8738850
    Abstract: Reliable storage for database management systems (DBMS) running on memory devices such as NAND type flash memory utilizes minimum I/O overhead and provides maximum data durability. A virtual page map is utilized between the flash memory and a page access component to record changes to the DBMS pages and prevent overwriting or data loss. There is no need for journaling and logging, and performance is increased by reducing the write and erase counts on the flash memory. The logical page numbers of the DBMS are mapped to physical page numbers in the page map, such that the virtual page map allocates an available page from the physical pages when changes to a page occur, and the updated information is stored in the allocated page. The allocated page number is mapped to the logical page number of the original page, thus maintaining a modified page representation while preventing physical in-place updates.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: May 27, 2014
    Assignee: Oracle International Corporation
    Inventors: SangCheol Lee, BongSoo Ko, HyungGook Yoo, SongHee Kang
  • Patent number: 8738876
    Abstract: A method for performing block management is provided, where the method is applied to a controller of a Flash memory that includes a plurality of blocks. The method includes: selecting a target block having a least erase count from at least one portion of blocks in a data region of the Flash memory, and utilizing the target block as a block to be erased, wherein serial numbers of the at least one portion of blocks correspond to order of last update of the at least one portion of blocks, respectively; and determining whether to move/copy valid data of the target block into a heavily worn block or a lightly worn block according to a serial number of the target block, where the degree of wear of the heavily worn block is higher than that of the lightly worn block. An associated memory device and a controller thereof are also provided.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: May 27, 2014
    Assignee: Silicon Motion Inc.
    Inventor: Yang-Chih Shen
  • Patent number: 8738846
    Abstract: A file system-aware SSD management system including an SSD management module that incorporates both file system information and information related to the underlying physical solid-state storage media into its operations is described. Also described are related methods for performing data management operations in a file system-aware manner. By incorporating both file system and physical storage information, the system may achieve various advantages over conventional systems, such as enhanced I/O performance, simplified SSD firmware, and extended SSD lifespan. Moreover, by moving solid-state management functions above the firmware level, the system may enable the simultaneous management of a pool of multiple SSDs.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: May 27, 2014
    Assignee: Arkologic Limited
    Inventors: Kyquang Son, Ronald Lee, Henry C. Lau, Rajesh Ananthanarayanan
  • Patent number: 8725962
    Abstract: A main memory data rewriting device includes a rewrite condition analysis unit configured to analyze a rewrite condition for target data in main memory data stored in a main memory before deactivation of an information processing device, and create a first processing content to acquire environment data substituting the target data from outside of the information processing device and a second processing content to rewrite the target data to the environment data, an environment data processing unit configured to acquire the environment data according to the first processing content when the information processing device is temporarily activated at an activation time set to rewrite the target data during a deactivating period of the information processing device, and a rewrite processing unit configured to rewrite a region of a nonvolatile storage medium in which the target data is stored with the environment data according to the second processing content.
    Type: Grant
    Filed: September 17, 2009
    Date of Patent: May 13, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keisuke Mera, Takeshi Ishihara, Nobuhiko Sugasawa
  • Patent number: 8725963
    Abstract: A computer system has a random access memory (RAM) that stores currently used memory pages and SWAP storage for storing memory page that is not in use. If the process requires memory page stored on the SWAP storage, a corresponding page is loaded to RAM. If the page in RAM is not currently in use, it is moved to the SWAP storage. The computer system has a number of Virtual Environments (i.e., Containers) that run their own processes, a VE/Container RAM and a virtual SWAP storage. The Container processes have access to a VE/Container RAM. When the Container process request OS for memory, the memory manager allocates memory pages in the RAM and also allocates memory pages for the Container process in the VE/Container RAM. If no free virtual RAM is available, the process data is moved to the virtual SWAP storage.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: May 13, 2014
    Assignee: Parallels IP Holdings GmbH
    Inventors: Pavel Emelianov, Kirill Korotaev, Alexander G. Tormasov
  • Publication number: 20140129786
    Abstract: A translation lookaside buffer coherency unit with Emulated Purge (TCUEP) fetches first instructions for execution in a multi-processor system. The TCUEP associates a first instruction timestamp with each of the first instructions. The TCUEP receives a multi-processor coherency operation and increments the first timestamp value in a master-tag register to form a second timestamp value after receiving the multi-processor coherency operation. The TCUEP fetches, by an instruction fetch unit in the first microprocessor, second instructions for execution in the multiprocessor system. The TCUEP associates a second instruction timestamp with each of the second instructions. The TCUEP enables an emulated purge mechanism to suppress hits in the translation lookaside buffers for the second instructions. The TCUEP after determining the first instructions are complete, purges entries in the translation lookaside buffers and disables the emulated purge mechanism.
    Type: Application
    Filed: November 2, 2012
    Publication date: May 8, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joerg Deutschle, Ute Gaertner, Lisa C. Heller
  • Patent number: 8719511
    Abstract: A system and method is provided wherein, in one aspect, a currently-requested item of information is stored in a cache based on whether it has been previously requested and, if so, the time of the previous request. If the item has not been previously requested, it may not be stored in the cache. If the subject item has been previously requested, it may or may not be cached based on a comparison of durations, namely (1) the duration of time between the current request and the previous request for the subject item and (2) for each other item in the cache, the duration of time between the current request and the previous request for the other item. If the duration associated with the subject item is less than the duration of another item in the cache, the subject item may be stored in the cache.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: May 6, 2014
    Assignee: Google Inc.
    Inventors: Timo Burkard, David Presotto
  • Patent number: 8719509
    Abstract: In an embodiment, a cache stores tags for cache blocks stored in the cache. Each tag may include an indication identifying which of two or more replacement policies supported by the cache is in use for the corresponding cache block, and a replacement record indicating the status of the corresponding cache block in the replacement policy. Requests may include a replacement attribute that identifies the desired replacement policy for the cache block accessed by the request. If the request is a miss in the cache, a cache block storage location may be allocated to store the corresponding cache block. The tag associated with the cache block storage location may be updated to include the indication of the desired replacement policy, and the cache may manage the block in accordance with the policy. For example, in an embodiment, the cache may support both an LRR and an LRU policy.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: May 6, 2014
    Assignee: Apple Inc.
    Inventors: James Wang, Zongjian Chen, James B. Keller, Timothy J. Millet
  • Patent number: 8711164
    Abstract: An integrated memory controller (IMC) may sit on the main CPU bus or a high speed system peripheral bus and couple to system memory. The IMC may use a lossless data compression and decompression scheme for improved performance. The IMC may also include microcode for specific decompression of particular data formats such as digital video and digital audio. Compressed data may be decompressed in the IMC and stored into system memory or saved in the system memory in compressed format. Internal memory mapping may allow for format definition spaces which may define the format of the data and the data type to be read or written. Software overrides may be placed in applications software in systems that desire to control data decompression at the software application level.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: April 29, 2014
    Assignee: Intellectual Ventures I LLC
    Inventor: Thomas A. Dye
  • Patent number: 8713065
    Abstract: A hybrid object tree that interconnects individual data objects of different data types from a group of different input data sources is provided. The instantiated data objects of the hybrid object tree include an internal dynamic data area that encapsulates at least one reference to an original input data source. At least one attribute is identified that is unavailable at the referenced original input data source of a first instantiated data object of the hybrid object tree. The at least one attribute is added to the first instantiated data object of the hybrid object tree within the internal dynamic data area of the first instantiated data object.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: April 29, 2014
    Assignee: International Business Machines Corporation
    Inventor: Arthur L. De Magalhaes
  • Patent number: 8713066
    Abstract: Embodiments of the invention provide a storage subsystem comprising a non-volatile solid-state memory array and a system operation module for managing memory operations. The system operation module is configured to store system operation data in a data structure that includes linked lists for storing system operation data, with at least some lists including entries referencing blocks in the solid-state memory array belonging to a category. The system operation module is further configured to (1) move a particular entry from a first linked list to a second linked list when a block referenced by the particular entry in the first linked list has met a condition for being classified in a new category that is different from that of the blocks referenced by entries in the first linked list, and (2) update entries within the first and second linked lists so that the dependencies in the linked lists are maintained.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: April 29, 2014
    Assignee: Western Digital Technologies, Inc.
    Inventors: Jerry Lo, Lan D. Phan, Cliff Pajaro
  • Publication number: 20140115238
    Abstract: According to various embodiments, a storage controller configured to control storage of data in a pre-determined area of a storage medium may be provided. The storage controller may include a memory configured to store a write pointer, a reclaim pointer, and a wrapped around pointer. The write pointer may indicate a location of the storage medium to write incoming data. The reclaim pointer may indicate a location of the storage medium to perform a space reclamation. The wrapped around pointer may indicate a location of the storage medium where writing is to continue if writing of data reaches an end of the pre-determined area.
    Type: Application
    Filed: October 17, 2013
    Publication date: April 24, 2014
    Applicant: Agency for Science, Technology and Research
    Inventors: Weiya Xi, Sufui Sophia Tan, Khai Leong Yong, Chun Teck Lim, Chao Jin, Zhi Yong Ching
  • Patent number: 8706782
    Abstract: Systems and methods for optimal data storage are provided. The method comprises storing data objects that are most closely related in a storage container by modeling a constraint satisfaction problem for placement of said data objects in one or more storage containers, wherein a weight is assigned to an edge connecting two data objects based on an association defining relationships between the two data objects connected by said edge, taking into account certain penalties for placing multiple copies of the same object in the one or more storage containers, and wherein a storage container comprises a logical or physical storage area as a unit of storage.
    Type: Grant
    Filed: June 12, 2011
    Date of Patent: April 22, 2014
    Assignee: International Business Machines Corporation
    Inventors: Simona Cohen, Avraham Harpaz
  • Patent number: 8706982
    Abstract: A method and apparatus for providing efficient strong atomicity is herein described. Optimized strong operations may be inserted at non-transactional read accesses to provide efficient strong atomicity. A global transaction value is copied at a beginning of a non-transactional function to a local transaction value; essentially creating a local timestamp of the global transaction value. At a non-transactional memory access within the function, a counter value or version value is compared to the LTV to see if a transaction has started updating memory locations, or specifically the memory location accessed. If memory locations have not been updated by a transaction, execution is accelerated by avoiding a full set of slowpath strong atomic operations to ensure validity of data accessed. In contrast, the slowpath operations may be executed to resolve contention between a transactional and non-transaction access contending for the same memory location.
    Type: Grant
    Filed: December 30, 2007
    Date of Patent: April 22, 2014
    Assignee: Intel Corporation
    Inventors: Bratin Saha, Ali-Reza Adl-Tabatabai, Cheng Wang, Tatiana Shpeisman
  • Patent number: 8706983
    Abstract: A method and system for performing garbage collection operations on update blocks in a memory device using volatile memory is disclosed. When performing a garbage collection operation, a first part of the data related to the garbage collection operation is written to a volatile memory in the memory device, and a second part of the data related to the garbage collection operation is written to a non-volatile memory in the memory device. The first part of the data that is written to the volatile memory (such as a random access memory) may comprise control information (such as mapping information of the logical addressable unit to a physical metablock). The second part of the data related to the garbage collection that is written to the non-volatile memory (such as a flash memory) may comprise the consolidated data in the update block.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: April 22, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: Neil David Hutchison, Steven Sprouse
  • Patent number: 8706985
    Abstract: The present invention is directed to systems and methods for optimizing garbage collection in data storage. The data storage may be a shingled disk drive or a non-volatile solid-state memory device. Garbage collection is optimized by selectively saving data read from certain locations of the data storage in response to host read commands and using the saved data for subsequent garbage collection operations. The decision of whether to save data may be based on a number of criteria, including whether the data is located in an area of the data storage that is due to be garbage collected in the near future. In this manner, certain garbage collection operations can be performed without having to re-read the saved data.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: April 22, 2014
    Assignee: Western Digital Technologies, Inc.
    Inventors: William B. Boyle, Robert M. Fallone
  • Patent number: 8706979
    Abstract: A method and apparatus for handling reusable and non-reusable code is herein described. Page table entries include code reuse and locality fields to hold hints for associated pages. If a code reuse and locality field holds a non-reusable value to indicate an associated page holds non-reusable code, then an instruction decoded from the associated page is not stored in the trace to obtain maximum efficiency and power savings from the trace cache and decode logic.
    Type: Grant
    Filed: December 30, 2007
    Date of Patent: April 22, 2014
    Assignee: Intel Corporation
    Inventor: Ron Gabor
  • Patent number: 8706984
    Abstract: A delete notification can be received at a storage stack filter in a storage stack. It can be determined whether the delete notification applies to an entire storage device. If the delete notification does not apply to the entire storage device, a first set of actions can be taken with the storage stack filter in response to the delete notification. If the delete notification does apply to the entire storage device, a second set of actions can be taken with the storage stack filter in response to the delete notification.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: April 22, 2014
    Assignee: Microsoft Corporation
    Inventors: Karan Mehra, Andrew Herron
  • Patent number: 8706994
    Abstract: Various embodiments for synchronization of source and replicated instances of sequential access storage components in a computing environment by a processor device are provided. A replication synchronization table (RST) of a source instance is updated at a source component with the compacted information. Based on the RST of the source instance and the RST of the replicated instance, data representative of a most recent position on the source component from which data should be transmitted to a replicated component to achieve a full synchronization is determined.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: April 22, 2014
    Assignee: International Business Machines Corporation
    Inventors: Shay H. Akirav, Yariv Bachar, Elena Drobchenko, Samuel Krikler, Aharon Lazar, Itay Maoz, Dan Melamed, Gil E. Paz
  • Publication number: 20140101396
    Abstract: Embodiments of the invention relate to counter-based entry invalidation for a metadata previous write queue (PWQ). An aspect of the invention includes writing an address into an entry in the metadata PWQ, the address being associated with an instance of metadata received from a pipeline and setting a valid tag associated with the entry in the metadata PWQ to valid. Another aspect of the invention includes initializing a counter to zero and incrementing the counter based on receiving a count signal from the pipeline until the counter is equal to a threshold. Yet another aspect of the invention includes setting the valid tag to invalid based on the counter being equal to the threshold.
    Type: Application
    Filed: December 10, 2013
    Publication date: April 10, 2014
    Applicant: International Business Machines Corporation
    Inventors: James J. Bonanno, Brian R. Prasky
  • Patent number: 8694562
    Abstract: A generational garbage collector utilizes a pool-based heap to store objects dynamically generated at runtime. The pool-based heap is configured as a collection of pools where each pool stores objects associated with the same generation. Each pool contains a pool header that identifies the generation of all objects within the pool. The pools are aligned to a memory boundary that is a multiple of the pool size. Select bits of an object's memory address may be used to access the pool header so that an object's generation, which is needed in various phases of the garbage collection process, is readily determined.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: April 8, 2014
    Assignee: Microsoft Corporation
    Inventors: Abhinaba Basu, Jaiprakash Sharma
  • Patent number: 8687009
    Abstract: An image processing apparatus for managing a memory device having a plurality of storage areas including a storage area storing out-of-use information and a free area storing no information, the image processing apparatus comprises memory control unit adapted to determine whether or not there is a storage area storing the out-of-use information based on a request for storing information and determining the storage area storing the out-of-use information as an area for storing the information, in a case where the storage area exists; and information writing unit adapted to overwrite generated information to the storage area determined by the memory control unit.
    Type: Grant
    Filed: July 9, 2009
    Date of Patent: April 1, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hideyuki Kitani
  • Patent number: 8688754
    Abstract: At least one region of a heap that includes memory allocations is analyzed, using age and occupancy criteria, across a number of local garbage collection cycles using a processor executing a region-based garbage collector. Based upon the analyzed age and occupancy criteria of the at least one region, at least one stable region in age and occupancy is identified among the at least one region of the heap across the number of local garbage collection cycles. Maintenance of a remembered set (RS) of external references into the at least one stable region is temporarily stopped for each identified stable region during at least one additional local garbage collection cycle.
    Type: Grant
    Filed: September 19, 2012
    Date of Patent: April 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Peter W. Burka, Aleksandar Micic, Ryan A. Sciampacone
  • Patent number: 8688743
    Abstract: A hybrid object tree that interconnects individual data objects of different data types from a group of different input data sources is provided. The instantiated data objects of the hybrid object tree include an internal dynamic data area that encapsulates at least one reference to an original input data source. At least one attribute is identified that is unavailable at the referenced original input data source of a first instantiated data object of the hybrid object tree. The at least one attribute is added to the first instantiated data object of the hybrid object tree within the internal dynamic data area of the first instantiated data object.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: April 1, 2014
    Assignee: International Business Machines Corporation
    Inventor: Arthur L. De Magalhaes
  • Patent number: 8688945
    Abstract: A storage device includes a controller that is configured to execute safe deletion operations so as to free up storage space on the device in response to triggering events. The safe deletion operations ensure that the data states of a host device making use of the storage device and the storage device itself are synchronized so as to prevent deletion of data from the storage device before it is offloaded to another storage platform.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: April 1, 2014
    Assignee: Eye-Fi, Inc.
    Inventors: Berend Ozceri, Eugene M. Feinberg
  • Patent number: 8688932
    Abstract: In a virtual computer system controlling a disk volume and a virtual server which is connected to the disk volume, to which the area of the disk volume is allocated as a virtual disk and which executes a process using the allocated virtual disk, the virtual computer system erases information stored in the virtual disk allocated to the virtual server to be deleted correspondingly with the deletion of the virtual server. An administrative server may be provided to select a server system which is low in load from among plural server systems controlling virtual servers as a server system for erasing information stored in the virtual disk allocated to the virtual server to be deleted.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: April 1, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Eri Kataoka, Yoshifumi Takamoto
  • Patent number: 8683150
    Abstract: A storage system includes a plurality of data vats, and a processor including an optimizing unit that optimizes a value of data stored in the storage system. The optimizing unit optimizes the value by computing and implementing an optimal decision for allocating new data to a first data vat of the plurality of data vats, moving existing data from at least a second data vat of the plurality of data vats to the first data vat, and deleting existing data from the first data vat, based on an amount of data in each of the plurality of data vats.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Nikhil Bansal, Frederick Douglis, Lisa Karen Fleischer, Kirsten Weale Hildrum, Akshay Kumar Reddy Katta, John Davis Palmer, Elizabeth Suzanne Richards, David Tao, William Harold Tetzlaff, Joel Leonard Wolf, Philip Shi-lung Yu
  • Patent number: 8683534
    Abstract: A method and apparatus for storing and distributing video information in an interactive information distribution system by storing video information on either a centralized or de-centralized secondary storage partition in a network of provider and subscriber equipment, and therein distributing the video information to a subscriber having made a request for such video information.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: March 25, 2014
    Assignee: Comcast IP Holdings I, LLC
    Inventors: James B. Armstrong, Christopher W. B. Goode
  • Patent number: 8677065
    Abstract: Aspects of the innovations herein are consistent with a storage system for storing variable sized objects. The storage system may be a transaction-based system that uses variable sized objects to store data. The storage system may be implemented using arrays disks that are arranged in ranks. Each rank may include multiple stripes. Each stripe may be read and written as a convenient unit for maximum performance. A rank manager may be provided to dynamically configure the ranks to adjust for failed and added disks by selectively shortening and lengthening the stripes. The storage system may include a stripe space table that contains entries describing the amount of space used in each stripe. An object map may provide entries for each object in the storage system describing the location (e.g., rank, stripe and offset values), the length and version of the object.
    Type: Grant
    Filed: April 3, 2011
    Date of Patent: March 18, 2014
    Inventor: Robert E. Cousins
  • Patent number: 8677071
    Abstract: Techniques are described for controlling processor cache memory within a processor system. Cache occupancy values for each of a plurality of entities executing the processor system can be calculated. A cache replacement algorithm uses the cache occupancy values when making subsequent cache line replacement decisions. In some variations, entities can have occupancy profiles specifying a maximum cache quota and/or a minimum cache quota which can be adjusted to achieve desired performance criteria. Related methods, systems, and articles are also described.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: March 18, 2014
    Assignee: Virtualmetrix, Inc.
    Inventors: Gary Allen Gibson, Valeri Popescu
  • Patent number: 8677054
    Abstract: A method includes storing data in a non-volatile memory that includes multiple memory blocks. At least first and second regions are defined in the non-volatile memory. A definition is made of a first over-provisioning ratio between a first logical address space and a first physical memory space of the first region, and a second over-provisioning ratio, different from the first over-provisioning ratio, between a second logical address space and a second physical memory space of the second region. Portions of the data are compacted, individually within each of the first and second regions and independently of the other region, by copying the portions from one or more source memory blocks to one or more destination memory blocks using the first and second over-provisioning ratios, respectively.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: March 18, 2014
    Assignee: Apple Inc.
    Inventors: Avraham Meir, Oren Golov
  • Publication number: 20140075137
    Abstract: A method of managing a memory that can quickly secure an available space is provided. The method includes recording compression ratios of data stored in pages of a main memory, and securing space of the main memory when the main memory has insufficient available space, by compressing data of pages having a compression ratio of a standard value or greater among pages of the main memory and storing the compressed data in the main memory.
    Type: Application
    Filed: September 13, 2013
    Publication date: March 13, 2014
    Applicant: Samsung Electronics Co. Ltd.
    Inventor: Hee-Sub SHIN
  • Publication number: 20140075136
    Abstract: A method for protecting page-level metadata in a storage system is provided. The method includes providing in a page table first protection data, receiving a command to read data from a page of the storage system corresponding to the page table, and comparing first protection data to second protection data. If the first protection data is different than the second protection data, then the method includes identifying third protection data in the storage system and comparing the third protection data to the first protection data. If the third protection data is different than the first protection data, then the method includes determining that the page-level metadata is inconsistent.
    Type: Application
    Filed: September 12, 2012
    Publication date: March 13, 2014
    Applicant: DOT HILL SYSTEMS CORPORATION
    Inventor: Ian Robert Davies
  • Patent number: 8671246
    Abstract: An information processing system performs a prefetch for predicting data that is likely to be accessed by a central processing unit, reading the predicted data from a main memory, and storing the data in a cache area in advance. The information processing system includes a usage information storage unit that stores therein usage information indicating whether prefetched data has been accessed; and a usage information writing unit that writes the usage information of the prefetched data in the usage information storage unit.
    Type: Grant
    Filed: July 28, 2009
    Date of Patent: March 11, 2014
    Assignee: Fujitsu Limited
    Inventors: Takashi Toyoshima, Shuji Yamamura, Atsushi Mori, Takashi Aoki
  • Publication number: 20140068205
    Abstract: Described are systems and methods for transmitting data at an aggregation device. The aggregation device includes a record queue and an output bypass queue. The data is received from an electronic device. A record is generated of the received data. The record is placed in the record queue. A determination is made that the record in the record queue is blocked. The blocked record is transferred from the record queue to the output bypass queue.
    Type: Application
    Filed: September 4, 2012
    Publication date: March 6, 2014
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: David E. Mayhew, Mark Hummel, Michael J. Osborn
  • Publication number: 20140068206
    Abstract: Methods, systems, and computer program products are provided for optimizing selection of files for eviction from a first storage pool to free up a predetermined amount of space in the first storage pool. A method includes analyzing an effective space occupied by each file of a plurality of files in the first storage pool, identifying, from the plurality of files, one or more data blocks making up a file to free up the predetermined amount of space based on the analysis of the effective space of each file of the plurality of files, selecting one or more of the plurality of files as one or more candidate files for eviction, based on the identified one or more data blocks, and evicting the one or more candidate files for eviction from the first storage pool to a second storage pool.
    Type: Application
    Filed: November 5, 2013
    Publication date: March 6, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Duane M. BALDWIN, Sandeep R. PATIL, Riyazahamad M. SHIRAGUPPI, Prashant SODHIYA
  • Publication number: 20140059291
    Abstract: An invention is provided for protecting the data integrity of a cached storage device in an alternate operating system (OS) environment. The invention includes replacing an actual partition table for a disk with a dummy partition table. The dummy partition table is designed to render data on the disk inaccessible when the dummy partition table is used by an OS to access the data. During operation, the data on the disk can be accessed using information based on the actual partition table. In response to receiving a request to disable caching, the dummy partition table on the disk is replaced with the actual partition table, thus rendering the data on the formally cached disk accessible in an alternate OS environment where appropriate caching software is not present.
    Type: Application
    Filed: August 27, 2012
    Publication date: February 27, 2014
    Inventors: Kashif Memon, Pradeep Bisht
  • Publication number: 20140059271
    Abstract: A method includes receiving one or more storage commands and at least one flush command in a storage device, which includes a non-volatile memory and a volatile buffer for buffering data received for storage in the non-volatile memory. The flush command instructs the storage device to commit the data buffered in the volatile buffer to the non-volatile memory. The storage commands are executed in accordance with a first storage rule. The flush command is executed in accordance with a second storage rule having smaller latency relative to the first storage rule.
    Type: Application
    Filed: August 27, 2012
    Publication date: February 27, 2014
    Applicant: APPLE INC.
    Inventors: Avraham Poza Meir, Guy Ben-Yehuda, Oren Golov, Ori Isachar, Roman Guy, Yair Schwartz