Entry Replacement Strategy Patents (Class 711/159)
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Patent number: 8849351Abstract: The present invention provides a method involving at least one mobile unit having at least one first session with a base station router. The method includes vacating at least one first session associated with the at least one mobile unit.Type: GrantFiled: December 29, 2006Date of Patent: September 30, 2014Assignee: Alcatel LucentInventors: John K. Burgess, Ken Del Signore, David Vollman, David Welch
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Patent number: 8849875Abstract: At least one region of a heap that includes memory allocations is analyzed, using age and occupancy criteria, across a number of local garbage collection cycles using a processor executing a region-based garbage collector. Based upon the analyzed age and occupancy criteria of the at least one region, at least one stable region in age and occupancy is identified among the at least one region of the heap across the number of local garbage collection cycles. Maintenance of a remembered set (RS) of external references into the at least one stable region is temporarily stopped for each identified stable region during at least one additional local garbage collection cycle.Type: GrantFiled: October 15, 2013Date of Patent: September 30, 2014Assignee: International Business Machines CorporationInventors: Peter W. Burka, Aleksandar Micic, Ryan A. Sciampacone
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Patent number: 8843721Abstract: A data storage system comprises a controller, a first lower performance storage medium and a second higher performance storage medium. The controller is connected to the storage mediums and is arranged to control I/O access to the storage mediums. The controller is further arranged to store an image on the first storage medium, initiate a copy function from the first storage medium to the second storage medium, direct all I/O access for the image to the second storage medium, periodically age data from the second storage medium to the first storage medium, create a new empty bitmap for each period, and in response to an I/O access for data in the image, update the latest bitmap to indicate that the data has been accessed and update the previous bitmaps to indicate that the data has not been accessed.Type: GrantFiled: March 14, 2013Date of Patent: September 23, 2014Assignee: International Business Machines CorporationInventors: Carlos Francisco Fuente, William James Scales, Barry Douglas Whyte
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Patent number: 8843712Abstract: A method and system for performing sensed garbage collection in a memory is disclosed. In one embodiment, a method includes measuring arrival times of read/write commands received from a processor executing an application; transforming the arrival times from a time domain to frequency domain data; locking onto a phase of the read/write commands; determining predicted arrival times of future read/write commands; creating a real-time schedule of memory requests using the arrival times of the read/write commands and the predicted arrival times of the future read/write commands; using the real-time schedule to sense idle periods where the application will not make a request of the memory; and performing garbage collection in the memory during at least one of the idle periods.Type: GrantFiled: January 28, 2013Date of Patent: September 23, 2014Assignee: Marvell International Ltd.Inventor: Ronald D. Smith
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Publication number: 20140281295Abstract: A technique for supporting user mode specification of RCU grace period latency to an operating system kernel-level RCU implementation. Non-expedited and expedited RCU grace period mechanisms are provided for invocation by RCU updaters performing RCU update operations to respectively initiate non-expedited and expedited grace periods. An expedited grace period indicator in a kernel memory space is provided for indicating whether a non-expedited RCU grace period or an expedited RCU grace period should be invoked. The non-expedited RCU grace period mechanism is adapted to check the expedited grace period indicator, and if an expedited RCU grace period is indicated, to invoke the expedited grace period mechanism. A communication mechanism is provided for use by a user mode application executing in a user memory space to manipulate the expedited grace period indicator in the kernel memory space, and thereby control whether an expedited or non-expedited RCU grace period should be used.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Paul E. McKenney
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Publication number: 20140281297Abstract: Techniques are provided by which memory pages may be migrated among PPU memories in a multi-PPU system. According to the techniques, a UVM driver determines that a particular memory page should change ownership state and/or be migrated between one PPU memory and another PPU memory. In response to this determination, the UVM driver initiates a peer transition sequence to cause the ownership state and/or location of the memory page to change. Various peer transition sequences involve modifying mappings for one or more PPU, and copying a memory page from one PPU memory to another PPU memory. Several steps in peer transition sequences may be performed in parallel for increased processing speed.Type: ApplicationFiled: December 19, 2013Publication date: September 18, 2014Applicant: NVIDIA CORPORATIONInventors: Jerome F. DULUK, JR., John MASHEY, Mark HAIRGROVE, Chenghuan JIA, Cameron BUSCHARDT, Lucien DUNNING, Brian FAHS
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Publication number: 20140281296Abstract: A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.Type: ApplicationFiled: October 16, 2013Publication date: September 18, 2014Applicant: NVIDIA CORPORATIONInventors: Jerome F. DULUK, JR., Cameron BUSCHARDT, Sherry CHEUNG, James Leroy DEMING, Samuel H. DUNCAN, Lucien DUNNING, Robert GEORGE, Arvind GOPALAKRISHNAN, Mark HAIRGROVE, Chenghuan JIA, John MASHEY
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Publication number: 20140281298Abstract: An approach is provided for suggesting data for deletion from an electronic data storage medium. An external device detects initiation of transfer of data from first storage medium to second storage medium. Next, the external device determines an available storage in the second storage medium for the data. Then, the external device generates a list to suggest content for deletion within the second storage medium to accommodate the data.Type: ApplicationFiled: May 31, 2014Publication date: September 18, 2014Applicant: Core Wireless Licensing, S.a.r.l.Inventors: Craig PUGSLEY, Jesmond Allen
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Patent number: 8838903Abstract: A hierarchical data-storage system has a volatile storage medium, a first non-volatile storage medium, and a controller including a ranking engine tracking data writes to each of the memory mediums. Each medium is associated with a pre-set capacity threshold, and the controller, upon the volatile medium reaching its pre-set threshold, identifies one or more blocks of data as least-frequently written to the volatile medium, copies the data in those blocks to the non-volatile medium, and marks those blocks as available for new data writes, and the controller, upon the non-volatile medium reaching its pre-set threshold, identifies one or more blocks of data as least-frequently written to the non-volatile medium, and marks those blocks as available for new data writes from the volatile medium.Type: GrantFiled: February 4, 2010Date of Patent: September 16, 2014Assignee: Dataram, Inc.Inventor: Jason Caulkins
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Publication number: 20140258654Abstract: For the purpose of suppressing decrease of a deduplication rate in a storage system, a storage system according to the present invention includes: a data buffer; a dividing unit configured to generate divided data by dividing data inputted into the data buffer; and a storage processing unit configured to store the divided data into a storage device while eliminating duplicate storage. The dividing unit is configured to generate the divided data by dividing the data inputted into the data buffer by a preset division standard based on the content of the data and also divide, by the division standard, connected data that residual data being left without being divided by the division standard and continuing data continuing to the residual data and being inputted in the data buffer are connected.Type: ApplicationFiled: March 6, 2014Publication date: September 11, 2014Applicant: NEC CorporationInventor: Kenji Mori
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Publication number: 20140258656Abstract: Methods, program products, and systems for lock-free object recycling are described. In some implementations, a system can provide a type-neutral wrapper for a first data object. Upon receiving an indicator that the first data object is no longer used, the system can store the first data object and the type-neutral wrapper in a lock-free data structure. Upon receiving a request to create a second data object, the system can fetch the type-neutral wrapper and the first data object from the lock-free data structure without using a lock. The system can then return the first data object as a response to the request.Type: ApplicationFiled: May 23, 2014Publication date: September 11, 2014Applicant: Apple Inc.Inventor: Wei-De Ju
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Publication number: 20140258769Abstract: An apparatus includes a non-volatile memory and a controller. The non-volatile memory includes a plurality of R-blocks. The controller is coupled to the non-volatile memory. The controller is configured to (i) write data using the R-blocks as a unit of allocation and (ii) perform recycling operations selectively on either an entire one of the R-blocks or a portion less than all of one of the R-blocks.Type: ApplicationFiled: March 7, 2013Publication date: September 11, 2014Applicant: LSI CORPORATIONInventors: Leonid Baryudin, Alex G. Tang, Earl T. Cohen
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Publication number: 20140258650Abstract: A system for managing storage of data units includes a data storage system configured to store multiple data blocks, at least some of the data blocks containing multiple data units, with at least a group of the data blocks being stored contiguously, thereby supporting a first read operation that retrieves data units from at least two adjacent data blocks in the group. The system is configured to perform two or more operations with respect to data units. The operations include: a second read operation, different from the first read operation, that retrieves a data unit to be read based at least in part on an address of a data block containing the data unit to be read, and a delete operation that replaces a first data block containing a data unit to be deleted with a second data block that does not contain the deleted data unit.Type: ApplicationFiled: March 6, 2013Publication date: September 11, 2014Inventors: Ephraim Meriwether Vishniac, Stephen J. Schmidt
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Publication number: 20140258651Abstract: A system for managing storage of data units includes a data storage system configured to store multiple data blocks, at least some of the data blocks containing multiple data units, and configured to store, for at least some of the data blocks, corresponding historical information about prior removal of one or more data units from that data block, the removal affecting at least some addresses of data units in that data block. The system is configured to perform at least one operation that accesses at least a first data unit stored in a first data block according to address information interpreted based on any stored historical information corresponding to the first data block.Type: ApplicationFiled: March 6, 2013Publication date: September 11, 2014Applicant: Ab Initio Technology LLCInventors: Ephraim Meriwether Vishniac, Stephen J. Schmidt
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Publication number: 20140258652Abstract: A system for managing storage of data units includes a data storage system configured to store multiple data blocks, at least some of the data blocks containing multiple data units, with at least a group of the data blocks being stored contiguously, thereby supporting a first read operation that retrieves data units from at least two adjacent data blocks in the group. The system is configured to perform one or more operations with respect to data units, the operations including a delete operation that replaces a first data block containing a data unit to be deleted with a second data block that does not contain the deleted data unit, with the second data block having the same size as the first data block.Type: ApplicationFiled: March 6, 2013Publication date: September 11, 2014Applicant: Ab Initio Technology LLCInventors: Ephraim Meriwether Vishniac, Stephen J. Schmidt
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Publication number: 20140258655Abstract: Disclosed are a method for data de-duplication and an apparatus for the same. The method may comprise obtaining access property of data based on input request or output request for the data, determining de-duplication unit of the data based on the access property, and performing de-duplication on the data based on the de-duplication unit. Thus, data de-duplication rate may be determined adaptively based on input/output characteristics of data. Also, data de-duplication may be performed based on the determined data de-duplication rate so as to provide low input/output latency.Type: ApplicationFiled: March 7, 2014Publication date: September 11, 2014Applicant: POSTECH ACADEMY - INDUSTRY FOUNDATIONInventors: Chan Ik Park, Se Jin Park
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Publication number: 20140258653Abstract: Data stored within symmetric and asymmetric memory components of main memory is integrated by identifying a first data as having access characteristics suitable for storing in an asymmetric memory component. The first data is included among a collection of data to be written to the asymmetric memory component. An amount of data is identified within the collection of data to be written to the asymmetric memory component. The amount of data is compared within the collection of data to a volume threshold to determine whether a block write to the asymmetric memory component is justified by the amount of data. If justified, the collection of data is loaded to the asymmetric memory component.Type: ApplicationFiled: October 7, 2013Publication date: September 11, 2014Applicant: Virident Systems Inc.Inventors: Vijay Karamcheti, Kenneth A. Okin, Kumar Ganapathy, Ashish Singhai, Rajesh Parekh
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Patent number: 8832393Abstract: In described embodiments, a multiple first-in, first-out buffer pointers (multi-FIFO pointers) alignment system includes synchronization circuitry to align multiple FIFO buffer operations. A FIFO read clock stoppage signal is generated by master logic that stops the read clock shared by all the transmit channels and then re-starts the read clock to align them. The FIFO read clock stoppage signal is applied to the read clock of all FIFOs which need to be aligned and, when rate change is needed, the FIFO read clock stoppage signal suspends the read clock, causing local write and read pointers to be reset. After the FIFO read clock stoppage signal is de-asserted, the read clock starts to all FIFOs concurrently, thereby aligning the channels.Type: GrantFiled: April 18, 2012Date of Patent: September 9, 2014Assignee: LSI CorporationInventors: Jung Ho Cho, Vladimir Sindalovsky, Lane A. Smith
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Patent number: 8831409Abstract: Storage management technology, in which a system determines a first amount of storage space on a downloader device of a user that is available for download of new content made available on channels subscribed to by the user. The system also determines a second amount of storage space needed to download new content that has been made available on channels subscribed to by the user. The system further compares the second amount of storage space to the first amount of storage space and determines whether the second amount of storage space exceeds the first amount of storage space. Based on a determination that the second amount of storage space exceeds the first amount of storage space, the system controls downloading of the new content to the downloader device and deletion of previously-stored content on the downloader device based on a content allocation policy.Type: GrantFiled: June 7, 2010Date of Patent: September 9, 2014Assignee: PurpleComm Inc.Inventors: Jack H. Chang, William H. Sheu, Sherman Tuan
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Patent number: 8832381Abstract: A processor is provided. The processor including a cache, the cache having a plurality of entries, each of the plurality of entries having a tag array and a data array, and a remapper configured to create at least one identifier, each identifier being unique to a process of the processor, and to assign a respective identifier to the tag array for the entries related to a respective process, the remapper further configured to determine a replacement value for the entries related to each identifier.Type: GrantFiled: February 21, 2011Date of Patent: September 9, 2014Assignee: Advanced Micro Devices, Inc.Inventor: Douglas B. Hunt
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Patent number: 8825969Abstract: A hardware and/or software facility to enable emulated storage devices to share data stored on physical storage resources of a storage system. The facility may be implemented on a virtual tape library (VTL) system configured to back up data sets that have a high level of redundancy on multiple virtual tapes. The facility organizes all or a portion of the physical storage resources according to a common store data layout. By enabling emulated storage devices to share data stored on physical storage resources, the facility enables deduplication across the emulated storage devices irrespective of the emulated storage device to which the data is or was originally written, thereby eliminating duplicate data on the physical storage resources and improving the storage consumption of the emulated storage devices on the physical storage resources.Type: GrantFiled: November 29, 2010Date of Patent: September 2, 2014Assignee: NetApp, Inc.Inventors: Vivek Gupta, Ameet Pyati, Satish Singhal, Pawan Saxena
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Patent number: 8825951Abstract: A mechanism is provided for managing a high speed memory. An index entry indicates a storage unit in the high speed memory. A corresponding non-free index is set for a different type of low speed memory. The indicated storage unit in the high speed memory is assigned to a corresponding low speed memory by including the index entry in the non-free index. The storage unit in the high speed memory is recovered by demoting the index entry from the non-free index. The mechanism acquires a margin performance loss corresponding to a respective non-free index in response to receipt of a demotion request. The margin performance loss represents a change in a processor read operation time caused by performing a demotion operation in a corresponding non-free index. The mechanism compares the margin performance losses of the respective non-free indexes and selecting a non-free index whose margin performance loss satisfies a demotion condition as a demotion index.Type: GrantFiled: March 27, 2012Date of Patent: September 2, 2014Assignee: International Business Machines CorporationInventors: Xue D. Gao, Chao Guang Li, Yang Liu, Yi Yang
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Publication number: 20140237199Abstract: Method and apparatus for handling page protection faults in combination particularly with the dynamic conversion of binary code executable by a one computing platform into binary code executed instead by another computing platform. In one exemplary aspect, a page protection fault handling unit is used to detect memory accesses, to check page protection information relevant to the detected access by examining the contents of a page descriptor store, and to selectively allow the access or pass on page protection fault information in accordance with the page protection information.Type: ApplicationFiled: April 25, 2014Publication date: August 21, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Simon Murray, Geraint M. North
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Patent number: 8812767Abstract: A method of controlling a memory including a first storage area and a second storage area. The method includes determining, in response to a request for writing a write data string, whether the write data string changes a logical value stored in the memory from a first logical value to a second logical value, writing, to the first storage area, a logical value that is located in a position of the write data string and does not change an existing logical value of the memory from the first logical value to the second logical value, and writing the second logical value that is located in a position of the write data string and changes an existing logical value of the memory from the first logical value to the second logical value to the second storage area which is different from the first storage area.Type: GrantFiled: January 18, 2012Date of Patent: August 19, 2014Assignee: Fujitsu Semiconductor LimitedInventor: Kazuya Sawa
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Patent number: 8812791Abstract: A system and method is provided wherein, in one aspect, a currently-requested item of information is stored in a cache based on whether it has been previously requested and, if so, the time of the previous request. If the item has not been previously requested, it may not be stored in the cache. If the subject item has been previously requested, it may or may not be cached based on a comparison of durations, namely (1) the duration of time between the current request and the previous request for the subject item and (2) for each other item in the cache, the duration of time between the current request and the previous request for the other item. If the duration associated with the subject item is less than the duration of another item in the cache, the subject item may be stored in the cache.Type: GrantFiled: October 8, 2013Date of Patent: August 19, 2014Assignee: Google Inc.Inventors: Timo Burkard, David Presotto
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Patent number: 8812804Abstract: A secure demand paging (SDP) system includes a dynamic random access memory (DRAM), a microprocessor having a secure internal memory and coupled to said DRAM, and a non-volatile memory storing a representation of operations accessible by the microprocessor. The stored representation of operations includes a coded physical representation of operations to configure an SDP space in the DRAM, to organize the SDP space into virtual machine contexts, to organize at least one of the virtual machine contexts into block book keeping blocks and book keeping spaces in the block book keeping blocks, and to execute a secure demand paging process between said secure internal memory and said DRAM.Type: GrantFiled: January 6, 2012Date of Patent: August 19, 2014Assignee: Texas Instruments IncorporatedInventors: Steven C. Goss, Gregory R. Conti, Narendar Shankar, Mehdi-Laurent Akkar, Aymeric Vial
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Patent number: 8812773Abstract: In a method of merging blocks in a semiconductor memory device according to example embodiments, a plurality of data are written into one or more first blocks using a first program method. One or more merge target blocks that are required to be merged are selected among the one or more first blocks. A merge-performing block for a block merge operation is selected among the one or more first blocks and one or more second blocks. A plurality of merge target data are written from the merge target blocks into the merge-performing block using a second program method that is different from the first program method.Type: GrantFiled: May 24, 2011Date of Patent: August 19, 2014Assignee: SAMSUNG Electronics Co., Ltd.Inventors: Min-Seok Kim, Ki-Tae Park
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Publication number: 20140229690Abstract: A method and circuit arrangement utilize secure clear instructions defined in an instruction set architecture (ISA) for a processing unit to clear, overwrite or otherwise restrict unauthorized access to the internal architected state of the processing unit in association with context switch operations. The secure clear instructions are executable by a hypervisor, operating system, or other supervisory program code in connection with a context switch operation, and the processing unit includes security logic that is responsive to such instructions to restrict access by an operating system or process associated with an incoming context to architected state information associated with an operating system or process associated with an outgoing context.Type: ApplicationFiled: March 12, 2013Publication date: August 14, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: INTERNATIONAL BUSINESS MACHINES CORPORATION
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Publication number: 20140229691Abstract: A data control system comprises a communication interface, a processing system, and a storage system. The communication interface is configured to receive a request to retrieve data from a primary storage volume that includes a secondary storage volume. The storage system is configured to store the primary storage volume that includes the secondary storage volume. The processing system is configured to identify changed segments of a plurality of segments in the primary storage volume and identify allocated segments of the changed segments. The communication interface is further configured to transfer the allocated segments in response to the request.Type: ApplicationFiled: April 19, 2014Publication date: August 14, 2014Applicant: Quantum CorporationInventors: Gregory L. Wade, J. Mitchell Haile
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Publication number: 20140229689Abstract: A system and method for ballooning with assigned devices includes inflating a memory balloon, determining whether a first memory page is locked based on information associated with the first memory page, when the first memory page is locked unlocking the first memory page and removing first memory addresses associated with the first memory page from management by an input/output memory management unit (IOMMU), and reallocating the first memory page. The first memory page is associated with a first assigned device.Type: ApplicationFiled: February 14, 2013Publication date: August 14, 2014Applicant: Red Hat Israel, Ltd.Inventors: Paolo Bonzini, Michael Tsirkin
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Patent number: 8806166Abstract: Evaluating memory allocation in a multi-node computer including calculating, in dependence upon a normalized measure of page frame demand, a weighted coefficient of memory affinity, the weighted coefficient representing desirability of allocating memory from the node, and allocating memory may include allocating memory in dependence upon the weighted coefficient of memory affinity.Type: GrantFiled: September 29, 2005Date of Patent: August 12, 2014Assignee: International Business Machines CorporationInventors: Kenneth R. Allen, Rebecca N. B. Legler, Kenneth C. Vossen
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Publication number: 20140223117Abstract: A memory device may be equipped with quick erase capability to secure the contents of the memory device. The quick erase capability may effectively permanently disable access to data stored in the memory device instantaneously upon a command being issued, making all previous data written to the memory device unreadable. The quick erase capability may allow use of the memory device for new write operations and for reading the newly written data immediately once the erase command is received and executed. The quick erase capability may begin a physical erase process of data not newly written without altering other aspects of the quick erase. Aspects may be accomplished with one or more bits per row in a memory device.Type: ApplicationFiled: March 11, 2013Publication date: August 7, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michele M. Franceschini, Hillery C. Hunter, Ashish Jagmohan, Charles A. Kilmer, Kyu-hyoun Kim, Luis A. Lastras-Montano, Warren E. Maule
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Patent number: 8793428Abstract: A system for identifying an exiting process and removing traces and shadow page table pages corresponding to the process' page table pages. An accessed minimum virtual address is maintained corresponding to an address space. In one embodiment, whenever a page table entry corresponding to the accessed minimum virtual address changes from present to not present, the process is determined to be exiting and removal of corresponding trace and shadow page table pages is begun. In a second embodiment, consecutive present to not-present PTE transitions are tracked for guest page tables on a per address space basis. When at least two guest page tables each has at least four consecutive present to not-present PTE transitions, a next present to not-present PTE transition event in the address space leads to the corresponding guest page table trace being dropped and the shadow page table page being removed.Type: GrantFiled: January 22, 2013Date of Patent: July 29, 2014Assignee: VMware, Inc.Inventors: Qasim Ali, Raviprasad Mummidi, Kiran Tati
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Patent number: 8793555Abstract: A method of controlling a nonvolatile semiconductor memory includes checking, at a first interval period, an error count of data stored in a first group, the first group including a plurality of blocks/units, and when a first block/unit in the first group satisfies a first condition, assigning the first block/unit to a second group. The method includes checking, at a second interval period, an error count of data stored in the second group, the second interval period being shorter than the first interval period, and when a second block/unit in the second group satisfies a second condition, moving data stored in the second block/unit to an erased block/unit in which stored data is erased among the plurality of blocks/units.Type: GrantFiled: October 9, 2013Date of Patent: July 29, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Toshikatsu Hida, Shinichi Kanno, Hirokuni Yano, Kazuya Kitsunai, Shigehiro Asano, Junji Yano
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Patent number: 8793427Abstract: Remote memory can be used for a number idle pages located on a virtual machine. A number of idle pages can be sent to the remote memory according to a placement policy, where the placement policy can include a number of weighting factors. A hypervisor on a computing device can record a local size and a remote page fault frequency of the number of virtual machines. The hypervisor can scan local memory to determine the number of idle pages and a number of idle virtual machines. The number of idle pages, including a page map and a remote address destination for each idle page, can be sent to the remote memory by the hypervisor. The number of virtual machines can be analyzed to determine a per-virtual machine local memory allocation.Type: GrantFiled: February 10, 2011Date of Patent: July 29, 2014Assignee: Hewlett-Packard Development Company, L.P.Inventors: Kevin T. Lim, Jichuan Chang, Jose Renato G. Santos, Yoshio Turner, Parthasarathy Ranganathan
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Publication number: 20140207997Abstract: Techniques are disclosed relating to arranging data on storage media. In one embodiment, a computer system is configured to access a storage array that includes a plurality of storage blocks. The computer system executes a first set of processes and a second set of processes, where the first set of processes operates on selected ones of the plurality of storage blocks to increase a likelihood that the selected storage blocks are operated on by the second set of processes. In some embodiments, the second set of processes determines whether to operate on a storage block based on an amount of invalid data within the storage block. In such an embodiment, the first set of processes increases a likelihood that the storage block is operated on by increasing the amount of invalid data within the storage block.Type: ApplicationFiled: January 21, 2013Publication date: July 24, 2014Applicant: FUSION-IO, INC.Inventors: James Peterson, Ned Plasson
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Publication number: 20140208042Abstract: In one embodiment, the present invention includes a memory management unit (MMU) having entries to store virtual address to physical address translations, where each entry includes a location indicator to indicate whether a memory location for the corresponding entry is present in a local or remote memory. In this way, a common virtual memory space can be shared between the two memories, which may be separated by one or more non-coherent links. Other embodiments are described and claimed.Type: ApplicationFiled: March 21, 2014Publication date: July 24, 2014Inventors: Gautham N. Chinya, Hong Wang, Deepak A. Mathaikutty, Jamison D. Collins, Ethan Schuchman, James P. Held, Ajay V. Bhatt, Prashant Sethi, Stephen F. Whalley
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Publication number: 20140208045Abstract: A logical volume manager (LVM) may manage a plurality of logical volumes and a plurality of drives in a logical data storage using metadata stored on the plurality of drives. The LVM may operate in one of two modes. In the first mode, the LVM may deleted uncommitted metadata on a drive and may use committed metadata on the drive when accessing a logical volume. In a second mode, the LVM may use committed metadata on the drive when accessing the logical volume and may refrain from deleting the uncommitted metadata.Type: ApplicationFiled: January 22, 2013Publication date: July 24, 2014Applicant: RED HAT ISRAEL, LTD.Inventors: Eduardo Warszawski, Ayal Baron
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Publication number: 20140208046Abstract: Described embodiments detect an impending out-of-space (OOS) condition of a media. On startup, a media controller determines whether an impending OOS indicator is set from a previous startup. If the impending OOS indicator is not set, it is determined whether a free pool size has reached a threshold. The free pool is blocks of the solid-state media available to be written with data. If the free pool size has not reached the first threshold, while the startup time is less than a maximum startup time, garbage collection is performed on the solid-state media to accumulate blocks to the free pool. If the startup time reaches the maximum startup time and the free pool size has not reached the threshold, the impending OOS indicator is set and the media is operated in impending OOS mode. Otherwise, if the free pool size reaches the threshold, the media is operated in normal mode.Type: ApplicationFiled: January 23, 2013Publication date: July 24, 2014Applicant: LSI CORPORATIONInventors: Leonid Baryudin, Earl T. Cohen
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Publication number: 20140201479Abstract: An integrated circuit device comprising at least one memory interface module arranged to be operably coupled between at least one data storage device and a plurality of master devices within a data processing system. The at least one memory interface module comprises a plurality of buffers and at least one data access control module. The at least one data access control module being arranged to fetch data from the at least one data storage device in response to a received memory access request comprising a master device identifier, select at least one buffer based at least partly on the master device identifier of the received access request, and load the fetched data into the selected at least one buffer.Type: ApplicationFiled: September 1, 2011Publication date: July 17, 2014Applicant: Freescale Semiconductor, Inc.Inventors: Manfred Thanner, Nancy Amedeo, Stephan Mueller, Anthony Reipold
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Publication number: 20140201478Abstract: A mechanism is provided in a data processing system for de-duplication aware secure delete. Responsive to receiving a secure delete request for a file, the mechanism identifies a list of file blocks to be securely deleted from a physical disk device. Responsive to determining at least one virtual block of another file refers to a given disk block corresponding to a file block in the list, the mechanism copies the given disk block to generate a copied disk block in the physical disk device and updates a pointer of the at least one virtual block to refer to the copied disk block. The mechanism writes a secure delete pattern for each file block in the list of file blocks to a disk block in the physical disk device without performing de-duplication processing.Type: ApplicationFiled: January 14, 2013Publication date: July 17, 2014Applicant: International Business Machines CorporationInventors: Kalyan C. Gunda, Sandeep R. Patil, Subhojit Roy, Riyazahamad M. Shiraguppi
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Publication number: 20140195749Abstract: A system and method for performing coarse-grained deduplication of volume regions. A storage controller detects that a first region of a first volume is identical to a second region of a second volume, wherein the first volume points to a first medium and the second volume points to a second medium. In response to detecting the identical regions, the storage controller stores an indication that the first range of the first medium underlies the second range of the second medium. Also in response to detecting the identical regions, the mappings associated with the second range of the second medium are invalidated.Type: ApplicationFiled: October 4, 2013Publication date: July 10, 2014Applicant: PURE Storage, INC.Inventors: John Colgrove, Ethan Miller, John Hayes, Cary Sandvig, Christopher Golden, Jianting Cao
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Publication number: 20140195750Abstract: Aspects of the subject matter described herein relate to a buffer pool for a database system. In aspects, secondary memory such as solid state storage is used to extend the buffer pool of a database system. Thresholds such as hot, warm, and cold for classifying pages based on access history of the pages may be determined via a sampling algorithm. When a database system needs to free space in a buffer pool in main memory, a page may be evicted to the buffer pool in secondary memory or other storage based on how the page is classified and conditions of the secondary memory or other storage.Type: ApplicationFiled: March 13, 2014Publication date: July 10, 2014Applicant: Microsoft CorporationInventors: Chengliang Zhang, Sadashivan Krishnamurthy, Georgiy I. Reynya, Alexandre Verbitski, Pedro Celis, Dexter Paul Bradshaw
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Publication number: 20140195748Abstract: Mechanisms are provided for efficient replica cleanup during resynchronization. According to various embodiments, a plurality of deleted data segment ranges on a first storage node may be identified. The first storage node may be configured to store a plurality of data segments. Each of the plurality of data segments may have associated therewith a respective identifier. Each of the data segment ranges may designate one or more data segments that have been deleted from the first storage node. The plurality of deleted data segment ranges may be transmitted to a second storage node configured to mirror the plurality of data segments stored on the first storage node. The plurality of deleted data segment ranges may be capable of being used to identify one or more data segments to delete from the second storage node.Type: ApplicationFiled: January 24, 2013Publication date: July 10, 2014Applicant: Dell Products L.P.Inventors: Murali Bashyam, Sreekanth Garigala
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Patent number: 8775751Abstract: Reclamation of storage space in presence of copy-on-write snapshot. In one embodiment, a reclamation command is generated. In response to generating the reclamation command, first data held within one storage device is copied to another storage device via a communication link. One or more first physical memory regions of the one storage device, which stores the first data, is allocated to a first region of a data volume. The other storage device is configured to store a copy-on-write snapshot of the data volume. In response to copying the first data, de-allocate the one or more first physical memory regions from the first data volume region.Type: GrantFiled: December 7, 2010Date of Patent: July 8, 2014Assignee: Symantec CorporationInventors: Niranjan Pendharkar, Shailesh Vaman Marathe
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Patent number: 8775752Abstract: A virtual memory management apparatus of an embodiment is embedded in a computing machine 80 and is provided with an application program 21, an operating system 22, a volatile memory 11, and a nonvolatile memory 12. The volatile memory 11 is provided with a plurality of clean pages. The nonvolatile memory 12 is provided with a plurality of dirty pages and a page table memory unit 51. The operating system 22 is provided with a virtual memory management unit 23 which includes a page transfer unit 25.Type: GrantFiled: February 13, 2012Date of Patent: July 8, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hideki Yoshida, Tatsunori Kanai, Masaya Tarui, Yutaka Yamada
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Patent number: 8775756Abstract: A virtual tape emulator (VTE) that performs data integrity read back verification at host sync points. The VTE first flushes data that it may have buffered to a backend storage subsystem such as a disk array. The VTE then reads all data that was written to the backend storage array between a prior sync point and the current sync point. During this feedback verification, integrity checks can be performed. An error detected during read back verification is returned to the host operation that triggered the sync operation.Type: GrantFiled: March 29, 2012Date of Patent: July 8, 2014Assignee: EMC CorporationInventors: Larry W. McCloskey, Bruce Offhaus, Eric M. Vaughn
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Publication number: 20140189211Abstract: In the present disclosure, a persistent storage device includes both persistent storage, which includes a set of persistent storage blocks, and a storage controller. The persistent storage device stores and retrieves data in response to commands received from an external host device. The persistent storage device stores a logical block address to physical address mapping. The persistent storage device also, in response to a remapping command, stores an updated logical block address to physical block address mapping.Type: ApplicationFiled: March 14, 2013Publication date: July 3, 2014Inventors: Johann George, Aaron Olbrich
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Patent number: 8769221Abstract: A method, system, and computer program product for preemptive page eviction in a computer system are provided. The method includes identifying a region in an input file for preemptive page eviction, where the identified region is infrequently accessed relative to other regions of the input file. The method also includes generating an output file from the input file, where the identified region is flagged as a page for preemptive page eviction in the output file. The method further includes loading the output file to a memory hierarchy including a faster level of memory and a slower level of memory, wherein the flagged page is preemptively written to the slower level of memory.Type: GrantFiled: January 4, 2008Date of Patent: July 1, 2014Assignee: International Business Machines CorporationInventors: Eli M. Dow, Marie R. Laser, Charulatha Dhuvur, Jessie Yu
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Patent number: 8769187Abstract: A mobile device includes a system-on-chip (SOC) that includes a mobile device control module, a solid state disk (SSD) control module, and a random access memory (RAM) control module. The mobile device control module executes application programs for the mobile device. The solid-state disk (SSD) control module controls SSD operations. The RAM control module communicates with the mobile device control module and the SSD control module and stores both SSD-related data and mobile device-related data in a single RAM.Type: GrantFiled: April 2, 2013Date of Patent: July 1, 2014Assignee: Marvell World Trade Ltd.Inventor: Sehat Sutardja