Entry Replacement Strategy Patents (Class 711/159)
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Patent number: 8660133Abstract: In general, in one aspect, included are descriptions of providing a single network interface from physical network interfaces that provides a number of receive queues equal to the sum of the number of receive queues provided by each of the physical network interfaces.Type: GrantFiled: January 3, 2012Date of Patent: February 25, 2014Assignee: Intel CorporationInventor: Patrick L. Connor
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Patent number: 8661189Abstract: Systems and methods for trimming LBAs are provided. The LBAs can be trimmed from a file and from an NVM interface that maintains a logical-to-physical translation of the file's LBAs and controls management of the file's contents stored on non-volatile memory (“NVM”). The file can be any suitable file that has any number of associated LBAs. In addition, the file can be linked to one or more data chunks stored in the NVM, each data chunk associated with LBAs in the file. When a data chunk is retrieved or read from the NVM, that chunk no longer needs to be maintained in the NVM. Accordingly, after the data chunk is retrieved from the NVM and provided to an appropriate destination, the LBAs associated with the retrieved data chunk can be trimmed.Type: GrantFiled: August 31, 2010Date of Patent: February 25, 2014Assignee: Apple Inc.Inventors: Daniel J. Post, Eric Tamura, Matthew Byom, Neil Crane, Kenneth Herman, Francois Barbou-des-Place
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Publication number: 20140052946Abstract: Techniques for opportunistic data storage are described. In one embodiment, for example, an apparatus may comprise a data storage device and a storage management module, and the storage management module may be operative to receive a request to store a set of data in the data storage device, the request indicating that the set of data is to be stored with opportunistic retention, the storage management module to select, based on allocation information, storage locations of the data storage device for opportunistic storage of the set of data and write the set of data to the selected storage locations. Other embodiments are described and claimed.Type: ApplicationFiled: August 19, 2013Publication date: February 20, 2014Inventor: Jeffrey S. Kimmel
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Publication number: 20140052945Abstract: A method, system and computer program product for optimizing storage system behavior in a cloud computing environment. An Input/Output (I/O) operation data is appended with a tag, where the tag indicates a class of data for the I/O operation data. Upon the storage controller reviewing the tag appended to the I/O operation data, the storage controller performs a table look-up for the storage policy associated with the determined class of data. The storage controller applies a map to determine a storage location for the I/O operation data in a drive device, where the map represents a logical volume which indicates a range of block data that is to be excluded for being stored on the drive device and a range of block data that is to be considered for being stored on the drive device. In this manner, granularity of storage policies is provided in a cloud computing environment.Type: ApplicationFiled: August 14, 2012Publication date: February 20, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Rohith K. Ashok, Darryl E. Gardner, Ivan M. Heninger, Douglas A. Larson, Gerald F. McBrearty, Aaron J. Quirk, Matthew J. Sheard
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Publication number: 20140052907Abstract: An apparatus and associated methodology contemplate a data storage system having a removable storage device operably transferring data between the data storage system and another device via execution of a plurality of input/output (I/O) commands. A commonality factoring (CF) module executing computer instructions stored in memory assigns a CF tag to a data pattern in the transferred data. A deduplication module executing computer instructions stored in memory determines if the data pattern corresponding to the CF tag is previously stored in the removable storage device.Type: ApplicationFiled: August 17, 2012Publication date: February 20, 2014Applicant: Spectra Logic CorporationInventor: Matthew Thomas Starr
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Patent number: 8656121Abstract: Fine-grained detection of data modification of original data is provided by associating separate guard bits with granules of memory storing original data from which translated data has been obtained. The guard bits indicating whether the original data stored in the associated granule is protected for data coherency. The guard bits are set and cleared by special-purpose instructions. Responsive to attempting access to translated data obtained from the original data, the guard bit(s) associated with the original data is checked to determine whether the guard bit(s) fail to indicate coherency of the original data, and if so, discarding of the translated data is initiated to facilitate maintaining data coherency between the original data and the translated data.Type: GrantFiled: May 17, 2011Date of Patent: February 18, 2014Assignee: International Business Machines CorporationInventors: Guy L. Guthrie, Geraint North, William J. Starke, Derek E. Williams
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Patent number: 8650281Abstract: Various embodiments of a system and method for handling network partitions in a cluster of nodes are disclosed. The system and method may use a set of arbitration servers that are ordered in a particular order. Client nodes in different partitions may send requests to the arbitration servers to attempt to win control of them. The client node that wins a majority of the arbitration servers may remain in the cluster, and the client nodes in the other partitions may exit the cluster. The first arbitration server may award control to whichever client node whose request for control is received first. The remaining arbitration servers may be configured to give preference to the winner of one or more of the previous arbitration servers to attempt to ensure that one of the client nodes wins a majority.Type: GrantFiled: February 1, 2012Date of Patent: February 11, 2014Assignee: Symantec CorporationInventors: Abhijit Toley, Viraj Kamat
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Publication number: 20140040572Abstract: Storage access requests, such as write requests, are received from a virtual machine. A storage request processing module updates one of multiple virtual disks as directed by each of the storage access requests, and a replication management module stores information associated with each storage access request in one of multiple logs. The logs can be transferred to a recovery device at various intervals and/or in response to various events, which results in switching logs so that the replication management module stores the information associated with each storage access request in a new log and the previous (old) log is transferred to the recovery device. During this switching, request ordering for write order dependent requests is maintained at least in part by blocking processing of the information associated with each storage access request.Type: ApplicationFiled: August 1, 2012Publication date: February 6, 2014Applicant: MICROSOFT CORPORATIONInventors: Sriravi Kotagiri, Rahul Shrikant Newaskar
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Patent number: 8645644Abstract: A method is provided for fine-grained detection of data modification of original data by associating separate guard bits with granules of memory storing original data from which translated data has been obtained. The guard bits indicating whether the original data stored in the associated granule is protected for data coherency. The guard bits are set and cleared by special-purpose instructions. Responsive to attempting access to translated data obtained from the original data, the guard bit(s) associated with the original data is checked to determine whether the guard bit(s) fail to indicate coherency of the original data, and if so, discarding of the translated data is initiated to facilitate maintaining data coherency between the original data and the translated data.Type: GrantFiled: April 20, 2012Date of Patent: February 4, 2014Assignee: International Business Machines CorporationInventors: Guy L. Guthrie, Geraint North, William J. Starke, Derek E. Williams
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Patent number: 8645404Abstract: A split data word including a portion of each of two word-aligned data words stored at two word-aligned address boundaries within a memory is read from a displaced-read memory address relative to the word-aligned address boundaries within the memory. The portions of each of the two word-aligned data words within the split data word are compared with corresponding portions of a word-aligned search pattern. A determination is made that a potential complete match for the word-aligned search pattern exists within at least one of the two word-aligned data words based upon an identified match of at least one of the portions of the two word-aligned data words within the split data word with a corresponding at least one portion of the word-aligned search pattern.Type: GrantFiled: October 21, 2011Date of Patent: February 4, 2014Assignee: International Business Machines CorporationInventors: K. S. Sadananda Aithal, Ajay K. Sami
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Patent number: 8645633Abstract: Fine-grained detection of data modification of original data is provided by associating separate guard bits with granules of memory storing the original data from which translated data has been obtained. The guard bits facilitate indicating whether the original data stored in the associated granule is indicated as protected. The guard bits are set and cleared by special-purpose instructions. Responsive to initiating a data store operation to modify the original data, the associated guard bit(s) are checked to determine whether the original data is indicated as protected. Responsive to the checking indicating that a guard bit is set for the associated original data, the data store operation to modify the original data is faulted and the translated data is discarded, thereby facilitating data coherency between the original data and the translated data.Type: GrantFiled: May 17, 2011Date of Patent: February 4, 2014Assignee: International Business Machines CorporationInventors: Guy L. Guthrie, Geraint North, William J. Starke, Derek E. Williams
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Publication number: 20140032860Abstract: First data to be written which is output from a function module (2) is supplied to a built-in memory (3) and a first buffer memory (11), and second data to be written which is output from the function module (2) is supplied to the built-in memory (3) and a second buffer memory (12). The first and second FIFO memories (13, 14) select and store data items having a predetermined number of outputs from a plurality of first and second output data items which are sequentially output from the first and second buffer memories (11, 12), and do not select other data items. A comparator (15) compares the data items having the predetermined number of outputs which are selected and are output by the first and second FIFO memories (13, 14) with each other.Type: ApplicationFiled: April 21, 2011Publication date: January 30, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Hiromichi Yamada, Nobuyasu Kanekawa, Teruaki Sakata, Kesami Hagiwara, Yuichi Ishiguro
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Publication number: 20140019696Abstract: Methods and apparatus for point-in-time volumes are provided. A relationship is enabled between a source volume and point-in-time volume. Copying a data chunk to the point-in-time volume before a write operation modifies the data chunk on the source volume dynamically creates the point-in-time volume. The point-in-time volume can be accessed in read/write mode as a general purpose data storage volume. Other embodiments comprising additional features, such as a forced migration process, are also provided.Type: ApplicationFiled: March 14, 2013Publication date: January 16, 2014Applicant: DATACORE SOFTWARE CORPORATIONInventor: David A. Linde
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Publication number: 20140019695Abstract: The present invention is related to processing data sets, and more specifically to recovering problematic portions of a data set.Type: ApplicationFiled: July 12, 2012Publication date: January 16, 2014Inventors: Jefferson Singleton, Shaohua Yang
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Patent number: 8627036Abstract: Memory management techniques that permit an executing process to store content in memory and later retrieve that content from the memory, but that also permit a memory manager to discard that content to address memory pressure. A process executing on a computing device may notify a memory manager of the computing device that first memory space allocated to the process contains first content that is available for discard. If the memory manager detects the computing device is experiencing memory pressure, the memory manager may address the memory pressure by selecting memory space available for discard and discarding the content of the memory space. Before a process reuses content made available for discard, the process may notify the memory manager of the intent to reuse and, in response, receive empty memory and an indication that the content was discarded or receive an indication that the content is still available for use.Type: GrantFiled: September 12, 2011Date of Patent: January 7, 2014Assignee: Microsoft CorporationInventors: Steve Pronovost, Maxwell Abernethy, Rudolph Balaz, Ameet Chitre
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Patent number: 8621141Abstract: A method and system for wear leveling in a solid state drive by mapping the logical regions of the solid state drive that hold static content or information into the physical regions of the solid state drive that have erase counts more than an average erase count of all of the physical regions. By doing so, it allows the solid state drive to wear level itself naturally through continued usage. In one embodiment of the invention, the erase count of each physical region is incremented with every erasing operation of each physical region. The physical regions that have a high count of erase count operations are mapped with content of the logical regions with static content so that the possibility of future erase operations of these physical regions is reduced.Type: GrantFiled: April 1, 2010Date of Patent: December 31, 2013Assignee: Intel CorporationsInventors: Eric D. Mudama, David M. Jones, Andrew W. Vogan
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Publication number: 20130346707Abstract: Resource use is recorded with a partitioned reference counter. The sum of all resource counter partitions is equivalent to the total references to a resource. When one resource counter partition reaches zero, it is possible that the resource should be destroyed. To determine if this is the case, all other partitions can be checked for a value of zero. If all the partitions are zero, the resource can be destroyed. Coarse grained partitioning and add/release on all partitions can be employed to avoid extra work associated with a local partition reaching zero. Further, destroying or deleting a resource can be accomplished in a manner that avoids a race condition.Type: ApplicationFiled: June 21, 2012Publication date: December 26, 2013Applicant: MICROSOFT CORPORATIONInventors: Fabricio D. Voznika, Haitao Wang, Jack S. Richins, Jasraj Dange
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Patent number: 8612698Abstract: Methods and apparatus relating to a replacement policy for hot code detection are described. In some embodiments, it may be determined which entry amongst a plurality of entries stored in storage unit is to be replaced next. The entries may correspond to hot code and may store age and execution frequency information corresponding to the hot code. Other embodiments are also described and claimed.Type: GrantFiled: October 31, 2008Date of Patent: December 17, 2013Assignee: Intel CorporationInventors: Pedro Lopez, F. Jesús Sánchez, Josep M. Codina, Enric Gibert, Fernando Latorre, Grigorios Magklis, Pedro Marcuello, Antonio González
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Patent number: 8612699Abstract: Deduplication in a hybrid storage environment includes determining characteristics of a first data set. The first data set is identified as redundant to a second data set and the second data set is stored in a first storage system. The deduplication also includes mapping the characteristics of the first data set to storage preferences, the storage preferences specifying storage system selections for storing data sets based upon attributes of the respective storage systems. The deduplication further includes storing, as a persistent data set, one of the first data set and the second data set in one of the storage systems identified from the mapping.Type: GrantFiled: June 25, 2010Date of Patent: December 17, 2013Assignee: International Business Machines CorporationInventors: Bhushan P. Jain, John G. Musial, Abhinay R. Nagpal, Sandeep R. Patil
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Patent number: 8607008Abstract: A shared resource management system and method are described. In one embodiment a shared resource management system includes a plurality of engines, a shared resource, and a shared resource management unit. In one exemplary implementation the shared resource is a memory and the shared resource management unit is a memory management unit (MMU). The plurality of engines perform processing. The shared resource supports the processing. For example a memory store information and instructions for the engines. The shared resource management unit independently caches and invalidates page table entries on a per engine basis.Type: GrantFiled: November 1, 2006Date of Patent: December 10, 2013Assignee: NVIDIA CorporationInventors: David B. Glasco, Lingfeng Yuan
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Patent number: 8607210Abstract: Example embodiments described herein may comprise a transfer of firmware execution within a non-volatile memory device to one or more replacement instructions at least in part in response to a match between a code fetch address and an address stored in a trap address register.Type: GrantFiled: November 30, 2010Date of Patent: December 10, 2013Assignee: Micron Technology, Inc.Inventors: Massimiliano Mollichelli, Andrea Martinelli, Stefan Schippers
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Patent number: 8606994Abstract: A redundant array of independent disk (RAID) stack executes a first memory access routine and a second memory access routine having different access timing characteristics. The RAID stack determines a number of cache misses for the execution of each of the first and second memory access routines. The RAID stack selects one of the first and second memory access routines based on the number of cache misses for further memory accesses.Type: GrantFiled: September 25, 2012Date of Patent: December 10, 2013Assignee: Red Hat, Inc.Inventor: Douglas Ledford
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Publication number: 20130326141Abstract: A method and host device for packing and dispatching read and write commands are provided. In one embodiment, a host device receives commands from at least one application, wherein the commands include read commands and write commands. The host device stores the commands in the memory. The host device then selects the read commands from the memory and packs them together but separately from the write commands. The same thing is done for the write commands. The host device then sends the packed read commands and the packed write commands to the storage device. In another embodiment, the host device determines when to send the packed commands to the storage device based on at least one parameter.Type: ApplicationFiled: July 11, 2012Publication date: December 5, 2013Inventors: Alon Marcu, Amir Shaharabany
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Patent number: 8601201Abstract: A method and system manages memory in a network of virtual machines, including a copy of a master virtual machine (VM) memory system, the copy accessible to a memory server. The method includes determining whether a memory page requested by a clone VM memory system is fetchable from the memory server, the clone VM memory system hosted in a host memory system; if the memory page is fetchable from the memory server, fetching the memory page from the memory server; determining whether there is sufficient space in the host memory system to load the memory page; if there is insufficient space in the host memory system, evicting a selected memory page from the host memory system; and loading the memory page into the host memory system and the clone VM memory system.Type: GrantFiled: November 9, 2010Date of Patent: December 3, 2013Assignee: Gridcentric Inc.Inventors: Adin Scannell, Timothy Smith, Vivek Lakshmanan, David Scannell, Kannan Vijayan, Jing Su
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Patent number: 8601202Abstract: Methods and systems to wear level a non-volatile memory device across partitions. In an embodiment, a memory device performs background operations to swap host addressable memory partitions with a spare memory partition outside of the host address space. In one embodiment, the background inter-partition wear leveling operations are appended to a user erase operations.Type: GrantFiled: August 26, 2009Date of Patent: December 3, 2013Assignee: Micron Technology, Inc.Inventors: Robert Melcher, Sean Eilert, Gerard Kreifels
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Patent number: 8599982Abstract: An interface system is used for interfacing a synchronous circuit with an asynchronous circuit, wherein the synchronous circuit generates, in response to a clock signal, a first control signal for indicating that a first data signal contains valid data, and wherein the asynchronous circuit generates, according to an asynchronous communication protocol, a second control signal indicating the state of transmission of a second data signal.Type: GrantFiled: December 1, 2011Date of Patent: December 3, 2013Assignee: STMicroelectronics S.r.l.Inventors: Daniele Mangano, Salvatore Pisasale
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Patent number: 8595422Abstract: Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of memory cells; and a data randomizer configured to randomly or pseudo-randomly change original data to be stored in the memory block to changed data. The original data is changed such that a pattern of data as stored in the memory block is different than what it would have been if the original data had been stored in the memory block during a write operation. This configuration can reduce or eliminate data pattern-dependent errors in data digits stored in memory cells.Type: GrantFiled: July 11, 2012Date of Patent: November 26, 2013Assignee: Micron Technology, Inc.Inventors: Paul Ruby, Neal Mielke
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Patent number: 8595745Abstract: A memory swap management method that can preferentially place in a primary storage device a process that has a high possibility of being executed next, thereby shortening the time to start executing the next process. A planned execution sequence of jobs is stored when there are a plurality of jobs waiting to be executed. A process as a swap-out candidate and a process as a swap-in candidate are determined based on the execution sequence and types of processes stored in the primary storage device. According to the determination, the process as the swap-out candidate is swapped out from the primary storage device to a secondary storage device, and the process as the swap-in candidate is swapped in from the secondary storage device into an area of the primary storage device freed as a result of the swap-out.Type: GrantFiled: March 11, 2010Date of Patent: November 26, 2013Assignee: Canon Kabushiki KaishaInventor: Yoichi Matsuyama
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Publication number: 20130311731Abstract: A system and method of making golden master is disclosed. A user image is burned to a hard disk drive. The user image includes a user partition. A user partition record pointing to the user partition is stored in the disk partition table (DPT) of the hard disk drive. A DPT clearing module removes the user partition record from the DPT. A diagnostic partition is established between the starting sector address and the ending sector address of the user partition in the hard disk drive. A diagnostic partition record pointing to the diagnostic partition is written into the DPT. A partition record resuming module adds back the user partition record into the DPT.Type: ApplicationFiled: March 14, 2013Publication date: November 21, 2013Applicants: HON HAI PRECISION INDUSTRY CO., LTD., HONG FU JIN PRECISION INDUSTRY (Shenzhen) CO., LTD.Inventors: GANG LIU, HAI-HUI WU, GEN-SHENG LI
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Patent number: 8589630Abstract: In a first aspect, a first method is provided. The first method includes the steps of (1) providing a cache having a plurality of cache entries, each entry adapted to store data, wherein the cache is adapted to be accessed by hardware and software in a first operational mode; (2) determining an absence of desired data in one of the plurality of cache entries; (3) determining a status based on a current operational mode and a value of hint-lock bits associated with the plurality of cache entries; and (4) determining availability of at least one of the cache entries based on the status, wherein availability of a cache entry indicates that data stored in the cache entry can be replaced. Numerous other aspects are provided.Type: GrantFiled: July 3, 2012Date of Patent: November 19, 2013Assignee: International Business Machines CorporationInventors: John D. Irish, Chad B. McBride, Andrew H. Wottreng
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Publication number: 20130304969Abstract: A system for storing data comprises a performance storage unit and a performance segment storage unit. The system further comprises a determiner. The determiner determines whether a requested data is stored in the performance storage unit. The determiner determines whether the requested data is stored in the performance segment storage unit in the event that the requested data is not stored in the performance storage unit.Type: ApplicationFiled: April 18, 2013Publication date: November 14, 2013Inventor: R. Hugo Patterson
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Patent number: 8583881Abstract: A method and system for use in electronic data retention are provided. The method includes receiving, via electronic communication, a request indication indicating a request to delete, shred, purge, or remove a record from a data retention system; generating a determination, by a processor in response to instructions stored on a non-transitory storage medium, indicating that the record is associated with a hold indicator that is not based on a retention period; and sending, via electronic communication, a denial of the request in response to the determination indicating that the record is associated with a hold indicator that is not based on a retention period.Type: GrantFiled: October 1, 2012Date of Patent: November 12, 2013Assignee: Google Inc.Inventors: Alan L. Stuart, Toby Lyn Marek, Avishai Haim Hochberg, David Maxwell Cannon, Howard Newton Martin
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Patent number: 8583972Abstract: A method of controlling a nonvolatile semiconductor memory including a plurality of blocks, each one of the plurality of blocks being a unit of data erasing, includes determining a monitored block as a candidate for refresh operation from among the plurality of blocks based on a predetermined condition. The method includes monitoring an error count of data stored in the monitored block and not monitoring an error count of data stored in blocks excluding the monitored block among the plurality of blocks. The method also includes performing the refresh operation on data stored in the monitored block in which the error count is larger than a first threshold value.Type: GrantFiled: June 1, 2012Date of Patent: November 12, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Toshikatsu Hida, Shinichi Kanno, Hirokuni Yano, Kazuya Kitsunai, Shigehiro Asano, Junji Yano
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Patent number: 8583872Abstract: A cache memory having a sector function, operating in accordance with a set associative system, and performing a cache operation to replace data in a cache block in the cache way corresponding to a replacement cache way determined upon an occurrence of a cache miss comprises: storing sector ID information in association with each of the cache ways in the cache block specified by a memory access request; determining, upon the occurrence of the cache miss, replacement way candidates, in accordance with sector ID information attached to the memory access request and the stored sector ID information; selecting and outputting a replacement way from the replacement way candidates; and updating the stored sector ID information in association with each of the cache ways in the cache block specified by the memory access request, to the sector ID information attached to the memory access request.Type: GrantFiled: August 19, 2008Date of Patent: November 12, 2013Assignee: Fujitsu LimitedInventors: Shuji Yamamura, Mikio Hondou, Iwao Yamazaki, Toshio Yoshida
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Patent number: 8578116Abstract: A system and a method for protecting the security of data stored externally to a data processing engine of a data processor using at least one secure pad memory that is mapped to internal memory of the data processing engine and to the external memory. The memory data protection system and method performs an arithmetic operation, such as a bitwise exclusive OR (“XOR”) operation, on data being read from the data processing engine or written to the external memory using data stored in secure pads of the secure pad memory, which data may be random numbers generated by a random number generator.Type: GrantFiled: March 28, 2006Date of Patent: November 5, 2013Assignee: Broadcom CorporationInventors: Xuemin Chen, Stephane W. Rodgers
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Patent number: 8572327Abstract: A system and method is provided wherein, in one aspect, a currently-requested item of information is stored in a cache based on whether it has been previously requested and, if so, the time of the previous request. If the item has not been previously requested, it may not be stored in the cache. If the subject item has been previously requested, it may or may not be cached based on a comparison of durations, namely (1) the duration of time between the current request and the previous request for the subject item and (2) for each other item in the cache, the duration of time between the current request and the previous request for the other item. If the duration associated with the subject item is less than the duration of another item in the cache, the subject item may be stored in the cache.Type: GrantFiled: August 19, 2011Date of Patent: October 29, 2013Assignee: Google Inc.Inventors: Timo Burkard, David Presotto
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Patent number: 8572336Abstract: A storage control apparatus of the present invention is able to duplicatively manage data in a cache memory even during maintenance work. When a memory package CMPK3 specified by a user is removed from the apparatus 1 (S2), a microprocessor 2 changes a pair that has been configured using CMPK2 and CMPK3 to a pair of CMPK2 and a free area of a CMPK1. As a result, received data (S5) is respectively written to multiple cache memories (S6, S7), and duplicatively managed.Type: GrantFiled: October 14, 2010Date of Patent: October 29, 2013Assignee: Hitachi, Ltd.Inventors: Masanori Fujii, Sumihiro Miura
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Publication number: 20130282995Abstract: In described embodiments, a multiple first-in, first-out buffer pointers (multi-FIFO pointers) alignment system includes synchronization circuitry to align multiple FIFO buffer operations. A FIFO read clock stoppage signal is generated by master logic that stops the read clock shared by all the transmit channels and then re-starts the read clock to align them. The FIFO read clock stoppage signal is applied to the read clock of all FIFOs which need to be aligned and, when rate change is needed, the FIFO read clock stoppage signal suspends the read clock, causing local write and read pointers to be reset. After the FIFO read clock stoppage signal is de-asserted, the read clock starts to all FIFOs concurrently, thereby aligning the channels.Type: ApplicationFiled: April 18, 2012Publication date: October 24, 2013Inventors: Jung Ho Cho, Vladimir Sindalovsky, Lane A. Smith
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Patent number: 8566514Abstract: Various embodiments for performing truncate operations in nonvolatile memory are described. In one embodiment, an apparatus may include a nonvolatile memory to perform one or more truncate operations on a data file written to the nonvolatile memory and a volatile memory to track a truncate operation performed in the nonvolatile memory. Other embodiments are described and claimed.Type: GrantFiled: July 7, 2011Date of Patent: October 22, 2013Assignee: Intel CorporationInventors: Swati Gera, Karey Hart, Neil Gabriel, Lawrence Chang, Patrick McGinty
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Patent number: 8566531Abstract: A system and method is provided wherein, in one aspect, a currently-requested item of information is stored in a cache based on whether it has been previously requested and, if so, the time of the previous request. If the item has not been previously requested, it may not be stored in the cache. If the subject item has been previously requested, it may or may not be cached based on a comparison of durations, namely (1) the duration of time between the current request and the previous request for the subject item and (2) for each other item in the cache, the duration of time between the current request and the previous request for the other item. If the duration associated with the subject item is less than the duration of another item in the cache, the subject item may be stored in the cache.Type: GrantFiled: August 21, 2009Date of Patent: October 22, 2013Assignee: Google Inc.Inventors: Timo Burkard, David Presotto
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Patent number: 8555010Abstract: One embodiment provides a computer system and data backup method which enable improvements in the response performance of a storage apparatus to a write request from a host apparatus. In a case where, during execution of same intra-enclosure copy processing, a primary storage apparatus receives a write request in which the data write destination is a storage area in a target range for the same intra-enclosure copy processing in a first primary volume in the primary storage apparatus, the primary storage apparatus transmits an advance notification storing an address of a storage area in a secondary storage apparatus which corresponds to the data write destination storage area designated in the write request to the secondary storage apparatus such that an on-demand copy is executed based on the advance notification in the secondary storage apparatus.Type: GrantFiled: March 24, 2011Date of Patent: October 8, 2013Assignee: Hitachi, Ltd.Inventors: Atsushi Yuhara, Hiroshi Kuwabara, Junichi Hiwatashi
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Publication number: 20130262798Abstract: One embodiment of the present invention includes a method for maintaining a shadow page table in at least partial correspondence with guest page mappings of a guest computation. The method marking with a traced write indication at least those entries of the shadow page table that map physical memory locations which themselves encode the guest page mappings, the marking identifying, for a hardware facility, a subset of memory access targets for which updates are to be recorded in a guest write buffer accessible to the virtualization system. Responsive to a coherency-inducing operation of the guest computation, the method reads from the guest write buffer and introduces corresponding updates into the shadow page table.Type: ApplicationFiled: May 14, 2013Publication date: October 3, 2013Applicant: VMware, Inc.Inventors: Keith ADAMS, Sahil RIHAN
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Publication number: 20130262739Abstract: A memory system having a plurality of modules operated so that a group of memory modules may operation in a RAID configuration having an erase hiding property. The RAID groups are mapped to areas of memory in each of the memory modules of the RAID group. More than one RAID group may be mapped to a memory module and the erase operations of the RAID groups coordinated such that the erase operations do not overlap. This may improve the utilization of a bus over which the memory module communicates with the controller. Where a memory module is replaced by a memory module having an increased storage capacity, the additional storage capacity may be mapped to an expanded logical address space.Type: ApplicationFiled: March 13, 2013Publication date: October 3, 2013Inventors: Jon C.R. Bennett, Daniel C. Biederman
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Patent number: 8549251Abstract: In some embodiments, an apparatus includes a register having a first portion and a second portion. The first portion of the register has multiple bits and the second portion of the register has multiple bits. Each bit from the multiple bits of the first portion of the register is associated with a bit from the multiple bits of the second portion of the register such that a bit from the multiple bits of the first portion of the register is set for its associated bit from the multiple bits of the second portion of the register to be written.Type: GrantFiled: December 15, 2010Date of Patent: October 1, 2013Assignee: Juniper Networks, Inc.Inventors: Murali Vemula, Sathish Shenoy
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Patent number: 8543793Abstract: In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.Type: GrantFiled: February 3, 2011Date of Patent: September 24, 2013Assignee: Intel CorporationInventors: Jason W. Brandt, Sanjoy K. Mondal, Richard Uhlig, Gilbert Neiger, Robert T. George
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Patent number: 8539159Abstract: Methods and apparatuses are disclosed for managing memory write back. In some embodiments, the method may include examining current and future instructions operating on a stack that exists in memory, determining stack trend information from the instructions, and utilizing the trend information to reduce data traffic between various levels of the memory. As stacked data are written to a cache line in a first level of memory, if future instructions indicate that additional cache lines are required for subsequent write operations within the stack, then the cache line may be written back to a second level of memory. If however, the future instructions indicate that no additional cache lines are required for subsequent write operations within the stack, then the first level of memory may avoid writing back the cache line and also may keep it marked as dirty.Type: GrantFiled: July 31, 2003Date of Patent: September 17, 2013Assignee: Texas Instruments IncorporatedInventors: Gerard Chauvel, Serge Lasserre, Dominique D'Inverno
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Publication number: 20130232309Abstract: A content alignment system according to certain embodiments aligns a sliding window at the beginning of a data segment. The content alignment system performs a block alignment function on the data within the sliding window. A deduplication block is established if the output of the block alignment function meets a predetermined criteria. At least part of a gap is established if the output of the block alignment function does not meet the predetermined criteria. The predetermined criteria is changed if a threshold number of outputs fail to meet the predetermined criteria.Type: ApplicationFiled: January 25, 2013Publication date: September 5, 2013Applicant: CommVault Systems, Inc.Inventors: Manoj Kumar Vijayan, Deepak Raghuath Attarde, Srikant Viswanathan
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Patent number: 8521972Abstract: The present invention is directed to systems and methods for optimizing garbage collection in data storage. The data storage may be a shingled disk drive or a non-volatile solid-state memory device. Garbage collection is optimized by selectively saving data read from certain locations of the data storage in response to host read commands and using the saved data for subsequent garbage collection operations. The decision of whether to save data may be based on a number of criteria, including whether the data is located in an area of the data storage that is due to be garbage collected in the near future. In this manner, certain garbage collection operations can be performed without having to re-read the saved data.Type: GrantFiled: June 30, 2010Date of Patent: August 27, 2013Assignee: Western Digital Technologies, Inc.Inventors: William B. Boyle, Robert M. Fallone
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Publication number: 20130219135Abstract: A technique manages a virtual hard disk tree in a computing system executing a hypervisor to provide a client virtualization environment. The technique involves linking, by a client executing within a control virtual machine of the client virtualization environment, a first delta image of a virtual hard disk generated later in time to a base image of the virtual hard disk. The technique further involves modifying contents of the first delta image, the base image, and a second delta image which is linked to the base image; and deleting the second delta image after modifying the contents of the first delta image, the base image, and the second delta image. The base image and the first delta image, together with additional delta images of the virtual hard disk comprise a tree of images of the virtual hard disk.Type: ApplicationFiled: February 21, 2012Publication date: August 22, 2013Applicant: CITRIX SYSTEMS, INC.Inventors: Jonathan Knowles, Vincent Robert Hanquez
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Patent number: 8516193Abstract: Described are techniques for data processing and caching. In response to a client failing to retrieve contents of a data element from a cache location specified by a first data element identifier including a first content-based identifier, the contents of the data element are obtained and stored at a cache location specified by the first data element identifier. The contents of the data element are updated at a second point in time and stored as second contents in the data element source. The data element at the second point in time has a second content-based identifier. In response to the client failing to retrieve the second contents of the data element from a cache location specified by a second data element identifier including the second content-based identifier, the second contents of the data element are obtained and stored at a cache location specified by the second data element identifier.Type: GrantFiled: November 6, 2009Date of Patent: August 20, 2013Assignee: Pegasystems Inc.Inventors: John Clinton, Timothy Joseph Martel, Bachir Mohamed Berrachedi