Abstract: A microprocessor is connected to a first memory space through a first bus and to a second memory space through a second bus. The microprocessor includes a processing unit that includes a program bus and a data bus, and an interface unit connected, on one side, to the program bus and to the data bus and, on the other side, to the first and second buses. The interface includes a switching circuit for connecting the program bus and the data bus, respectively, to either the first bus or the second bus, in accordance with respective requests for accessing the program and data sent by the processing unit.

Abstract: A heterogeneous computer system, a heterogeneous input/output system and a data back-up method for the systems. An I/O subsystem A for open system and an I/O subsystem B for a mainframe are connected by a communication unit. In order to back up the data from at least a disk connected to the I/O subsystem B in a MT library system and in order to permit the mainframe to access the data in the I/O subsystem B, the I/O subsystem A includes a table for assigning a vacant memory address in a local subsystem to the memory of the I/O subsystem for an open system. A request of variable-length record format received from the mainframe is converted into a fixed-length record format for the subsystem B. The disk designated according to the table is accessed, and the data thus obtained is sent to the mainframe and backed up in the back-up system.

Abstract: In the method of generating an interleaved address, each 2{circumflex over ( )}i mod (p−1) value for i=0 to x−1 is stored. Here, p is a prime number dependent on a block size K of a data block being processed and x is greater than one. An inter-row sequence number is multiplied with a column index number to obtain a binary product. Both the inter-row sequence number and the column index number are for the block size K and the prime number p. Then, each binary component of the binary product is multiplied with a respective one of the stored 2{circumflex over ( )}i mod (p−1) values to obtain a plurality of intermediate mod value. An intra-row permutation address is generated based on the plurality of intermediate mod values, and an interleaved address is generated based on the intra-row permutation address.

Abstract: A data buffer of a memory controller receives first program data, whose size is smaller than that of a page buffer, from a system, and holds the received data. A data adding circuit of the memory controller adds mask data to the first program data, to generate second program data whose size is equal to that of the page buffer. Since the mask data are not programmed to memory cells, only the first program data, which are supplied from the system, are programmed to pages of a nonvolatile semiconductor memory. Namely, even when the size of the page buffer of the nonvolatile semiconductor memory is large, it is possible to maintain interchangeability with an exiting system only by using the memory controller of the present invention.

Abstract: An address range checking circuit capable of determining if a target address, A[M:0], is within an address space having 2N address locations beginning at a base address location, B[M:0], is disclosed, wherein the address range checking circuit does not require a large comparator circuit.

Abstract: A memory controller comprises a programmable interface coupled to address circuitry. The programmable interface receives a configuration signal into the memory controller indicating a selected address configuration. The address circuitry processes system addresses based on the selected address configuration to generate memory addresses. The configuration signal may also indicate a selected memory configuration, and the address circuitry processes the system addresses based on the selected memory configuration to generate memory device selections.

Abstract: Disclosed is a method for analyzing a sequence of data arrays. A selection of at least one type of region of interest and at least one region of interest from said data arrays is made. The sequence of data arrays are then transformed into a simplified data array. Events of interest in the selected regions of interest are then detected and stored in a second simplified data array.

Abstract: A method of reprogramming classification data in a packet classification state machine without interrupting the operation of the state machine is disclosed. Data relating to a plurality of new nodes from a starting node of the classification tree within a classification tree are stored such that they accurately indicate subsequent nodes within the existing data structure. Once the data is stored, a new first node address is stored in a predetermined location. Thereby causing subsequent state machine executions to begin at a new node. Preferably, the new first node address is stored using an atomic operation such that no reading of the first node address is possible during the store operation. The method allows a plurality of state machines to simultaneously use a same classification data memory because the method does not involve overwriting existing data.

Abstract: An object of the invention is to provide an image memory system capable of efficiently reading out image data also in case of consecutively reading out image data from an image memory along a direction other than the direction in which a burst access can be performed. In case that a bit-map image is partitioned into square or rectangular blocks and image data of pixels contained in one block are made to correspond to one row space, row spaces respectively corresponding to two blocks being adjacent to each other with a common side between them are made to belong to different synchronous DRAMs without fail and all of row spaces respectively corresponding to four blocks having commonly one vertex are made to belong to different banks.

Abstract: A one-time programmable memory is described with a storage allocation table which is compatible with a host computer.

Abstract: An address counter and address counting method is provided for enhancing an operational speed by forming a path for outputting a corresponding output address as soon as an external address or a previous internal address is inputted and further generating both a path for the case when a parity signal having a high state is inputted and a path for the case when a parity signal having a low state is inputted. While the paths are being produced, the parity signal is generated and the next internal address is immediately outputted in response to the generation of the parity signal. Moreover, an operation of latching the next address is terminated as soon as the parity signal is generated.

Abstract: A processing or control system having arrangements for separately and simultaneously generating instruction addresses and data addresses having two bus systems for accessing instruction and data storage, and having a single address range for both instructions and data. The boundary between the instruction range and the data range can be varied and placed under the control of the processor according to the needs of the particular application being processed. Some or all of the blocks of storage can access either the instruction bus or the data bus system, and the selection is made under the control of a control register within the processor. Advantageously, applications which require a larger amount of instruction storage, this can be provided; for applications which require a larger amount of data storage, that can be provided also; both are limited only by the total amount of storage available.

Abstract: Conventional information storage systems are subject to numerous practical constraints such as contiguity in the physical locations of blocks and the requirement that storage blocks be created in advance. Information retrieval in these systems has required the creation of indices, which take a long time to generate, and the structure of these systems makes them prone to deadlock because the indices are updated and the range of exclusion broadened when the referent information is modified. This invention utilizes the random access facilities of semiconductors to achieve high speeds and minimize the maintenance load. This invention introduces location tables and alternate-key tables to replace these indices. It also stores multiple records in a single block and can handle variable-length records and spanned records. The location tables manage the storage blocks.

Abstract: A system for interfacing over a multi-drop bus comprising a single-ended control interface coupled with a first power supply, and a common supply and a plurality of single-ended memory interfaces coupled with a second power supply, the common supply and coupled directly to the control interface. The control interface is configured to drive a control output signal and the memory interface is configured to drive a memory output signal. The output signals are driven to the common supply to transfer a logic low.

Abstract: A data processing system including a processor having a load/store unit and method for utilizing alias hit signals to detect errors within the read address tag arrays. Within a load store unit, implemented within a processor, a real address tag array is utilized to indicate when effective address aliasing occurs in a primary cache array. If aliasing occurs, Alias Hit signals are then used to clear any aliased entries. These Alias Hit signals can also be utilized to determine if there has been some type of failure within the real address tag array.

Abstract: An apparatus and method for creating packages and for transferring packages between computer systems provides a graphical user interface that allows a user to define various attributes for a package. Logical packages may be defined, which specify package elements to include in the package. Physical packages may also be defined, which contain a copy of the package elements specified in the logical package. Once a user defines a logical package, the logical package may be transferred to an endpoint system. The endpoint system reads the logical package, and from the parameters in the logical package determines where to retrieve the package elements and what other actions are appropriate while retrieving the package elements and constructing a physical package. In this manner, the endpoint system retrieves the package elements as required. The preferred embodiment of the present invention defines a packager using an object oriented framework mechanism that defines both core and extensible functions.

Abstract: Method for producing a predetermined length page memory pointer record, according to a selected page size and a selected page address, the method including the procedures of: determining a dynamic location of a separator bit within the page memory pointer record, according to the selected page size and an initial page size, the initial page size being respective of the smallest page size in a given memory system, writing a predetermined value to the dynamic location, writing a sequence of values opposite to the predetermined value to selected page size bits of the page memory pointer record, when the selected page size is different than the initial page size, and writing the selected page address to selected page address bits of the page memory pointer record.

Abstract: FIFO type memory is provided on a small circuit scale. Reading of data Dout<3:0> from a two-port type RAM (101) is executed with respect to the address specified by a read address (21) in synchronization with the fall of a clock (CLK) provided to a clock end (CLR). Writing of data Din<3:0> on the RAM (101) is executed with respect to the address specified by a write address (22) in synchronization with the rise of a clock (CLK) provided to a clock end (CLW). In an address delayer (103) after a read address (21) taking an address value is outputted, a write address (22) taking the same address value is always outputted with a fixed delay, so that a memory (100) performs the FIFO type data input/output as a whole.

Abstract: A surface computer includes an address generator for generating an address for adjusting surface region data concerning at least a storage region and a concurrent computer, provided at a subsequent stage of the address generator, having a plurality of unit computers.

Abstract: An auto (i.e., self)-relative pointer (114, 115) in a data structure (103) of a computer (100) defines a pointed-to location (106, 107) by means of an offset from its own location (104, 105). The address (124, 125) of the pointer is offset by the value (M, N) of the pointer obtain the address (126, 127) of the pointed-to location.

Abstract: A method of linear space target address generation for a relative branch is described. The method includes generating a selection signal, and generating a linear space target address using the selection signal by generating a plurality of corrected target addresses and selecting the linear space target address from the plurality of corrected target addresses using the selection signal.

Abstract: The method of the present invention comprises splitting pointer data in a code and data image, and allocating the upper half of each pointer in a compressed block to allow a system to exceed a memory addressing limitation during execution, while retaining the same data structure layout. In addition, the method of the present invention compresses and then allocates the upper pointer data “on demand” so that memory requirements during a large pointer (for instance, 64-bit) build are merely incremental over normal pointer (32-bit) requirements.

Abstract: A memory that supports non-aligned memory accesses includes a field address generator circuit, multiple field memories, and a data rotation circuit. The field address generator circuit generates multiple field addresses in response to an address associated with a memory access. Each field memory receives one of the field addresses from the field address generator circuit. The data rotation circuit rotates data associated with the memory access based upon the memory access address to support a non-aligned access. The memory can support either non-aligned read accesses or non-aligned write accesses. A method for performing non-aligned read or write memory accesses is also described.

Abstract: A virtual set cache that avoids virtual set store miss penalty. During a query pass of a store operation, only the untranslated physical address bits of the store address are used to index the cache array. In one embodiment, the untranslated physical address bits select four virtual sets of cache lines. In parallel with the selection of the four virtual sets, a TLB translates the virtual portion of the store address to a physical address. Comparators compare the tags of all of the virtual sets with the translated physical address to determine if a match occurred. If a match occurs for any of the four virtual sets, even if not the set specified by the original virtual address bits of the store address, the cache indicates a hit. The matching virtual set, way and status are saved and used during the update pass to store the data.

Abstract: A redundant disk array and improved method for redundant disk array access improve the performance of storage systems for computers. The disk array and method retrieve data from redundant drives according to an algorithm that will fetch contiguous pages from a single storage device, rather than alternating accesses between storage devices. The result is a reduced access time and increased data throughput.

Abstract: A programming method of a multilevel memory cell is able to store a plurality of bits in a plurality of levels. The method includes writing a logic value in the multilevel memory cell by setting one of the programming levels thereof, these levels being included in the plurality of levels, with respect to a reference level according to the symbol to be written and to a previous programming level. The writing step is repeated until a highest possible value for the levels is reached. A multilevel memory device includes a plurality of multilevel memory cells organized into sectors, split into a plurality of data units whereon a programming operation is performed in parallel.

Abstract: A memory module of the unbuffered type with ECC function is employed. Configuration of an internal C/A bus is set to a single T-branch topology. An output impedance of a chipset is maintained substantially constant. A capacitor for cutting high-frequency components of a C/A signal is added on a C/A bus.

Abstract: The present invention relates to disk drive having a cache control system that generates scan results that permit response to a host command using existing cached data having a logical block address (LBA) range that overlaps a host command LBA range. The cache control system forms variable length segments of memory clusters in a cache memory for caching disk data in contiguous LBA ranges. The cached LBA ranges are scanned for segments having LBA ranges overlapping with an LBA range of a host command.

Abstract: Initially, data is copied from a disk to a page frame and then to a read buffer, for instance. Next, a check is made to determine whether the percent of real memory occupied by file pages is less than a preset maximum volume. If so, no space is allocated for additional file page and no page frames are returned to the free list. If not, the VMM selects the best candidate file pages in real memory and returns them to the free list. Ideal candidates are a thread's memory pages, from a thread doing sequential I/O the file system. In so doing, the page frames are added to the free list as soon as the I/O is complete.

Abstract: A semiconductor memory device has a burst write mode in which predetermined plural command signals are input through a plurality of command pads and a mask control operation in the burst write mode is performed in response to the command signals. Therefore, the mask control in burst write mode is increased in speed to give an improved data transfer rate.

Abstract: A branched command/address bus architecture between a memory register and a plurality of memory units includes a main bus connected to the memory register. A first sub-bus is connected to the main bus and branches into a first number of memory unit buses, wherein each of them is connected to a command/address input of a memory unit associated with the same. A second sub-bus is also connected to the main bus and branches into a second number of memory unit buses, wherein each of them is connected to a command/address input of a memory unit associated with the same, wherein the second number is smaller than the first number. Further, the second sub-bus branches into a number of auxiliary buses, wherein the number of auxiliary buses corresponds to the difference between the first number and the second number, wherein each auxiliary bus is capacitively loaded corresponding to the memory unit buses and does not serve for driving a memory unit.

Abstract: The invention relates to a method and an arrangement for the verification of NV fuses as well as to a corresponding computer program product and to a corresponding computer-readable storage medium which can be used notably for the detection of attacks on the smart card security which modify EEPROM contents and hence also the contents of EEPROM fuses.

Abstract: Apparatus for addressing a data memory (21), with the apparatus (1) having:

Abstract: The present invention provides a memory architecture allowing for instructions of variable length to be stored without wasted memory spaces. Instructions of one, two, and three bytes can all be retrieved in a single fetch. The exemplary embodiment divides the memory block into two x16 memories having some special addressing circuitry. This structure logically arranges the memory into a number of rows, each of four byte-wide columns. To the first of these x16 memories, the full address is provided. If the address is within the two columns of the second x16 memory; the full address is also provided to the second x16 memory. If the address is to the first of the x16 memories, the second x16 memory instead receives the portion of the address specifying the row with one added to it. This results in a dual row access with the last one or two bytes of 3-byte instruction being supplied by the row above the first byte.

Abstract: There is disclosed an address range checking circuit capable of determining if a target address, A[M:0], is within an address space having 2N address locations beginning at a base address location, B[M:0], wherein the address range checking circuit does not require a large comparator circuit.

Abstract: Conventional information storage systems are subject to numerous practical constraints such as contiguity in the physical locations of blocks and the requirement that storage blocks be created in advance. Information retrieval in these systems has required the creation of indices, which take a long time to generate, and the structure of these systems makes them prone to deadlock since the indices are updated and the range of exclusion broadened when the referent information is modified. This invention utilizes the random access facilities of semiconductors to achieve high speeds and minimize the maintenance load. This invention introduces location tables and alternate-key tables to replace these indices. It also stores multiple records in a single block and can handle variable-length records and spanned records. The location tables manage the storage blocks.

Abstract: A method and system for memory access comprising address transformation means for generating a single value of memory address (y) from one or more corresponding values of an input quantity in which the number of values of the input quantity that correspond to a single value of the memory address varies across the range of values of the input quantity. The relationship between an input quantity and the corresponding memory address may be characterised as a hyperbolic function.

Abstract: A data carrier is disclosed for the communication of transmission information to a communication station. In particular, the data carrier includes a program memory for storing a program code including instruction and address information in at least one program code line, a data memory for storing data information, and a processor for processing the communicated transmission information, wherein each program code line address mode information included in the instruction information and the associated address information can be determined/processed to access a memory location of the program or data memory, and includes an address mode extension device, which in the presence of specific address information, determines stored additional address mode information.

Abstract: A neuronal phase-locked loop (NPLL) that can decode temporally-encoded information and convert it to a rate code is based on an algorithm similar to that of the electronic PLL, but is a stochastic device, implemented by neural networks (real or simulated). The simplest embodiment of the NPLL includes a phase detector (that is, a neuronal-plausible version of an ideal coincidence detector) and a controllable local oscillator that are connected in a negative feedback loop. The phase detector compares the firing times of the local oscillator and the input and provides an output whose firing rate is monotonically related to the time difference. The output rate is fed back to the local oscillator and forces it to phase-lock to the input. Every temporal interval at the input is associated with a specific pair of output rate and time difference values; the higher the output rate the further the local oscillator is driven from its intrinsic frequency.

Abstract: A data processing system having a central processing (CPU) unit and a method of operation is provided. The CPU has an instruction set architecture that is optimized for intensive numeric algorithm processing. The CPU has dual load/store units connected to dual memory target ports of a memory controller. The CPU can execute two aligned data transfers each having a length of one byte, two bytes, four bytes, or eight bytes in parallel by executing two load/store instructions. The CPU can also execute a single non-aligned data transfer having a length of four bytes or eight bytes by executing a non-aligned load/store instruction that utilizes both memory target ports. A data transfer address for each load/store instruction is formed by fetching the instruction, decoding the instruction to determine instruction type, transfer data size, and scaling selection, selectively scaling an offset provided by the instruction and combining the selectively scaled offset with a base address value.

Abstract: A pointer circuit for pointing to elements in at least one collection of elements comprises a base pointer adapted to provide a first binary-coded value defining a first address of an element in the collection. The pointer circuit also comprises a binary shift circuit receiving the first binary-coded value provided by the base pointer and a second binary-coded value defining a shift value. The binary shift circuit combines the first and second binary-coded values to provide a third binary-coded value defining a second address of an element in the collection differing from the first address by the shift value. A shift value generator fed by the first binary-coded value generates the second binary-coded value depending on the first binary-coded value, in such a way that a generated shift value takes into account shift values corresponding to first binary-coded values preceding a current first binary-coded value in a prescribed first binary-coded value progression order.

Abstract: A system and method for storing only one copy of a data block that is shared by two or more processes is described. In one embodiment, a global/non-global predictor predicts whether a data block, specified by a linear address, is shared or not shared by two or more processes. If the data block is predicted to be non-shared, then a portion of the linear address referencing the data block is combined with a process identifier that is unique to form a global/non-global linear address. If the data block is predicted to be shared, then the global/non-global linear address is the linear address itself. If the prediction as to whether or not the data block is shared is incorrect, then the actual value of whether or not the data block is shared is used in computing a corrected global/non-global linear address.

Abstract: A transparent memory array has a processor and a plurality of memory banks, each memory bank being directly connected to the processor. The memory array has improved throughput performance in part because it can function without precharge signals, row address latch signals, and column address latch signals, among others. The transparent memory array further comprises a plurality of row address decoders, each having a row address input bus and a row address output bus. One row address decoder's input bus is connected to the processor, while its output bus is connected to a first memory bank. The memory array is also comprised of a plurality of column address decoders, each having a column address input bus and a column address output bus. One column address decoder's input bus is connected the processor, while its output bus connected to the first memory bank.

Abstract: A device is provided for accessing circuit units via access registers. The circuit units have a plurality of inputs for access to said circuit units. A first access register having register outputs which are connected to a first part of the inputs of at least one first circuit unit, and having register outputs which are connected to inputs of at least one second circuit unit is provided. In addition, a second access register having register outputs which are connected to a second part of the inputs of said at least one first circuit unit, and having register outputs connected to inputs of at least one third circuit unit is provided.

Abstract: Embodiments are provided in which a first and second instructions are executed in parallel. A first and a second address are generated according to the first and second instructions, respectively. The first address is used to select a data cache line of a data cache RAM and a first data bank from the data cache line. The second address is used to select a second data bank from the data cache. The first and second data banks are outputted in parallel from the data cache RAM. An instruction pair testing circuit tests the probability of the first and second instructions accessing a same data cache line of the data cache RAM. If it is unlikely that the two instructions will access a same data cache line, the second instruction is refetched and re-executed, and the second data bank is not used.

Abstract: A micro-controller is connected to an external circuit via an address bus and a read control signal line. The external circuit includes an enable circuit, a decoder and a register group. The enable circuit produces an enable signal from the sixteenth bit of 16-bit information on the address bus and a control signal on the read control signal line. The decoder creates an address from the ninth to fifteenth bits of the 16-bit information. When the enable signal is valid, the register group writes a signal value of the first to eighth bits of the 16-bit information into a register specified by the address. Accordingly, the micro-controller can send the read control signal, the register address and the register data to the external circuit via the address bus. It is therefore possible to write data into the external circuit without using a write control signal line.

Abstract: A ferroelectric memory circuit (C) comprises a ferroelectric memory cell in the form of a ferroelectric polymer thin film (F) and first and second electrodes (E1; E2) respectively, contacting the ferroelectric memory cell (F) at opposite surfaces thereof, whereby a polarization state of the cell can be set, switched or detected by applying appropriate voltages to the electrodes (E1; E2). At least one of the electrodes (E1; E2) comprises at least one contact layer (P1; P2), said at least one contact layer (P1; P2) comprising a conducting polymer contacting the memory cell (C), and optionally a second layer (M1; M2) of a metal film contacting the conducting polymer (P1; P2), whereby said at least one of the electrodes (E1; E2) either comprises a conducting polymer contact layer (P1; P2) only, or a combination of a conducting polymer contact layer (P1; P2) and a metal film layer (M1; M2).

Abstract: An optical storage medium includes a plurality of tracks and a plurality of information pits arranged in the tracks. The information pits are designed to produce reflection light upon irradiation of light. The information pits are disposed in a matrix layout so that the reflection light includes at least four diffracted rays. An information pit is offset from the predetermined reference point in the track direction and the tracking direction. Thus, the particular information pit carries information indicated by the offset position relative to the reference point.

Abstract: A data processor in which a speed of an address translating operation is raised is disclosed. A translation lookaside buffer is divided into a buffer for data and a buffer for instruction, address translation information for instruction is also stored into a translation lookaside buffer for data, and when a translation miss occurs in a translation lookaside buffer for instruction, new address translation information is fetched from the translation lookaside buffer for data. A high speed of the address translating operation can be realized as compared with that in case of obtaining address translation information from an external address translation table each time a translation miss occurs in the translation lookaside buffer for instruction.

Abstract: System and methods for addressing unique locations in an matrix are discloses. According to some embodiments, the system includes In another embodiment, a system consisting of a plurality of uniquely addressable locations is disclosed. These embodiments includes a plurality of virtual columns that include a plurality of serially connected switch elements. The plurality of switch elements may be one of a plurality of responsive types and responsive to at least one of a plurality of possible switching signal types.