Abstract: A card-cage audio visual signal control system with card ID assignment is disclosed. Cards are removably installed in slots inside a cage enclosure, each card performing a specific function with respect to audio visual signals applied to the card. Card IDs are used to communicate with the cards. Card IDs alternate between physical and logical addresses for each card, thus allowing the cards to be moved from slot to slot inside the cage enclosure without having to reprogram the card-cage audio visual signal control system every time a card is so moved.

Abstract: A computer system provides a program access to a first register during real mode operation by using an index register and a data register, wherein the index register and the data register are located in real mode memory space and the first register is located outside of real mode memory space.

Abstract: A memory may be configured to rearrange and store data to enable a conflict free mode for a memory access pattern required by a coder-decoder (codec).

Abstract: According to one embodiment of the present invention, a controller that partitions a media library for multiple host applications can, for each partition, assign a base element address for an element type and associate physical element addresses for elements of an element type with an index value. For a partition, the logical element address corresponding to a physical element address for an element can be determined by adding the index number associated with the physical element address to the base element address for that element type. The physical element address corresponding to a logical element address for an element can be determined by subtracting the base element address for the element type from the logical element address for the element. The result of subtracting the base element address from the logical element address is an index value for which the associated physical element address can be found.

Abstract: The present invention provides a method for copying data through a virtualized storage system using distributed table driven (I/O) mapping. In a system having a virtual disk (the “original disk”), a persistent mapping table for this virtual disk exists on a controller, and volatile copies of some or all entries in this mapping table are distributed to one or more more mapping agents. The method of the present invention creates a new virtual disk mapping table that has the exact same entries as the mapping table as the original virtual disk. The new snapshot disk then shares the same storage as the original disk, so it is space efficient. Furthermore, creating new snapshot disk involves only copying the contents of the mapping table, not moving data, so the creation is fast. In order to allow multiple virtual disks to share storage segments, writes to either the original virtual disk or the snapshot copy cannot be seen by the other.

Abstract: An address translation unit is provided for use in a computer system. The unit contains a set of page table entries for mapping from a virtual address to a packet address. Each page table entry corresponds to one page of virtual memory, and typically includes one or more specifiers. Each specifier relates to a different portion of the page, and maps from that portion of the page to a corresponding range of packet addresses. Accordingly, the unit allows for address translation to be performed with a sub-page granularity.

Abstract: A method, apparatus, and computer instructions for transferring data from a memory to a network adapter. A request is received to transfer data to a network adapter. An offset is set for a starting address of the data to align the data with an end of a frame in the memory, wherein the frame is transferred from the memory to the network adapter.

Abstract: A method and apparatus is described herein for managing bad blocks/sectors in a nonvolatile memory. Upon detecting an input/output fault to a target block in a nonvolatile memory, the target block is remapped to a spare block, if the block is predicted as a bad block. Remapping is done for blocks used to store code both in serial execution code sequences and code sequences utilizing address translation. The remapping of bad blocks/sectors in nonvolatile memory allows nonvolatile memory in computer systems to be robust and resilient in handling bad blocks.

Abstract: A method for automatically determining performance problems in a computer system due to a metric indicating a current memory peak load in the computer system is disclosed.

Abstract: An example memory quality assuring system is provided. The system may include a memory mapping logic configured to facilitate accessing memory locations and redirecting memory accessing operations. The system may also include a memory quality assurance logic configured to logically replace a first memory location with a second memory location, to initiate testing logically isolated memory locations, and to selectively logically remove tested memory locations based on the testing. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the application. It is submitted with the understanding that it will not be employed to interpret or limit the scope or meaning of the claims 37 CFR 1.72(b).

Abstract: Techniques are provided for synchronously transmitting data in parallel from an external memory device to a destination circuit using a sequential read mode. The memory device includes an address counter. The address counter generates sequential read addresses for the data bits stored in the memory device. The destination circuit generates a clock signal that controls the address counter. The destination circuit can also transmit a start address to the memory device. The address counter sequentially generates a new read address in response to transitions in the clock signal beginning with the start address. Data bits are transferred in parallel from the memory device to the destination circuit.

Abstract: An embodiment of the present invention is a technique to process faults in a direct memory access address translation. A register set stores global control or status information for fault processing of a fault generated by an input/output (I/O) transaction requested by an I/O device. An address translation structure translates a guest physical address to a host physical address. The guest physical address corresponds to the I/O transaction and is mapped to a domain. The address translation structure has at least an entry associated with the domain and domain-specific control information for the fault processing.

Abstract: A method for providing synchronized updates to a data record in a data store, the data record including a plurality of data fields, each of the plurality of data fields having an initial field value, the method includes reading the data record from the data store into a data record in memory, each of the plurality of data fields of the data record in the data store having a corresponding data field in the data record in memory, the data fields in the data record in memory having inspectable and modifiable field values; identifying a set of relevant fields comprising at least one of an inspected field and a modified field of the data record in memory; in response to a determination that fields of the data record in the data store corresponding to each of the fields in the set of relevant fields has a value of its initial field value, updating the data record in the data store with the value of modified fields in the data record in memory.

Abstract: A system is provided in which a first storage device for managing a target to which a first physical port and a first logical volume are allocated, a second storage device for managing a second logical volume, and a computer for establishing a first communication path with the first physical port and conducting access to the target by using the communication path. The first storage device creates in the second storage devices a target holding an identifier identical to that of the aforementioned target and allocates the second logical volume and a second physical port to the target, and the computer establishes a second communication path with the second physical port and maintains the access to the target by using the second communication path.

Abstract: A pointer manager is described. The pointer manager includes write circuitry to enter, into a queue that is implemented with a first memory, a pointer value that a read hub has exhausted the use of. The pointer manager also includes read circuitry to remove, from said queue, a pointer value that is to be sent to a write hub. The pointer manager also includes write circuitry to add, to a link list that is maintained with a second memory, a pointer value that is to be sent to the write hub. The pointer manager also includes read circuitry to obtain, from said link list, a pointer value that is to be sent to a read hub.

Abstract: In one embodiment, a method is provided for storing data in a physical storage having at least one portion of unused memory, comprising maintaining a first list comprising one or more records associated with respective segments within the unused memory, and receiving a request to store data in at least one logical storage sector associated with the physical storage. A record associated with a segment of the unused memory in which at least some of the data is to be stored is selected from the first list, and the record is updated to include an identifier of the at least one logical storage sector. The record is stored in a second list that associates respective segments with respective logical storage sectors.

Abstract: One or more methods and/or systems of utilizing a memory external to an integrated circuit chip are presented. In one embodiment, the system comprises an integrated circuit containing a logic circuitry, a one time programmable memory, a control processor, and a data interface. In one embodiment, a method of storing data into a memory comprises programming one or more bits of a one time programmable memory, generating an identifier from the integrated circuit chip, and using the identifier to store data within the memory.

Abstract: An electronic system comprises a control unit for ordering the storage of an index value for indexed registers, in an additional index register linked to a defined initiator module, in response to a request to write the index value in an index register linked to the indexed registers, initiated by the initiator module. In response to any request to access an indexed register initiated by a defined initiator module, the control unit copies the index value from the additional index register linked to this initiator module to the index register linked to this indexed register, prior to execution of the access request. This enables management of access to indexed registers associated with an arbitration mechanism provided for managing conflicting access requests initiated by different functional modules in a system on a chip.

Abstract: The prevalence of identical vulnerabilities across software monocultures has emerged as the biggest challenge for protecting the Internet from large-scale attacks against system applications. Artificially introduced software diversity provides a suitable defense against this threat, since it can potentially eliminate common-mode vulnerabilities across these systems. Systems and methods are provided that overcomes these challenges to support address-space randomization of the Windows® operating system. These techniques provide effectiveness against a wide range of attacks.

Abstract: The invention relates to a method and an array for determining the IP addresses of a terminal array connected to an IP network by means of a telecommunication network. A pseudo-hardware address is administratively assigned as identifier to the subscriber connection of the terminal array. Said identifier is stored in the peripheral area of the telecommunication network and transmitted in an IP address request by the terminal array to a network management unit for assigning IP addresses. Said network management unit assigns an IP address using the identifier of the terminal connection and transmits said address to the terminal array.

Abstract: A system and method are shown for load balancing across global network resources using an existing network protocol, such as Mobile IP, having a redirect feature. According to one method, each of a plurality of servers at a data center uses Mobile IP to obtain an IP address that is also provided to a content server site. Further, a content server site includes a plurality of IP addresses assigned to the plurality of servers and creates a load database including load data for each server. When a client request is received at the content server site from a client device, the content server site determines a network address of a server to process the client request based on the load data, and provides the network address of the server to the client device. When the client device receives the network address of the server, the client device sends an application request to the selected server, and the selected server sends an application response to the client device.

Abstract: A CAM system (200) can include a number of entries (202-0 to 202-3) having one portion for storing a data value (e.g., E1) and another portion for storing a replicated data value (E1(REP)). For on-the-fly error correction, the entries can be searched by applying an appended key value that includes a key portion (KEY) and replicated key portion (KEY(REP)).

Abstract: A storage device for a multibus architecture includes at least one memory to store data, information, and/or addresses, along with a memory connection having a port to connect the memory to one of the buses of the multibus architecture. The memory connection, the port, and the bus have data lines to transmit data along with address lines to transmit addresses, and/or control information to control the memory and other devices connected to each specific bus within the multibus architecture. A switching device selectively connects the memory connection to one of the buses to enable a memory access to transmit data, addresses, and/or control information to or from the selected one of these buses.

Abstract: A system, apparatus, and method are disclosed for increasing the physical memory size accessible to a processor, at least in part, by reclaiming physical address space typically associated with addresses of a restricted linear address space (i.e., addresses that are otherwise unusable by the processor as system memory). In one embodiment, an exemplary memory controller redirects a linear address associated with a range of addresses to access a reclaimed memory hole. The memory controller includes an address translator configured to determine an amount of restricted addresses and to establish a baseline address identified as a first number being a first integer power of 2. The range of addresses can be located at another address identified as a second number being a second integer power of 2. As such, the address translator translates the linear address into a translated address associated with the reclaimed memory hole based on the baseline address.

Abstract: A hardware implemented method for writing data to a cache is provided. In this hardware implemented method, a Block Initializing Store (BIS) instruction is received to write the data from a processor core to a memory block. The BIS instruction includes the data from the processor core. Thereafter, a dummy read request is sent to a memory controller and known data is received from the memory controller without accessing a main memory. The known data is then written to the cache and, after the known data is written, the data from the processor core is written to the cache. A system and processor for writing data to the cache also are described.

Abstract: In a virtual computer system, the invention virtualizes a primary protection mechanism, which restricts memory accesses based on the type of access attempted and a current hardware privilege level, using a secondary protection mechanism, which is independent of the hardware privilege level. The invention may be used to virtualize the protection mechanisms of the Intel IA-64 architecture. In this embodiment, virtual access rights settings in a virtual TLB are translated into shadow access rights settings in a hardware TLB, while virtual protection key settings in a virtual PKR cache are translated into shadow protection key settings in a hardware PKR cache, based in part on the virtual access rights settings. The shadow protection key settings are dependent on the guest privilege level, but the shadow access rights settings are not.

Abstract: A system, apparatus, and method are disclosed for controlling accesses into memory to minimize sequential accesses to the same bank of memory, at least in part, by characterizing a subset of an address in parallel with address translations associated with those accesses. In one embodiment, an exemplary memory controller can include an address translator configured to translate an address useable by a processor to a first memory address. Also, the memory controller includes a bit characterizer configured to characterize a subset of the address as having a value from a range of values, and a bank separator coupled to the address translator and the bit characterizer for receiving a first portion of the first memory address and the value, respectively. Accordingly, the bank separator is configured to differentiate the first portion from a second portion of a second memory address.

Abstract: A trusted data store is provided for use with a trusted element of a trusted operating system on a computing machine. In the trusted data store, a storage medium stores data in a pre-determined arrangement, where the data includes trusted data from the trusted element of the trusted operating system on the computing machine. An access controller writes data to and reads data from the storage medium, and a trust controller is interposed between the computing machine and the access controller. The trust controller allows only the trusted element to perform operations on the trusted data thereof on the storage medium.

Abstract: Methods and apparatus for accessing multiple memory arrays within a memory device using multiple sets of address/data lines are provided. The memory arrays may be accessed independently, using separate addresses, in one mode of operation, and accessed using a common single address in another mode of operation.

Abstract: The present invention relates to a method and a device for the fast verification of sector addresses in a data stream obtained from a recording medium upon a request from a microcontroller. According to the invention, the method comprises the steps of: reading the data stream from the recording medium; decoding the data stream to obtain a decoded data stream comprising user data and sector addresses; comparing the sector addresses with a range of valid sector addresses; and transmitting only user data having sector addresses within the range of valid sector addresses; whereby dedicated comparing means are provided for performing the comparing step independently of the microcontroller.

Abstract: A high speed, microcomputer based, Fibre Channel compatible and fault tolerant information processing and mass storage system especially suited for information servers and application servers. A unique and extremely versatile system architecture, including a dual loop arbitrated, Fibre Channel capable, multiple-fault tolerant, hot-swappable mass storage disk array, permits combinations of servers and mass storage arrays which can be tailored for a wide variety of applications and which can be configured with emphasis on the system characteristics such as redundancy, speed, processing capability, storage capability, and the like, as desired. A unique backplane and/or midplane arrangement for connecting the system components allows for easy and, in most cases, on-line field upgrading and/or service and at the same time provides for the very effective cooling of components, particularly those such as disk drives which tend to produce a lot of heat.

Abstract: When a peripheral LSI has a memory space which is other than the memory space of a CPU, access is made without one of the memory spaces being aware of the other memory spaces. A flexible bus controller BSC makes address translation according to information on the relation between addresses of both memory spaces. The invention assures wider latitude in CPU type selection and makes it easy to reuse an existing program or develop a new program.

Abstract: A content prefetcher having a prefetch chain reinforcement mechanism. In response to a prefetch hit at a cache line within a prefetch chain, a request depth of the hit cache line is promoted and the hit cache line is scanned for candidate virtual addresses in order to reinforce the prefetch chain.

Abstract: An instruction buffer and a method of buffering instructions.

Abstract: Method and apparatus for use with buffered memory modules are included among the embodiments. In exemplary systems, the memory module has a buffer that receives memory commands and data, and then presents those commands and data to physical memory devices through a separate interface. The buffer has the capability to accept an implicit memory command, i.e., a command that does not contain a fully-formed memory device command, but instead instructs the memory module buffer to form one or more fully-formed memory device commands to perform memory operations. Substantial memory channel bandwidth can be saved, for instance, with a command that instructs a memory module to clear a region of memory or copy a region to a second area in memory. Other embodiments are described and claimed.

Abstract: Method and apparatus for keeping and maintaining inventory of logical entities stored in a computer storage system are disclosed. Identifying information for each user of a logical volume is maintained. As a part of the inventory process, this system may verify that the logical volume is still in use, for example by determining when it was last accessed and if a certain time threshold has been exceeded, verifying with the users of the logical entity that logical entity is no longer needed to be stored at its current location.

Abstract: The invention concerns a monitoring device (18) integrated to a microprocessor chip (12) executing a series of instructions comprising: device (26) for producing simultaneously several types of monitoring messages of the microprocessor, a buffer (28) divided into several blocks (A, B, C, D, E) each of which is designed to store only messages of one of the types capable of being produced simultaneously, the size of each block depending on the maximum frequency at which the messages can be stored, and device (26) for, each time one or more messages are simultaneously stored in the blocks (A, B, C, D, E) of the buffer (28), storing in a predetermined block (F) of the buffer a coded value representing said block(s) of the buffer.

Abstract: The generation and selection of addresses to be employed in a verification environment are tightly coupled to ensure that the addresses a user desires to be selected have been generated. Addresses are generated based on one or more defined selection attributes. The generated addresses are maintained in a database structure that also includes any attributes associated with the addresses. At least one address is selected from the database structure via a filter and forwarded to a component under test.

Abstract: Various embodiments of the present invention are directed to methods by which a virtual-machine monitor can introduce branch instructions, in order to emulate privileged and other instructions on behalf of a guest operating system, into guest-operating-system code residing on virtually aliased virtual-memory pages. In a described embodiment of the present invention, the virtual-machine monitor physically aliases each virtual alias for a particular physical memory page by allocating a physical page for the virtual alias, copying the original contents of the physical memory page to the allocated physical page, or physical alias page, and subsequently patching each physical alias page appropriate to the physical address of the physical alias page.

Abstract: A processor includes a trace cache memory coupled to a trace generator. The trace generator may be configured to generate a plurality of traces each including one or more operations that may be decoded from one or more instructions. Each of the operations may be associated with a respective address. The trace cache memory is coupled to the trace generator and includes a plurality of entries each configured to store one of the traces. The trace generator may be further configured to restrict each of the traces to include only operations having respective addresses that fall within one or more predetermined ranges of contiguous addresses.

Abstract: A memory address decoding method for determining if a given address is located in one of a plurality of sections. Each section has a plurality of memory units arid each memory unit has a unique corresponding address, the corresponding address using the binary system. The method includes making die corresponding address in a section with greater size smaller than the corresponding address in a section with smaller size, building a single bit-pattern for each section from all corresponding addresses, and comparing if at least one comparative bit of the given address matches those in any of the bit-patterns so as to determine the given address is located in one of the sections based on the comparison.

Abstract: A system and method for enabling rapid partial configuration of reconfigurable devices includes a configuration definition unit and a configuration loading unit. The configuration definition unit defines partial configuration requirements, and contains at least a starting address of configuration data for the partial reconfiguration, data size specifying the number of contiguous locations to be reconfigured, and desired configuration data corresponding to the contiguous locations. The configuration loading unit provides for loading the configuration data into the reconfigurable device according to the partial configuration requirements without providing commands corresponding to any addresses outside of said configuration requirements.

Abstract: A scrambling operation is used to space apart the grants that a communication circuit receives during a period of time, such as 512 arbitration periods. An operator can enter the number of arbitration periods that a communication circuit is to receive in blocks of sequential logical address ranges. The logical addresses are then changed to physical addresses that are spaced apart, thereby significantly reducing the buffering required by the communication circuit.

Abstract: A method, system, and program manages updates of user data and parity data stored in stripes across a plurality of disk storage units arranged in a data organization type such as a RAID array. In one embodiment, a record of stripes potentially containing inconsistent user and parity data is stored on a disk storage unit. In another aspect, before writing a record of stripes to a disk storage unit, stripe entries for a plurality of write processes is permitted to accumulate. In another aspect, a record of stripes may be written to different disk storage units and a generation number is used to identify the latest record of stripes.

Abstract: The present invention relates to switching technology in computer networks and in particular to a method and system for switching information packets through a m input, n output device. According to the invention it is proposed to temporarily buffer said packets according to a new, self-explanatory, preferred a linear addressing scheme in which a respective buffer location of consecutive stream packets results from a respective self-explanatory, or linear, respectively, incrementation of a buffer pointer. Preferably, a matrix of FIFO storage elements (10,11,12,13) having an input and an output crossbar can be used for implementing input/output paralleling modes (ILP,OLP) and multiple lanes and achieving address input/output scaling up to a single cycle.

Abstract: A system and method for passing messages between domains with low overhead in a multi-node computer system. A CPU node in a sending domain issues a request to a memory node in a receiving domain using memory-mapped input/output window. This causes the message to be transmitted to a coherent space of the receiving domain. All messages are cache-line in size. A small portion of each cache line, cyclic counter field, is overwritten before the cache line is written in the coherent address space of the receiving domain. A massaging driver polls the cyclic count field of the cache line in the processor cache to determine when the next message is written in the coherent address space of the receiving domain. This allows the CPU to detect when the last received message is written into the coherent address space of the receiving domain without generating transactions on CPU interface.

Abstract: A method of operating a processor includes concatenating a first word and a second word to produce an intermediate result, shifting the intermediate result by a specified shift amount and storing the shifted intermediate result in a third word, to create an address.

Abstract: A branched command/address bus architecture between a memory register and a plurality of memory units includes a main bus connected to the memory register. A first sub-bus is connected to the main bus and branches into a first number of memory unit buses, wherein each of them is connected to a command/address input of a memory unit associated with the same. A second sub-bus is also connected to the main bus and branches into a second number of memory unit buses, wherein each of them is connected to a command/address input of a memory unit associated with the same, wherein the second number is smaller than the first number. Further, the second sub-bus branches into a number of auxiliary buses, wherein the number of auxiliary buses corresponds to the difference between the first number and the second number, wherein each auxiliary bus is capacitively loaded corresponding to the memory unit buses and does not serve for driving a memory unit.

Abstract: A system includes a processor, a storage system having one or more physical storage devices, and a controller coupled to the processor and the storage system. The controller maintains a virtual physical drive (VPD) map that defines a set of virtual physical drives, and maps the virtual physical drives to storage media of the physical storage devices. The controller receives access requests from the processor and controls the physical storage media according to the VPD map such that the virtual physical drives appear to the processor as physically independent drives. The controller provides hardware-level security to prevent unauthorized access by the processor or any software application executing on processor. In addition, the controller may maintain primary virtual storage and secondary virtual storage within the virtual physical drives, and may dynamically reallocate the virtual storage to backup and restore data in a manner that appears almost instantaneous to the user.

Abstract: Column addresses are generated by a burst controller that includes respective latches for the three low-order bits of a column address. The two higher order bits of the latched address bits and their compliments are applied to respective first multiplexers along with respective bits from a burst counter. The first multiplexers apply the latched address bits and their compliments to respective second multiplexers during a first bit of a burst access, and bits from a burst counter during the remaining bits of the burst. The second multiplexers are operable responsive to a control signal to couple either the latched address bits or their compliments to respective outputs for use as an internal address. The control signal is generated by an adder logic circuit that receives the two low-order bits of the column address.