Abstract: A system, method, apparatus, means and computer program code for writing data includes identifying a plurality of pages to be written to a data volume, each page including a file identifier and a key, creating a first page group from the plurality of pages, the first page group including pages associated with a first file as identified by the file identifier and sorted by the key; and writing the first page group to the data volume.

Abstract: A memory system having a memory controller and several separate memory devices connected to the controller by a system bus. The memory devices each included an array of memory cells, addressing circuitry used to address the cells and an address storage circuit which stores a local address unique to each of the memory devices. The local addresses are sequentially assigned to the memory devices by selecting a first one of the devices and forwarding an address assign command to the selected device. A command decoder, having detected the address assign command, will permit a local address placed on the bus by the controller to be loaded into the selected memory device. This sequence will continue until all of the memory devices have been assigned local addresses at which time the memory devices can be accessed to perform memory read, program, erase and other operations.

Abstract: A method and apparatus for block interleaving that eliminates the step of intermediary buffering. The method includes: (a) calculating a memory address at which first output data, of which number is equal to the number of rows of a first encoder is stored, (b) storing the first output data at the calculated memory address of a circular buffer, (c) storing second output data at an address which is incremented by a specific constant value from the calculated memory address of the circular buffer, and (d) storing (n+1)th output data at an address which is incremented by n from the calculated memory address of the circular buffer.

Abstract: A method and apparatus for addressing a plurality of mass memory components coupled to a host device. The memory components can be arranged in a chain or in a ring configuration. In a ring, each memory component receives a bit pattern from the preceding stage and sends a bit pattern to the next stage in consecutive clock periods. Based on the received bit pattern, a recipient component knows the bus width between itself and the sending component. In a chain, each memory component also sends the received bit pattern back to the preceding stage. The memory component can generate its own address by counting clock periods. Alternatively, a recipient component changes its received bit pattern before sending the bit pattern to the next stage. As such, the recipient component knows its address based on the received bit pattern.

Abstract: A data storing part outputs n-bit data according to a reading address generated by an address generator. A peak value candidate selecting part selects a maximum value of a plurality of elements forming the n-bit data as a peak value candidate when data of one data unit is expressed as one element and outputs the peak value candidate together with a positional information indicating an element position of the peak value candidate. When the peak value candidate is larger than a peak value held in a peak value holding part, a peak value calculating part calculates an address of the peak value candidate using the positional information of the peak value candidate and a reading address, outputs the address and the peak value candidate to the peak value holding part, and updates content held in the peak value holding part.

Abstract: A disk formatter includes an address module for creating disk block address data corresponding to a disk sector of a disk drive. A sector write module initiates a physical mode write operation to the disk sector that incorporates the corresponding disk block address data.

Abstract: In one embodiment, a method of a kernel dumper module includes generating a dump file associated with a kernel when the kernel crashes, storing the dump file to a functional memory upon applying an overwrite protection to a core dump of the dump file, restarting the kernel through a warm reboot of the kernel such that the core dump is not erased from the functional memory, and transferring the core dump to a system file using the kernel.

Abstract: Before arbitration is performed in an arbitration section, an access from a master is kept in a waiting state until update of a conversion table buffer is performed, and an address conversion section is provided in a subsequent stage of the arbitration section. Without waiting for the completion of buffer update, an access is issued in advance at a time when it is assured that update is completed at the completion of address conversion. Thus, influences of waiting buffer update on another master can be eliminated and access latency can be reduced.

Abstract: A system for aggregating portions of multiple blocks of data into a single composite block. The block of data comprises different packets of data stored in correspondingly different sections of a memory. The system gathers selected portions of the stored packets and then transfers the selected portions of the gathered packets into a transmitted block of data having the selected portions appended contiguously one to the other. The memory stores the packets in word-based locations, the word-based locations having a common word width, W. The stored packets have a variable number of bytes. The bytes of the gathered selected portions of the stored packets are offset from an initial byte position of the stored packets. The packets have variable offsets. Also, a disclosed is a system for distributing packets stored contiguously in a memory to a plurality of different non-contiguous memory locations.

Abstract: A memory of allocating memory for use by a subfunction of a computer chip, wherein the subfunction uses contiguous memory regions, the method comprising the steps of (a) creating a placeholder for contiguous memory buffers used by the subfunction of the chip by reserving a region of memory subsystem space, wherein the region does not need to be backed by true physical storage and the size is at least as large as the contiguous memory buffer required by the subfunction, (b) allocating pages of remaining memory in the memory subsystem to satisfy the amount of memory required by the subfunction, wherein the allocated pages do not necessarily result in a contiguous memory region, (c) remapping the allocated pages of step b into a contiguous region of the placeholder created in step a and (d) disabling the remapping after the subfunction is completed to free the memory in the placeholder.

Abstract: A circuit for transforming memory address is disclosed. A first memory address is transformed into a second memory address with more bits than the first memory address for providing a memory. The memory space is an even multiple of the maximum of the first memory address. Therefore a large memory can be used as a small memory.

Abstract: A system, method, and program product are provided that identifies a cache set using Translation LookAside Buffer (TLB) attributes. When a virtual address is requested, the method, system, and program product identifies a cache set using buffer attributes. When a virtual address is received, an attempt is made to load the received virtual address from a cache. When the attempt results in a cache miss, a page is identified within a Translation LookAside Buffer that includes the virtual address. A class identifier is then retrieved from the identified page, with the class identifier identifying a cache set that is selected from the cache.

Abstract: A system includes a memory, a plurality of pages held in the memory, an instruction translation look aside buffer (ITLB), a first data translation look aside buffer (DTLB), and a translation look aside (TLB) miss handler. The system also includes an executable/non-executable (x) indicator associated with each page in memory. The TLB miss handler sets the x-indicator for a particular page to indicate “non-executable” when that page is accessed in a mode that allows writing to that page. The ITLB or the ITLB miss handler refuses to allow instructions from a page with an associated x-indicator of “non-executable” to be loaded into the instruction buffer.

Abstract: A circular buffer storing packets for processing by one or more network processors employs an empty buffer address register identifying where a next received packet should be stored, a next packet address register identifying the next packet to be processed, and a packet-processing address register within each network processor identifying the packet being processed by that network processor. The n-bit addresses to the buffer are mapped or masked from/to the m-bit packet-processing address registers by software, allowing the buffer size to be fully scalable. A dedicated packet retrieval instruction supported by the network processor(s) retrieves a new packet for processing using the next packet address register and copies that into the associated packet-processing address register for use in subsequent accesses. Buffer management is thus independent of the network processor architecture.

Abstract: Systems and methods of monitoring logical block address (LBA) activity are disclosed. In an embodiment, a pattern of a data storage device may be monitored. An LBA may be detected that is accessed based on the pattern. The LBA may be added to a list of LBAs stored in a memory.

Abstract: A system and method for translating addressing protocols between two types of storage drives in a storage environment is provided. A storage environment may include a JBOD of Serial ATA drives coupled to a host server through an external SCSI connection. The addressing protocol of the host server will typically involve addressing each Serial ATA drive by a unique SCSI target ID. This addressing protocol of the host server is translated to an addressing protocol in which each Serial ATA drive is addressed through unique LUN identifier and a single SCSI target ID, which is the addressing scheme of some SCSI-based peripheral controllers.

Abstract: A method and a device for accessing data wherein the data is sequentially stored as data objects. The data objects are identified by a control variable having consecutive integer values. The control variable and the memory address is determined of a first known data object and an estimate for the size of a data object is determined therefrom. The control variable of the requested data object is multiplied by the estimate, as a result whereof an initial value for a memory address of the requested data object is formed. The actual control variable of the data object stored under the initial value is determined, the search for the requested data object being terminated in the case of correspondence between the actual control variable and the desired control variable, and otherwise the search is continued.

Abstract: A mobile device enables communication over a wireless communication network between the user of the mobile device and a correspondent. The mobile device includes a display having a plurality of display modes including a folder view display mode wherein a plurality of folders are viewable. An input device is operable to change the display mode of the display between the folder view display mode and other display modes. A memory within the mobile device stores a user selected folder selected from the plurality of folders. A processor controls the operation of the mobile device such that after the user selected folder is stored in memory, when the input device is operated to change the display mode of the display to the folder view display mode, the user selected folder is automatically displayed on the display.

Abstract: Since no control of accesses made by a computer as accesses to a storage apparatus is executed, the computer can be used illegally to steal and improperly change data stored in the storage apparatus. Thus, an access-control mechanism external to the computer is constructed to solve this problem. That is to say, the control of accesses is executed in the storage apparatus and a network apparatus for each program executed by the computer. In order to enhance the implementability of such control of accesses, the control is executed without extending a variety of protocols of communications among the computer, the network apparatus and the storage apparatus. By implementing the control of accesses in this way, a program other than programs specified in advance is not capable of making an access to data stored in the storage apparatus. Thus, even if the computer is used illegally, data stored in the storage apparatus can be prevented from being stolen and changed improperly.

Abstract: A method is provided for programming a DMA controller in a system on a chip. According to the method, a memory management unit translates a programming virtual address into a programming physical address according to a translation table. A first sub-block without discontinuity beginning at the programming physical address and ending at an end address equal to the physical address immediately preceding a first discontinuity is formed, with the first discontinuity being determined by a discontinuity module according to information supplied by a memory management unit. Some of the programming elements intended for the DMA controller are defined according to the first identified sub-block. Also provided is a system on a chip.

Abstract: A method for retrieving and managing addresses is provided. The steps may include of receiving, at a first buffer of m buffers, a request for an address; obtaining the address from a corresponding first register of the m registers; sending the address, received by said obtaining, to a destination; storing the address, received by the obtaining, in the first buffer; and clearing the contents of a second buffer of the m buffers, in response to any of said receiving, obtaining or storing, without clearing the contents of said first buffer, wherein m is a positive integer.

Abstract: A disk formatter includes an address module for creating disk block address data corresponding to a disk sector of a disk drive. A sector write module initiates a physical mode write operation to the disk sector that incorporates the corresponding disk block address data.

Abstract: Various embodiments of the present invention are directed to systems and methods for synchronizing mixed elements (MEs) comprising structure data and unstructured filestreams between peer computer systems in a hardware/software interface system environment that does not permit snapshotting of large unstructured ME filestreams during synchronization. For several such embodiments, the method comprises synchronizing the ME in two steps, one for snapshotting the structured data component of the ME (as well as the cv of the filestream but not the filestream itself) and one for locking and transmitting the filestream to the receiving sync peer if and only if, after being locked, it is determined that the filestream is unchanged from the time of the ME data component snapshot.

Abstract: Materials are described for producing memory cells which have a size in the nanometer range and include a CT complex located between two electrodes. The CT complex includes thiophene derivatives, pyrrole derivatives or phthalocyanines together with naphthalenetetracarboxylic acid, dianhydrides, diamides, fullerenes or perylene compounds.

Abstract: A moving window history of at least one previous data address accessed by a processor is maintained, the at least one previous data address in the history each being associated with an index. A difference between a current data address and one of the at least one previous data address in the history is determined. The difference and the index associated with the one of the at least one previous data address in the history are provided as a representation of the current address.

Abstract: The invention relates to a method for generating an identification data block (ID) for a data carrier (41), which data carrier (41) has a multiplicity of logical data blocks (300) continuously numbered with respective block numbers in a data block size, a reading of the data of the logical data blocks is carried out and the generating of the identification data block (ID) is carried out by means of a combining function from read first data of a logical first data block (301) defined by a first block number and from read second data of a logical second data block (302) defined by a second block number, wherein the logical second data block defined by the second block number is determined in dependence on the read third data of a logical third data block (303) defined by a third block number.

Abstract: There are provided a buffer circuit buffers data between a synchronous circuit and an asynchronous circuit, and a control method therefor. There are also provided an interface circuit that controls data transfer between a synchronous memory circuit and the asynchronous circuit, and a control method therefor, which are used in the buffer circuit and the control method therefor. A data buffer circuit that is interposed between an image processing system and a main system includes a one-port RAM, a control signal generating section, an subsequent cycle address generating section, and a first selector. The first selector selectively outputs the present cycle address to an address of the one-port RAM when an access to the one-port RAM is a write access, and selectively outputs the subsequent cycle address to the address of the one-port RAM when the access to the one-port RAM is a read access.

Abstract: One embodiment of the present invention includes a method for handling status commands direct to a partitioned media library that comprises establishing a set of initial logical element addresses for a set of physical element addresses with each initial logical element address corresponding to a physical element address of an element assigned to a library partition, assigning a set of new logical element addresses for the set of physical element addresses in response to a command from a host application (e.g., a MODE SELECT command) and determining a corresponding physical address for a received element address based on the set of new logical element addresses.

Abstract: A method and a programmable unit for bit field shifting in a memory device in a programmable unit as a result of the execution of an instruction, in which a bit segment is shifted within a first memory unit to a second memory unit, are presented. The bit segment is read with a first bit length from a first bit field in the first memory unit starting at a first start point. The bit segment that has been read is stored in the first bit field in the second memory unit starting at a second start point. The first or the second start points is updated by a predetermined value and the updated start point is stored for subsequent method steps.

Abstract: A memory system having a memory controller and several separate memory devices connected to the controller by a system bus. The memory devices each included an array of memory cells, addressing circuitry used to address the cells and an address storage circuit which stores a local address unique to each of the memory devices. The local addresses are sequentially assigned to the memory devices by selecting a first one of the devices and forwarding an address assign command to the selected device. A command decoder, having detected the address assign command, will permit a local address placed on the bus by the controller to be loaded into the selected memory device. This sequence will continue until all of the memory devices have been assigned local addresses at which time the memory devices can be accessed to perform memory read, program, erase and other operations.

Abstract: An embodiment of the present invention is a technique to perform address translation. A table structure is indexed by a source identifier of an input/output (I/O) transaction specifying a guest physical address and requested by an I/O device to map the I/O device to a domain assigned to the I/O device. An address translation structure translates the guest physical address to a host physical address corresponding to the I/O transaction.

Abstract: A multiple computer system is disclosed in which n computers (M1, M2 . . . Mn) each run a different portion of a single application program written to execute only on a single computer. The local memory of each computer is maintained substantially the same by updating all computers with every change made to addressed memory locations. Contention can arise when the same memory location is substantially simultaneously updated by two or more machines because of transmission delays and latency of the communications network interconnecting all the computers. In particular a method of data consolidation which permits contention detection and resolution is disclosed. A count value indicative of the cumulative number of times each memory location has been updated is utilized. Contention is indicated if the currently stored count value and the incoming updating count value are the same.

Abstract: An apparatus for a compact disk with an independent audio functionality is disclosed. The apparatus includes a logic core, an IDE controller, and a pass-through module, which are coupled to a micro-controller core. The logic core receives and sends signals to and from a system interface in response to the micro-controller core. The logic core disables sending signals to the system interface in response to the micro-controller core. The IDE controller core receives and sends signals to and from a CD drive interface in response to the micro-controller core. The IDE controller core also disables sending signals to the CD drive interface in response to the micro-controller core. The pass-through module is coupled to the system interface and to the CD drive interface. The pass-through module passes signals between the system interface and the CD drive interface when the computer is in power on mode.

Abstract: A computer system including input/output devices that transfer data and a computer that controls a process using a virtual storage and inputs data to and outputs data from a medium, wherein the input/output devices and the computer include address conversion tables for converting a virtual address into an actual address, the computer requests all the input/output devices to permit page operation such as page-out processing, processing for deleting a virtual address space following termination of a process, and processing for changing a page, the input/output devices perform operation for the address conversion tables in response to a request from the computer and notifies the computer of permission of the page operation, and, when the permission for the page operation is obtained from all the input/output devices, the computer performs operation for the address conversion table and performs page operation.

Abstract: A device, method, and system for switching library managers of a data library while maintaining data library storage devices online. A library manager accepts and executes data transaction commands for access to data residing on the storage devices of the data library. A transition manager module receives a directive to transition library management functions from a first library manager to a second library manager. The transition manager module stops the first library manager from accepting new data transaction commands while maintaining the storage devices online. The first library manager may execute previously accepted data transaction commands. The transition manager module suspends the library management functions of the first library manager and activates the library management functions of the second library manager. The storage devices of the data library may complete data transaction commands throughout the library manager transition.

Abstract: A mechanism for broadcasting instructions/data to a plurality of processors in a multiprocessor device via aliasing is provided. In order to broadcast data to a plurality of processors, a control processor writes to the registers that store the identifiers of the processors and sets two or more of these registers to a same value. The control processor may write the desired data/instructions to be broadcast to a portion of memory corresponding to the starting address associated with the processor identifier of the two or more processors. When the two or more processors look for a starting address of their local store from which to read the two or more processors will identify the same starting address, essentially aliasing the memory region. The two or more processors will read the instructions/data from the same aliased memory region starting at the identified starting address and process the same instructions/data.

Abstract: A portable electronic device includes a processing device, a memory operatively coupled to said processing device, said memory comprising a plurality of blocks, wherein at least one block of the plurality of blocks may be powered independent of other blocks of the plurality of blocks, and a logic circuit operative to dynamically adjust a demand page buffer size within the memory and utilized by the processor, thereby permitting a corresponding adjustment of a number of powered memory blocks within the memory.

Abstract: Electrical interfaces, addressing schemes, and command protocols allow for communications with memory modules in computing devices such as imaging and printing devices. Memory modules may be assigned an address through a set of discrete voltages. One, multiple, or all of the memory modules may be addressed with a single command, which may be an increment counter command, a write command, or a punch out bit field. The status of the memory modules may be determined by sampling a single signal that may be at a low, high, or intermediate voltage level.

Abstract: A performance monitoring device and method are disclosed. The device monitors performance events of a processor. A counter is adjusted in response to the occurrence of a particular performance event. The counter can be associated with a particular instruction address range, or a data address range, so that the counter is adjusted only when the performance event occurs at the instruction address range or the data address range. Accordingly, the information stored in the counter can be analyzed to determine if a particular instruction address range or data address range results in a particular performance event. Multiple counters, each associated with a different performance event, instruction address range, or data address range, can be employed to allow for a detailed analysis of which portions of a program lead to particular performance events.

Abstract: An apparatus for setting an enclosure address in a computer system having a plurality of enclosures includes at least one enclosure address control device including input means for changing the enclosure address of an associated enclosure of the plurality of enclosures, a display device for indicating the enclosure address assigned to the associated enclosure, a controller for receiving an enclosure address change input from the input means and a logic device for resetting devices within the associated enclosure. The apparatus further includes a register device for receiving the enclosure address from the controller a predetermined period of time after the controller receives the enclosure address change input from the input means. After the predetermined period of time expires, the controller issues a command to the logic device for resetting the devices within the associated enclosure, to assign the changed enclosure address to the devices.

Abstract: The invention relates to a semi-conductor component test procedure, and a semiconductor component test device (10b), which comprise: a device (43) for generating pseudo-random address values to be applied to corresponding address inputs of a semi-conductor component (2b), in particular a memory component, to be tested.

Abstract: The present invention provides a system and method for inband management of a virtual disk. A novel volume information command, which is a vendor-specific SCSI command, is sent by a client to a storage appliance, in response, generates a data structure containing various path and networking data associated with a vdisk. This data structure is then returned to the requesting client via a SCSI connection. A client may then utilize the returned information for generating snapshots or other data integrity/backup features offered by the storage appliance.

Abstract: The invention relates to a semi-conductor component test procedure, as well as to a semi-conductor component test device with a shift register, which comprises several memory devices from which pseudo-random values (BLA, COL, ROW) to be used for testing a semi-conductor component are able to be tapped and emitted at corresponding outputs of the semi-conductor component test device, whereby the shift register comprises at least one further memory device, from which a further pseudo-random value (VAR) is able to be tapped and whereby a device is provided, with which the further pseudo-random value (VAR) can selectively, if needed, be emitted at at least one corresponding further output of the semi-conductor component test device.

Abstract: A network system having a plurality of processing partitions which includes a network interface unit coupled to a plurality of processing entities is disclosed. The network interface unit includes a plurality of memory access channels. The plurality of memory access channels is virtualized. The network interface unit is shared among the plurality of processing partitions.

Abstract: In an LSI implemented by a DMA chip, a BCC check block performs BCC check of cache data each time the cache data is read. In response to a check result indicating whether or not the check is completed, a CM read block turns on a BCC check bit and a BCC error bit of a data-transfer-end notification. Further, an FCC check block performs FCC check of the cache data. In response to a check result indicating whether or not the check is completed, the CM read block turns on an FCC check bit and an FCC error bit of the data-transfer-end notification. When data transfer is finished, the CM read block sends the data-transfer-end notification to a CPU via a descriptor block.

Abstract: Methods, apparatuses and systems for populating a data structure. The data structure may be established in a memory unit and may have a total number of N slots for entries. In this case, N is defined as an integer representing the total number of slots in the data structure, and N is further expressible as a power of two with an integer exponent x. Entries may then be stored into L slots of the data structure, with L being defined as an integer representing a number of slots that contain entries. To produce an index value, x bits of a binary representation of L may be swapped. A new data entry is then stored into an entry of the data structure represented by the index value.

Abstract: A method and a device for converting a virtual address of a program executed by a processor and provided by a program counter into a physical address in a program memory, the program having been stored in the memory in at least one segment of consecutive addresses. The method includes adding to each address provided by the program counter a number corresponding to the offset between the memory address and the virtual address provided by the program counter, and detecting a possible overflow from the current segment by comparing the obtained physical address with the start and end addresses of the considered segment.

Abstract: A method, computer program product, and distributed data processing system that allows a system image within a multiple system image virtual server to directly expose a portion, or all, of its associated system memory to a shared PCI adapter without having to go through a trusted component, such as a Hypervisor. Specifically, the present invention is directed to a mechanism for sharing conventional PCI I/O adapters, PCI-X I/O Adapters, PCI-Express I/O Adapters, and, in general, any I/O adapter that uses a memory mapped I/O interface for communications.

Abstract: A forwarding device compares a first address from a first coherent input/output (I/O) transaction with an address from at least one processor-issued transaction to determine if an address conflict exists. The forwarding device completes a first processor-issued transaction of the at least one processor-issued transaction if the address conflict exists and rejects the first coherent I/O transaction. The forwarding device holds remaining processor transactions of the at least one processor-issued transaction that have an address conflict with the first address of the first coherent I/O transaction. The forwarding device transmits the first coherent I/O transaction to an external I/O device, waits for the first coherent I/O transaction to return from the external I/O device, and completes the first coherent I/O transaction. The forwarding device releases the remaining processor transactions once the first coherent I/O transaction has been completed.

Abstract: A system that enables creation of URL addresses in which the path information is partially or entirely symbolic. The symbolic path information is maintained even after the physical path information is altered, whereby users do not have to learn or provide constantly changing URL addresses to accommodate changes in the organization and presentation of evolving or changing web sites. To this end, web servers interface with a URL resolution database tool that contains information that enable the conversion of the symbolic path information to physical path information. Alternatively, the conversion from symbolic to physical path information is carried by augmented web browsers which have access to symbolic path information conversion servers located on the Internet at a centrally distributed location, or even locally, so that web servers receive only physical path information.