Abstract: An address converter has a base address register and address mask register for setting the start address and range, respectively, of a transparent mode access permitted area. By using the values of these base address register and address mask register, the address converter converts an address signal (address value) supplied from an external bus master into an address signal within a predetermined range from the start position of the transparent mode access permitted area. A transparency controller executes transparent mode access by using the converted address signal. This makes it possible to connect devices having different address bus widths to an external bus without forming any new external circuit, and to set an arbitrary transparent mode access permitted area.

Abstract: A computer body outputting a predetermined number of address signals A0 to A11 and a plurality of select signals CSO and CSI, generates a memory select signal CS and an additional address signal A12 added to the signals A0 to A11 according to the inputted signals CSO and CSI, and provides the signal CS, signal A12, and signals A0 to AI1 to a 256-megabit SDRAM (memory), so that the computer body can access the corresponding data. The computer body can access the data corresponding to the generated additional address signal A12 and predetermined number of the address signals A0 to A11.

Abstract: A multi-level semiconductor memory device for storing multi-level data having three or more values is implemented by utilizing a nonvolatile memory device for storing 2-valued data. Identification of successive 16-bit data externally applied is performed with external address bit AA [2], and a storage block is selected with external address bit AA [23]. Upper word data LW and lower word data UW are compressed into byte data of 8 bits, respectively, and stored in a memory cell array.

Abstract: A semiconductor memory device, comprising a memory array including a plurality of memory cells capable of storing data of at least 1 bit, includes a data write control section for controlling a data write operation to the plurality of memory cells; an address signal generation section for generating an address signal which represents an address of a prescribed memory cell; a determination section for determining whether or not to write data to the prescribed memory cell and outputting a first write signal; a data register section for storing data represented by the first write signal and outputting a second write signal; and a data write section for writing data to the prescribed memory cell based on the second write signal. The data register section stores the data based on a control signal which is output by the data write control section.

Abstract: A method and apparatus for efficiently storing an effective address (EA) in an effective to real address translation (ERAT) table supporting multiple page sizes by adding PSI fields, based on the number of unique page sizes supported, to each ERAT entry and using one ERAT entry to store an EA for a memory page, regardless of page size, by setting the PSI fields to indicate the page size.

Abstract: A method for managing a content addressable memory (CAM) look-up table using the longest prefix matching (LPM) is provided. The method includes providing a pair of pointers per every band of data having the same prefix in length, wherein one of the pair of pointers stores the address of data having the lowest address in each band of data, and the other pointer of the pair of pointers stores the next higher address of data having the highest address in each band of data; and making a space in which data is to be added in the CAM look-up table by moving data having the addresses stored in the pair of pointers provided per each band of data that has a shorter prefix length than the prefix length of the data to be added, when data is added to the CAM look-up table. According to the method, it is possible to easily and efficiently add new data into the look-up table of the CAM.

Abstract: Methods and/or systems and/or apparatus for improved memory management include different allocation and deallocation strategies for various sizes of objects needing memory allocation during runtime.

Abstract: Systems and methods are provided for searching at least one content addressable memory entry associated with a content addressable memory (CAM). A given content addressable memory entry comprises a plurality of CAM fields. At least one input selector controls access to the plurality of CAM fields, such that retrieval of a subset of the plurality of CAM fields is selectively enabled. A match evaluator compares an enabled subset of CAM fields to a search value.

Abstract: A method of managing memory mapped input output operations to an alternate address space comprising: executing a first instruction directed to a first memory mapped input output alternate address space of a machine associated with a first adapter to allocate a resource associated with the first adapter to a process in accordance with a definition of a z/Architecture; wherein a selected process issues at least one of a load and a store instruction executed in a problem state of the machine to a selected address location of a selected resource. The method further includes ensuring that the selected resource corresponds with the allocated resource and determining that the selected process corresponds with the process to which the resource is allocated.

Abstract: In a single-chip microcomputer including a nonvolatile semiconductor memory device and write, read and erase circuits for performing a write operation, a read operation and an erase operation upon the nonvolatile semiconductor memory device, respectively, a sequencer is connected between the write, read and erase circuits and an interface. The sequencer receives first data via the interface from the exterior to write the first data into the nonvolatile semiconductor memory device, reads the first data from the nonvolatile semiconductor device, compares the first data with second data read via the interface from the exterior thus performing a verification upon the nonvolatile semiconductor memory device, and reads third data from the nonvolatile semiconductor memory device and transmits the third data via the interface to the exterior.

Abstract: A method for addressing dynamic random access memory, with providing a row address and a column address to addressing terminals of the memory, in intervals provided by a timing clock signal, to allow increasing address bus bandwidth without increasing the number of address terminals; the inventive method provides—dividing the row address and/or the column address into parts, and providing the respective parts to the address terminals at a rising, and a falling edge of the timing clock signal.

Abstract: A non-volatile memory system is organized in physical groups of physical memory locations. Each physical group (metablock) is erasable as a unit and can be used to store a logical group of data. A memory management system allows for update of a logical group of data by allocating a metablock dedicated to recording the update data of the logical group. The update metablock records update data in the order received and has no restriction on whether the recording is in the correct logical order as originally stored (sequential) or not (chaotic). Eventually the update metablock is closed to further recording. One of several processes will take place, but will ultimately end up with a fully filled metablock in the correct order which replaces the original metablock. In the chaotic case, directory data is maintained in the non-volatile memory in a manner that is conducive to frequent updates. The system supports multiple logical groups being updated concurrently.

Abstract: A data transmission device is used to forward data that have been received from a first device, and are intended for a second device, to the second device. The data transmission device described has a whole series of characteristics that allow the data that are to be transmitted to be transmitted very easily very quickly and which confer additional functions on the data transmission device.

Abstract: A system for instruction memory storage and processing in a computing device having a processor, the system is based on backwards branch control information and comprises a dynamic loop buffer (DLB) which is a tagless array of data organized as a direct-mapped structure; a DLB controller having a primary memory unit partitioned into a plurality of banks for controlling the state of the instruction memory system and accepting a program counter address as an input, the DLB controller outputs distinct signals. The system further comprises an address register located in the memory of the computing device, it is a staging register for the program counter address and an instruction fetch process that takes two cycles of the processor clock; and a bank select unit for serving as a program counter address decoder to accept the program counter address and to output a bank enable signal for selecting a bank in a primary memory unit, and a decoded address for access within the selected bank.

Abstract: Client software stores an identifier corresponding to memory configuration data of interest and causes a software interrupt that requests a memory configuration read function. An interrupt read function handler then reads the data of interest responsive to the identifier and returns the data of interest. The client software may include, for example, BIOS firmware or application software executing in real or protected mode. The memory configuration information may be stored in a hidden I/O or MMIO register device. In such an embodiment, the interrupt handler may enable access to the hidden I/O or MMIO register device prior to reading the data of interest and disable access to the hidden I/O or MMIO register device afterwards.

Abstract: A system for transmitting real-time data between an asynchronous network (104) and a synchronous network (106) is disclosed. A method (100) may include an ingress path (102) for transmitting data from an asynchronous system (104) to a synchronous system (106), and an egress path (108) for transmitting data from a synchronous system (106) to an asynchronous system (104). An ingress path (102) may include a packet receiver (110) and write to synchronous system (112) steps. An egress path (108) may include read from synchronous system (114), packetizer (116), and packet transmitter (118) steps.

Abstract: A gateway using multiple NAT tables to translate network addresses (e.g., Internet Protocol Addresses). The gateway may comprise a service selection gateway connecting remote systems to service domains. The gateway translates local addresses of remote systems to external addresses, and vice versa. The external addresses (bound to the respective local addresses) may be provided by the service domains. The NAT information is partitioned according to service domains such that the external addresses related to the same service domain are stored in the same NAT table. If there is no overlap of external addresses provided by two service domains, the two service domains may share the same NAT table. Due to the partitioning of the NAT information, each table may be limited to be of small size, and the accesses to individual tables may be fast. As a result, a gateway may be able to process and forward packets quickly.

Abstract: The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among address banks that store memory addresses. Non-trial and error algorithms and techniques determine the number of addresses and the number of identical least significant bit (LSB) values that can share the same physical memory location. By sharing physical locations for identical LSB values, circuit hardware on a memory device (including fusible links and compare circuitry) is reduced. Thus, less die area is needed to provide the same degree of redundancy.

Abstract: The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among address banks that store memory addresses. Non-trial and error algorithms and techniques determine the number of addresses and the number of identical least significant bit (LSB) values that can share the same physical memory location. By sharing physical locations for identical LSB values, circuit hardware on a memory device (including fusible links and compare circuitry) is reduced. Thus, less die area is needed to provide the same degree of redundancy.

Abstract: The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among address banks that store memory addresses. Non-trial and error algorithms and techniques determine the number of addresses and the number of identical least significant bit (LSB) values that can share the same physical memory location. By sharing physical locations for identical LSB values, circuit hardware on a memory device (including fusible links and compare circuitry) is reduced. Thus, less die area is needed to provide the same degree of redundancy.

Abstract: Data bus capacitance is reduced by decoupling unaccessed memory circuits from a data bus during data transfers to or from other memory circuits.

Abstract: A method and profiling cache for management of virtual memory includes a set of entries stored in the profiling cache. Each entry of the set of entries includes a page address, a time stamp for the page address and a least recently used (LRU) count; and the LRU count is updated for each access of the page address. Entries in the profiling cache are cast out using the LRU counts. A translation lookaside buffer (TLB) includes a first TLB section for storing a plurality of temporarily pinned entries and a second TLB section for storing a plurality of non-pinned entries. Responsive to a TLB interrupt, an entry is loaded in the second TLB section using a first in first out algorithm for replacing the non-pinned entries. The first TLB portion is periodically updated utilizing identified ones of the set of entries in the profiling cache having oldest time stamps.

Abstract: A semiconductor disk wherein a flash memory into which data is rewritten in block unit is employed as a storage medium, the semiconductor disk including a data memory in which file data are stored, a substitutive memory which substitutes for blocks of errors in the data memory, an error memory in which error information of the data memory are stored, and a memory controller which reads data out of, writes data into and erases data from the data memory, the substitutive memory and the error memory. Since the write errors of the flash memory can be remedied, the service life of the semiconductor disk can be increased.

Abstract: A low-level function which enforces logical partitioning establishes a set of virtual indicator lights for certain physical components, the virtual indicator lights being only data in memory, a separate set of virtual indicator lights corresponding to each respective partition. Processes running in a partition can switch and sense the virtual indicator lights corresponding to the partition, but have no direct capability to either switch or to sense the virtual lights of any other partition. The low-level enforcement function alone can switch the state of the physical indicator light, which is generally the logical OR of the virtual indicator lights of the different partitions.

Abstract: Isolated memory is implemented by controlling changes to address translation maps. Control over the maps can be exercised in such a way that no virtual address referring to an isolated page is exposed to any untrusted process. Requests to edit an entry in a map are evaluated to ensure that the edit will not cause the map to point to isolated memory. Requests to change which map is active are evaluated to ensure that the map to be activated does not point to isolated memory. Preferably, these evaluations are performed by a trusted component in a trusted environment, since isolation of the memory depends on the evaluation component not being compromised. In systems that require all memory access requests to identify their target by virtual address, preventing the address translation maps from pointing to a portion of memory effectively prevents access to that portion of memory, thereby creating an isolated memory.

Abstract: An apparatus and method for transferring signals between timing domains. The apparatus includes a receiver for receiving signals operative in a first timing domain, a decoder for at least partially decoding the signals to generate at least one decoded signal, and an output timing register for outputting the at least one decoded signal in a second timing domain. The signals transferred from the first timing domain to the second timing domain may include, for example, command and/or address signals. The first and second timing domains need not have any predetermined phase relationship. By at least partially decoding the signals during the transfer between the first and the second timing domains, the latency introduced by the timing domain transfer is employed for a useful purpose.

Abstract: A virtual volume module in a host system provides virtual volume view to user-level and system-level applications executing on the host system. The virtual volume module maps I/O from the applications which are directed to a virtual volume to a first physical volume in a first storage system. When necessary, the virtual volume module can map application I/O's to a second volume in a second storage system. The second storage system replicates data in the first storage system, so that when re-mapping occurs it is transparent to the applications running on the host system.

Abstract: The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among address banks that store memory addresses. Non-trial and error algorithms and techniques determine the number of addresses and the number of identical least significant bit (LSB) values that can share the same physical memory location. By sharing physical locations for identical LSB values, circuit hardware on a memory device (including fusible links and compare circuitry) is reduced. Thus, less die area is needed to provide the same degree of redundancy.

Abstract: A surface computer includes an address generator for generating an address for adjusting surface region data concerning at least a storage region and a concurrent computer, provided at a subsequent stage of the address generator, having a plurality of unit computers.

Abstract: A data-driven type information processing apparatus includes at least a paired data generating unit, a memory control unit, and data memory. The memory control unit includes a pipeline register receiving a data packet output from the paired data generating unit, including a page address, a set value for setting an effective bit and data, and an address generating unit for generating an address for accessing the data memory by retrieving effective data from the data included in the data packet based on the set value and attaching the page address included in the data packet to the retrieved effective data.

Abstract: A system includes a peripheral device and an expander having interfaces to couple to one or more peripheral devices and an expander. The expander has a storage to store entries containing routing information used to route a request received by the expander to one of the interfaces, wherein each interface is allocated to a respective set of routing information entries. Mapping logic remaps unused routing information of one of the interfaces to one or more other interfaces to expand capacity of the one or more other interfaces.

Abstract: A translation look-aside buffer (TLB) capable of reducing power consumption and improving performance of a memory is provided. The fully-associative TLB which converts a virtual address into a physical address, comprises a first TLB having a plurality of banks; a second TLB having a plurality of entries, each of which having one virtual page number and 2N physical page numbers, wherein N is a natural number; and a selection circuit for outputting an output signal of the first TLB to the second TLB in response to a selection signal, wherein each bank of the first TLB has a plurality of entries, each of which has one virtual page number and one physical page number. The size of a page indicated by a virtual page number of the first TLB is different from the size of a page indicated by a virtual page number of the second TLB.

Abstract: A number of methods and systems for efficiently storing defective-memory-location tables. A asymmetrical-distortion-model vector quantization method and a run-length quantization method for compressing a defective-memory-location bit map that identifies defective memory locations within a memory are provided. In addition, because various different compression/decompression methods may be suitable for different types of defect distributions within a memory, a method is provided to select the most appropriate compression/decompression method from among a number of compression/decompression methods as most appropriate for a particular defect probability distribution. Finally, bit-map compression and the figure-of-merit metric for selecting an appropriate compression technique may enable global optimization of error-correcting codes and defective memory-location identification.

Abstract: A configurable address generator includes addressing sequence circuitry such as a set of counters. A set of comparators is also preferably included in the configurable address generator in order to detect different addressing conditions (e.g., full, empty, etc.). Coupled to these components is a plurality of programmable bits that allows the address generator to be configured to meet a number of different design requirements. For example, the configurable address generator can be configured as a stack pointer; it can also be configured to provide address generation for FIFO and MAC-based filter circuits, etc.

Abstract: In a system, device, and method for controlling access to a memory, a memory interface device is used to coordinate access to a memory device by a number of host applications. The memory interface device is situated between the number of host applications and the memory device. The memory interface device received memory access requests from the number of host applications, interacts with the memory device for servicing the memory access requests, and provides result/status information to the number of host applications. The memory interface device maintains a separate context for each memory access request in order to correlate each memory access request with the host application that issued the memory access request and the result/status information generated for the memory access request.

Abstract: This invention relates to the emulation processing method of a storage device and the storage device for accessing storage medium from a host that has a different sector size, and where alternate processing is performed in the sector unit of storage medium even when there is a writing error when updating the disk. In a system where a second sector size of a host is smaller than a first sector size of the storage medium, data that are staged in a buffer according to a request from the host is rewritten using write data, and then staged sector data or the rewritten sector data are saved in an alternate area and the storage medium is updated with the rewritten sector data. Since the sector data before updating is saved beforehand, it is possible to perform alternate processing using the sector unit of the storage medium.

Abstract: Methods, computer systems, and devices provide for the use of pointers of various formats stored in a ROM image that is initially stored in an on-board ROM device of a computer system. The pointers may be stored in either a first format such as segment:offset or a second format such as flat 32-bit. The flat 32-bit format allows the ROM device and ROM image to exceed one megabyte in size, which permits many modules to be included to allow the ROM image to provide support for a full spectrum of hardware of the computer system. The segment:offset format allows backward compatibility with legacy type systems and software. The format of the pointers is determined so that first format pointers are converted to second format pointers for use in accessing modules of the ROM image. Pointers already stored in the second format are utilized as is to access the modules.

Abstract: A system and a method are provided for improving memory management in a multiprocessor system. A direct memory access (DMA) operation is set up for a first processor. A DMA effective address is translated to a virtual address. The virtual address is translated to a physical address, which is used to access a memory hierarchy of the multiprocessor system.

Abstract: A system for the encryption and decryption of data employing dual ported RAM to accelerate data processing operations during the computation of the encryption and decryption algorithm. The system includes logic to track data changes in the dual ported memory for fast table initialization; a means to accelerate operations by performing read/write operations in different iterations of the algorithm to separate ports on the dual ported RAM in the same clock cycle; and a means to resolve data manipulation conflicts between out of order read/write operations so that the system correctly computes the desired algorithm.

Abstract: Memory and processing required for managing virtual memory segments is reduced by overloading the existing page table entries in a virtual memory page table to encode virtual memory segmentation data. Therefore, no additional data structures are required for virtual memory segment management. Virtual memory segmentation information is stored in the actual page table entries, using bits that are reserved as unused for the given computer architecture to identify the virtual memory segment management information.

Abstract: A virtual mode virtual memory manager method and apparatus are provided. Mechanisms are provided for allowing a virtual memory manager to operate in virtual mode utilizing virtual addresses for all of its own data structures, allowing for physical discontinuity of the physical memory backing those data structures. First order virtual memory manager metadata is included for resolving system wide virtual memory page faults. Second order virtual memory manager metadata is provided to resolve faults on the first order virtual memory manager metadata. The second order virtual memory manager metadata is associated with pinned entries in a page table and thus, faults on the second order virtual memory manager metadata cannot occur.

Abstract: An address generator is provided for generating addresses for testing an addressable circuit. The address generator can include a base address register for buffer-storing a base address. The base address register can be assigned an associated offset register group having a plurality of offset registers for buffer-storing relative address values. Further, the address generator can include a first multiplexer circuit which is dependent on a base register selection control signal, switches through an address buffer-stored in the base address register to a first input of an addition circuit and to an address bus, which is connected to the circuit to be tested. A second multiplexer circuit can be dependent on the base register selection control signal, through-connects the offset register group associated with the through-connected base address register to a third multiplexer circuit, which is dependent on an offset register selection control signal.

Abstract: The address of a data packet to be transferred from a memory to a network interface card within a direct memory access (DMA) is checked. First of all, the address of a descriptor corresponding to the data packet is read from the memory, wherein the descriptor contains information of the address of the data packet. Then, whether the address of the descriptor complies with a certain rule is determined. If the address of the descriptor does not comply with the certain rule, an interrupt signal is asserted to a processor to perform a corresponding interrupt service in order to re-read the address of the descriptor.

Abstract: A data storage system and method for providing consistent data to multiple clients based on data modification information as existing data is updated and new data is written to the system. The information indicates the modification status of each data block and identifies which data blocks have been modified during a certain time interval. The clients may query and update the modification information by submitting requests through a request processor. The data modification information includes an Altered Block Map that indicates block modification status and a Toggle Block Map that identifies which blocks have been modified. The system further includes a Modification Counter a Pending Reset Counter for improved recognition and handling of the modified data.

Abstract: A host computer has a file with a subroutine required for operation of an application on a target. The file is dynamically loaded to memory of the target, whereby the file has an entry point at a dynamically-determined location. Data representative of the address of the entry point is stored in memory at a predetermined location. The application is then run on the target, causing the application to determine the entry point, thereby accessing the subroutine and allowing the subroutine to run.

Abstract: Memory interleaving includes providing a non-power of two number of channels in a computing system and interleaving memory access among the channels.

Abstract: A method and system of managing virtual memory for a flash-memory system. Logical blocks in a buffer are used to store data copied from a physical block in a flash-memory. An operating system searches data in the buffer first. If the data is in the buffer, it is accessed. If not, the operating system searches for the data in the flash memory, meanwhile writing a logical block having a dirty flag back to a logical block.

Abstract: Multiple applications enable communications I/O operation and an I/O interface operations simultaneously at a low cost. The process A requests an OS to allocate an area where a request to an I/O device is put. The OS also allocates an unused context ID for the I/O device to the process A, maps a memory page corresponding to the context ID as an address for accessing the pending register for the process A, and stores a pointer (a physical address) to a request storing area of the process A into an embedded memory in the I/O device. The process A writes contents of requests in its own request storing area, and the OS notifies the I/O device that there is an unprocessed request by use of the address for the pending register. The I/O device reads out the contents of the request storing area by a DMA engine, and realizes the request.

Abstract: When a first computer instructs transfer of data from the first computer to a second computer, a transmitting device in the first computer instructs the second computer to perform pre-read of a translation look-aside buffer, which contains a transfer-destination virtual address, in concurrence with read-out of initial data or of initial data for which the transfer-destination address has exceeded a page boundary, thereby causing virtual-address translation information to be pre-registered in a translation look-aside buffer from an address translation table of the second computer.

Abstract: Memory management in a data processing system (10) is achieved by using one or more timing bits (54) to specify a timing parameter of a memory (18, 19, 34). To implement this in some embodiments of the present invention, a memory array (32, 33, 42) is multiple-mapped in the physical memory map (70) of processor (12) and the address bits (54) associated with the multiple-mapping are used to directly control timing parameters of the memory arrays (32, 33, 42). This allows for flexible timing specifications to be derived quickly on an access by access basis without requiring any additional control storage overhead.