Abstract: A flash memory device includes an array of memory cells for storing data pages, one or more buffers for retrieving the data pages and a logic mechanism that, responsive to a plurality of commands, transfers the data pages between the buffers and a host. Each command subsequent to a first command instructs retrieval of a data page whose address either precedes, or exceeds by more than 1, the address of the data page retrieved by the immediately preceding command, and at least one command does not explicitly specify the address of its retrieved data page. Another similar flash memory device uses two buffers to implement cache reads of data pages whose addresses are specified arbitrarily in the commands subsequent to the first command.

Abstract: A circuit is provided for performing interleaving and deinterleaving functions in a digital communication system. The circuit includes a single-port memory that reads first data units from a first interleaved sequence of address locations to generate a first data stream and that writes second data units from a second data stream to the address locations. A first address generator module communicates with the single-port memory and generates a first interleaved sequence of addresses that correspond to the address locations and correspond to one of an interleaving function and deinterleaving function between the first data stream and the second data stream.

Abstract: In a KVM system, a system provides for USB devices to be accessed by target computers. A KVM switch connects a client with a target server via a network, the client computer having at least one device attached thereto. A second mechanism connects to a USB port of the target and communicates with the target using a USB protocol. A client mechanism communicates with the second mechanism via the network. A virtual media mechanism enables the target server to access the USB device attached to the client.

Abstract: Memory addresses for a data stream are generated by a stream parameter generator that calculates a set of stream parameters for each of a number of memory access patterns and a regional address generator that calculates a sequence of addresses of a memory access pattern from a corresponding set of stream parameters. The stream parameters, which may include START_ADDRESS, STRIDE, SKIP and SPAN values for example, are updated in accordance with an update( ) function. The update( ) function, which may be defined by a user, defines how stream parameters change from one memory access pattern to the next. In one application, the update( ) function describes how the position, shape and/or size of a region of interest in an image changes or is expected to change.

Abstract: In one embodiment, the invention provides an apparatus for caching data in a network, with the apparatus including a proxy cache configured to receive request for an object from a client and to fetch data blocks from a server. The proxy cache may be configured to cache the data blocks in a hierarchical relationship within the object. The object may be, for example, a data file or a directory. The data blocks that are cached in the proxy cache define an active data set which is based upon a request from a client.

Abstract: The present invention provides a system and method for implementation and use of a shared memory. The shared memory may be accessed both independently and asynchronously by one or more processes at corresponding nodes, allowing data to be streamed to multiple processes and nodes without regard to synchronization of the plurality of processes. The various nodes may be adaptive computing nodes, kernel or controller nodes, or one or more host processor nodes. The present invention maintains memory integrity, not allowing memory overruns, underruns, or deadlocks. The present invention also provides for “push back” after a memory read, for applications in which it is desirable to “unread” some elements previously read from the memory.

Abstract: A memory card comprises a memory controller connected to a non-volatile memory module. The memory controller comprises a first circuit adapted to convert a first external address into a first internal address using a program stored in an internal memory. The memory controller further comprises a hardware accelerator adapted to generate a second internal address based on the first internal and external addresses.

Abstract: A method, system, computer system, and computer-readable medium that enable a secondary host that is not the file system host to create a backup of a clone file set that shares at least one data block on a storage device with an active file set. Start and end locations are identified for a set of contiguous storage locations (referred to as a “chunk”) on the storage device. Physical location information is obtained for each portion of a file contained in the chunk. The start and end locations and physical location information for portions of files contained in the chunk are provided to the secondary host, which sequentially reads data from the set of contiguous storage locations and constructs a copy of the file(s) making up the clone file set. The file(s) are written by the secondary host to a storage device to create a backup of the clone file set.

Abstract: Arbitrary patterns of address locations of digital data can be efficiently read from a memory of a signal processor. For example, a first memory address generator receives a first memory command signal from a first communication register to retrieve a first set of data from memory according to a look up table of memory addresses. The first memory access generator reads the look up table of memory addresses, which contain a second set of memory commands and reroutes the second set of commands to a bypass register. In turn, the second set of memory commands stored at the bypass register are read by a second memory address generator which retrieves a second set of data from memory according to the second set of memory command signals read out of memory by the first memory address generator.

Abstract: A digital signal processor is adapted to a working RAM, which is capable of storing a plurality of data in a rewritable manner and whose storage area is divided into a plurality of sub-areas that are designated by addresses in read/write operations, wherein an operation circuit performs calculations on the data of the working RAM in accordance with a program, and wherein upon detection of a non-access event in which the program does not need to access the working RAM, a write circuit compulsorily writes ‘0’ into the working RAM with regard to each of the prescribed addresses of the prescribed sub-areas subjected to initialization, which are designated by address data. Thus, it is possible to actualize the selective initialization on the prescribed sub-areas within the working RAM without increasing the scale of the peripheral circuitry, without requiring complicated controls, and without increasing the overall processing time therefor.

Abstract: Exemplary systems and methods include pre-fetching data in response to a read cache hit. Various exemplary methods include priming a read cache with initial data, and triggering a read pre-fetch operation in response to a read cache hit upon the initial data in the read cache. Another exemplary implementation includes a storage device having a read cache and a trigger module that causes a pre-fetch of data from a mass storage medium in response to a read cache hit upon data in the read cache.

Abstract: Various embodiments of the present invention include methods for determining nanowire addressing schemes and include microscale/nanoscale electronic devices that incorporate the nanowire addressing schemes for reliably addressing nanowire-junctions within nanowire crossbars. The addressing schemes allow for change in the resistance state, or other physical or electronic state, of a selected nanowire-crossbar junction without changing the resistance state, or other physical or electronic state, of the remaining nanowire-crossbar junctions, and without destruction of either the selected nanowire-crossbar junction or the remaining, non-selected nanowire-crossbar junctions. Additional embodiments of the present invention include nanoscale memory arrays and other nanoscale electronic devices that incorporate the nanowire-addressing-scheme embodiments of the present invention.

Abstract: Briefly, an apparatus, a method and a wireless communication device are provided. The wireless communication device includes a turbo encoder to generate an encoded data block and a transmitter to transmit a data sub-block of the encoded data block in a time slot of a physical channel of the wireless communication system. The encoded data block includes real time data.

Abstract: A pseudo SRAM which can perform read and write operations of data in a continuous burst mode in such a manner that it continuously generates burst row and column address signals, which gradually rise, based on external address signals that have already been received until new external address signals are received.

Abstract: A method and system for storage address re-mapping is disclosed. The method includes allocating logical addresses in blocks of clusters and re-mapping logical addresses into storage address space, where short runs of data dispersed in logical address space are mapped in a contiguous manner into blocks in storage address space. Valid data is flushed from blocks having both valid and obsolete data to make new blocks available for receiving data when an available number of new blocks falls below a desired threshold. The system includes a host file system, processor executable instructions residing on a host separately from the host file system or residing on a flash memory device such as an embedded solid state disk, or a backend memory manager of the flash memory device that is configured to map data from a logical address space to complete blocks in storage address space in a contiguous manner.

Abstract: The invention discloses a method for loading data from a disk. The method may comprise comparing a current sequence of disk requests to data indicative of a previous disk request sequence. Responsive to detecting a match between the current disk sequence and the previous disk I/O sequence, a copy of data blocks accessed during the current disk sequence may be stored in a contiguous portion of the disk. Responsive to a subsequent request for data in the disk sequence, the request may be mapped to and serviced from the sequential portion of the disk: The continuous portion of the disk to which the data is copied may be on a different partition of the disk than a disk partition on which the original data is stored. A sequence of disk accesses may be recorded. Responsive to retrieving data from the continuous portion, additional data from the contiguous portion of the disk may be prefetched and may be cached in a buffer.

Abstract: A hierarchical memory access control distinguishes between blocks of data that are known to be sequentially accessed, and the contents of each block, which may or may not be sequentially accessed. If the contents of a block are provided in a sequential manner within the block, but the sequence does not correspond to a higher-level sequence, due to a non-zero offset in the start of the sequence within the block, the memory access control is configured to optimize the use of available memory by signaling when the within-block sequence corresponds to the higher-level sequence. While the within-block sequence differs from the higher-level sequence, access to the buffer is limited to the higher-level partitioning of the buffer. When the within-block sequence corresponds to the higher-level sequence, access to the buffer is provided at the within-block partitioning of the buffer.

Abstract: There are provided a buffer circuit buffers data between a synchronous circuit and an asynchronous circuit, and a control method therefor. There are also provided an interface circuit that controls data transfer between a synchronous memory circuit and the asynchronous circuit, and a control method therefor, which are used in the buffer circuit and the control method therefor. A data buffer circuit that is interposed between an image processing system and a main system includes a one-port RAM, a control signal generating section, an subsequent cycle address generating section, and a first selector. The first selector selectively outputs the present cycle address to an address of the one-port RAM when an access to the one-port RAM is a write access, and selectively outputs the subsequent cycle address to the address of the one-port RAM when the access to the one-port RAM is a read access.

Abstract: A technique for generating a list of all N-bit unsigned binary numbers by starting with an initial number less than some power of 2, successively multiplying the number by that power of 2 and adding the largest non-negative number less than that power of 2 such that the new number is not a duplicate of any of those already generated, and using the resulting lists to generate efficient hashing and serial decoding hardware and software.

Abstract: A data storing method for a storage apparatus. The storage apparatus has a memory block, which includes a first terminal and a second terminal. The data storing method includes receiving a data set; selecting a first writing direction or a second writing direction to be a preferred writing direction, wherein when the first writing direction is selected to be the preferred writing direction, the first terminal is a starting point corresponding to the first writing direction, and when the second writing direction is selected to be the preferred writing direction, the second terminal is a starting point corresponding to the second writing direction; and writing the data set into the memory block according to the selected writing direction.

Abstract: Typical cache architecture provides a single cache way prediction memory for use in predicting a cache way for both sequential and non-sequential instructions contained within a program stream. Unfortunately, one of the drawbacks of the prior art cache way prediction scheme lies in its efficiency when dealing with instructions that vary the PC in a non-sequential manner, such as branch instructions including jump instructions. To facilitate caching of non-sequential instructions an additional cache way prediction memory is provided to deal with the non-sequential instructions. Thus during program execution a decision circuit determines whether to use a sequential cache way prediction array or a non sequential cache way prediction array in dependence upon the type of instruction. Advantageously the improved cache way prediction scheme provides an increased cache hit percentage when used with non-sequential instructions.

Abstract: The present invention comprises a data access pattern interface that allows software to specify one or more data access patterns such as stream access patterns, pointer-chasing patterns and producer-consumer patterns. Software detects a data access pattern for a memory region and passes the data access pattern information to hardware via proper data access pattern instructions defined in the data access pattern interface. Hardware maintains the data access pattern information properly when the data access pattern instructions are executed. Hardware can then use the data access pattern information to dynamically detect data access patterns for a memory region throughout the program execution, and voluntarily invoke appropriate memory and cache operations such as pre-fetch, pre-send, acquire-ownership and release-ownership.

Abstract: Systems and methods using an excitement protocol enable prediction of which blocks of a resource to prefetch and store in memory. The system maintains a set of excitement values corresponding to the resource being accessed. The system also maintains a threshold. As blocks of the resource are requested, the system updates the set of excitement values. The system compares the excitement level to the threshold to determine whether to prefetch the corresponding resource block.

Abstract: Memory addresses for a data stream are generated by a stream parameter generator that calculates a set of stream parameters for each of a number of memory access patterns and a regional address generator that calculates a sequence of addresses of a memory access pattern from a corresponding set of stream parameters. The stream parameters, which may include START_ADDRESS, STRIDE, SKIP and SPAN values for example, are updated in accordance with an update( ) function. The update( ) function, which may be defined by a user, defines how stream parameters change from one memory access pattern to the next. In one application, the update( ) function describes how the position, shape and/or size of a region of interest in an image changes or is expected to change.

Abstract: A system to locate a storage device. The system receives a request for a data item stored on a first and second storage device. The request includes a data identifier for the data item. Next, the system generates a start value and a step value based on the data identifier. Next, the system locates the first storage device utilizing the start value and identifies the first storage device is unavailable. Next, the system locates a second storage device utilizing a backup value that is generated based on the step value and the start value.

Abstract: Interleaver for iterative decoder. A memory management scheme allows for single plane/single port memory devices to be used by the interleaver. The design is adaptable to soft-in soft-out (SISO) decoders that perform iterative decoding. The interleaver may be implemented within communication devices that implement two distinct SISOs that operate cooperatively or within communication devices that employ a single SISO (in a recycled embodiment) that functionally performs the analogous decoding operations that would be performed by the two distinct SISO implementation. The use of single plane/single port memory devices by the interleaver allows for a great deal of savings from many perspectives: the sizes of the required interleaver memory and the interleaver pattern memory are both cut in half using this approach, and a cost savings may also be realized, in that, cheaper, slower memories may be used since each respective interleaver memory is read only every other cycle.

Abstract: Techniques are provided for synchronously transmitting data in parallel from an external memory device to a destination circuit using a sequential read mode. The memory device includes an address counter. The address counter generates sequential read addresses for the data bits stored in the memory device. The destination circuit generates a clock signal that controls the address counter. The destination circuit can also transmit a start address to the memory device. The address counter sequentially generates a new read address in response to transitions in the clock signal beginning with the start address. Data bits are transferred in parallel from the memory device to the destination circuit.

Abstract: A distributed data cache includes a number of cache memory units or register files each having a number of cache lines. Data buses are connected with the cache memory units. Each data bus is connected with a different cache line from each cache memory unit. A number of data address generators are connected with a memory unit and the data buses. The data address generators retrieve data values from the memory unit and communicate the data values to the data buses without latency. The data address generators are adapted to simultaneously communicate each of the data values to a different data bus without latency. The cache memory units are adapted to simultaneously load data values from the data buses, with each data value loaded into a different cache line without latency.

Abstract: Arbitrary patterns of address locations of digital data can be efficiently read from a memory of a signal processor. For example, a first memory address generator receives a first memory command signal from a first communication register to retrieve a first set of data from memory according to a look up table of memory addresses. The first memory access generator reads the look up table of memory addresses, which contain a second set of memory commands and reroutes the second set of commands to a bypass register. In turn, the second set of memory commands stored at the bypass register are read by a second memory address generator which retrieves a second set of data from memory according to the second set of memory command signals read out of memory by the first memory address generator.

Abstract: A memory includes an address bus, address counter, address decoder, comparator, and control circuit. During a data read or write cycle, the address bus receives an external address, the address counter generates an internal address, which the address decoder decodes, and the comparator compares the external address to a value. Based on the relationship between the external address and the value, the comparator enables or disables the data transfer. For example, such a memory can terminate a page-mode read/write cycle by determining when the current external column address is no longer equal to the current internal column address. This allows the system to terminate the cycle after a predetermined number of data transfers by setting the external column address to a value that does not equal the internal column address.

Abstract: There is disclosed a technique for accessing a register file which comprises defining a first register address as a plurality of bits and using said first register address to access said register file generating a second register address by using a sequence of said plurality of bits with at least one of said plurality of bits supplied via a unitary operator, the unitary operator being effective to selectively alter the logical value of said bit depending on its logical value in the first register address, and using said second register address to access said register file. A computer system for carrying out such a technique is also enclosed.

Abstract: A method of detecting sequential data transfer requests, includes determining whether a first data transfer request crosses a boundary address, and, if it does, determining if the first data transfer request may be indicated as combinable with subsequent data transfer requests. The method may also include determining whether a previous data transfer request has been indicated as combinable, and if it has been indicated as combinable, determining that a new data transfer request is addressed adjacent to the previous data transfer request.

Abstract: In a method and system for cycling through addresses of a memory device, a respective bit pattern comprised of a predetermined number of bits is generated for each address. The respective bit pattern for each of the addresses is cycled through with a transition of less than the predetermined number of bits for sequencing to each subsequent address. For example, the respective bit pattern for each of the addresses is cycled through in a gray code sequence. By limiting the number of transitions in the address bits, charge gain failure of a flash memory device is minimized and even may be eliminated.

Abstract: An apparatus and method for speeding up access time of a large register file with wrap capability are provided. With the apparatus and method, the 2:1 multiplexers in conventional register file systems are eliminated from the circuit configuration and instead, additional primary multiplexers are provided for half of the addresses, e.g., the first four sub-arrays of the register file for which the wrap capability is needed. These additional primary multiplexers receive the read address and a shifted read word line signal. The other primary multiplexer receives the read address and an unshifted read word line signal. The outputs from the shifted and non-shifted primary multiplexers are provided to a set of secondary multiplexers which multiplex bits from the outputs of the shifted and non-shifted primary multiplexers to generate the read addresses to be used by the multiple read/write register file system.

Abstract: A processor includes a trace cache memory coupled to a trace generator. The trace generator may be configured to generate a plurality of traces each including one or more operations that may be decoded from one or more instructions. Each of the operations may be associated with a respective address. The trace cache memory is coupled to the trace generator and includes a plurality of entries each configured to store one of the traces. The trace generator may be further configured to restrict each of the traces to include only operations having respective addresses that fall within one or more predetermined ranges of contiguous addresses.

Abstract: A system is described which uses a burst access memory and a memory controller to anticipate the memory address to be used in future data read operations as requested by a microprocessor. Either the memory controller or the memory device initiates a burst read operation starting at a memory address generated thereby. The microprocessor can, therefore, wait to initiate a data read without suffering a time delay.

Abstract: Apparatus and methods for addressing predicting useful in high-performance computing systems. The present invention provides novel correlation prediction tables. In one embodiment, correlation prediction tables of the present invention contain an entered key for each successor value entered into the correlation table. In a second embodiment, correlation prediction tables of the present invention utilize address offsets for both the entered keys and entered successor values.

Abstract: Embodiments of the invention provide an automatic address generator that generates an address sequence directly using counters that count between predefined start and stop values in accordance with a predefined modes of indexing. The counters support slipping when counting to support convolutional filters in one-dimension (1D) and two-dimension (2D). For 2D indexing, a first counter indexes in the X direction and a second counter indexes in the Y direction in memory. The values from the first and second counter are combined with an offset value to form an address directly to memory.

Abstract: The present invention provides a system and method for implementation and use of a shared memory. The shared memory may be accessed both independently and asynchronously by one or more processes at corresponding nodes, allowing data to be streamed to multiple processes and nodes without regard to synchronization of the plurality of processes. The various nodes may be adaptive computing nodes, kernel or controller nodes, or one or more host processor nodes. The present invention maintains memory integrity, not allowing memory overruns, underruns, or deadlocks. The present invention also provides for “push back” after a memory read, for applications in which it is desirable to “unread” some elements previously read from the memory.

Abstract: A method of carrying out a data fetch operation for a data-parallel processor such as a SIMD processor is described. The operation is specifically involving the use of a plurality of non-sequential data addresses. The method comprises constructing a linear address vector from the non-sequential addresses, and using the address vector in a block fetch command to a data store.

Abstract: In one embodiment, the invention provides an apparatus for caching data in a network, with the apparatus including a proxy cache configured to receive request for an object from a client and to fetch data blocks from a server. The proxy cache may be configured to cache the data blocks in a hierarchical relationship within the object. The object may be, for example, a data file or a directory. The data blocks that are cached in the proxy cache define an active data set which is based upon a request from a client.

Abstract: A data controlling unit activates a predetermined number of data terminals according to a mode signal and changes a bus width of external data signal. According to the mode signal, an address controlling unit selects a predetermined number of bits of an internal address signal outputted from a controller and outputs the selected bits as an external address signal. Specifically, the address controlling unit selects upper bits of the internal address signal when the bus width of the external data signal is increased according to the mode signal. Therefore, it is possible to prevent occurrence of an unused external address terminal, enabling the increase in accessible external memory capacity.

Abstract: A memory controller, such as a SDRAM controller, forms a queue of memory access requests to maximize efficient use of the bandwidth of the memory data bus. More specifically, the SDRAM controller pre-calculates the number of data bursts required to retrieve all the required data from the SDRAM, and the starting address for each of the data bursts, and queues the access requests for these data bursts such that the data bursts may be retrieved without incurring the usual read latency for each data burst.

Abstract: A data processing apparatus and method are provided for controlling access to a slave device, the slave device having an address range associated therewith. The apparatus comprises control storage programmable to define a partition identifying a secure region and a non-secure region in the address range, with the data processing apparatus supporting a plurality of modes of operation including a secure mode, and the control storage being programmable only by software executing in the secure mode. A master device is arranged to issue an access request onto a bus, the access request identifying a sequence of addresses within the address range and including a control signal indicating whether the access request is a secure access request or a non-secure access request. The secure region is only accessible by a secure access request.

Abstract: According to one embodiment of the invention, an apparatus comprises a high speed memory unit, a memory controller and an external bus interface (EBIF) unit coupled to the memory controller. The EBIF unit, based on a memory request issued by a host device to read a block of data from an external memory device, (i) initiates a burst or page mode read cycle independent of whether the memory request is associated with consecutive memory accesses to the external memory device, (ii) stores the block of data read in the high speed memory unit in response to the burse or page mode read cycle, and (iii) retrieves requested data from the high speed memory unit in response to a subsequent, non-consecutive memory request issued by the host device for data already stored within the high speed memory unit.

Abstract: An apparatus and method for performing data access in accordance with memory access patterns are described. In one embodiment, the method includes the determination, in response to a memory access instruction, of a memory access pattern of data requested by the memory access instruction. Once the memory access pattern is determined, the data requested by the memory access instruction is accessed according to the determined memory access pattern. Finally, once the data is accessed, the data is processed according to the memory access instruction. Accordingly, in this embodiment of the present invention, data is accessed according to memory access patterns including zig-zag patterns scan, Zerotree scan, bit plane extraction, fine granularity scalability or the like.

Abstract: A linear and non-linear object management method and structure. A data structure on a computer-readable medium is used to store linear and non-linear objects in a range of memory of a volume. The data structure includes a contiguous range of memory in which the data objects are stored. A plurality of data objects are stored contiguously in the range of memory and are associated with a first or second list in the range of memory. The plurality of data objects include a first-type of data object having a data field in linear objects are stored and further include a second-type of data object having a data field containing non-linear data objects.

Abstract: Disclosed are a system, a method, and an article of manufacture to provide for configuring an automated data storage library having one or more storage frames that operate with different types of data storage media. The automated data storage library is configured to operate with sequential storage shelf addresses assigned to consecutive storage frames that use the same type of data storage media. The storage frames that operate with different types of data storage media may be physically assembled in any order. The automated data storage library may be expanded by attaching storage frames that operate with different types of data storage media in any order while maintaining sequential storage shelf addresses that span across multiple library frames.

Abstract: A method, apparatus, and system for configuring an address bit in a cache formed on an integrated circuit. The method, apparatus, and system include the ability to configure the address bit as either a tag bit or a set index bit and reconfigure the address bit.

Abstract: The invention comprises a hardware constructed address generator for a circular buffer which can be of any size and be in any position in memory. The address generator calculates both an absolute value and a wrapped value and selects one in accordance with whether the wrapped value falls within the boundaries of the buffer.