Abstract: A method and apparatus for accessing successive memory locations without the need for multiple index register writes and without the need for a wide address bus from the controller into a memory control system. The memory control system includes an index register and a data register. The index register has a connection to the controller and the buffer. The data storage register has a connection to the buffer and to the controller. The index register receives an address to a location in the buffer. Each time the contents of the index register are changed, data associated with the address are automatically written into the data storage register. Each time the data storage register is accessed (read or written), the index register in incremented. The controller is able to read or write unlimited numbers of sequential locations up to the full buffer space, using only a single controller access per byte.

Abstract: The present invention provides, at a lower cost, a highly reliable data reading method and data reading apparatus that can improve backward sequential reading performance. The disk drive is provided with a magnetic disk and a control section having an HDC, a RAM, an MPU controlling the operation of the entire HDD, including control of the HDC, a ROM, and an I/F for connecting to an external host device. The control section executes a backward reading detection step that detects backward reading, a step of receiving a command that reads a block of a first length from a first LBA, a step that reads a block of the first length from the first LBA when backward reading is detected, and a step that pre-fetches a second block from a second LBA smaller than the first LBA; when backward reading is detected, upon completion of the reading of data from the disk, the reading of data predicted to be requested by the next command begins immediately.

Abstract: A format structure for storing retrievably encoded data on a recording medium is disclosed. A start field for indicating the start of a data file is provided. Immediately following the start field there provided an index field for storing indexing data respecting the data file. In the index field a sequence of one or more positions of other start fields leading in one direction from a current position on the medium toward one end of the medium is stored. Immediately following the index field there is a field for storage data, which forms the data file. A method for storing encoded data on a storage medium is also disclosed. The last file stored on the medium is located. The index field of the last stored file is then retrieved. The index field associated therewith is duplicated for later use. The system then moves the storage medium to the end of the last stored file. At the current position of the medium a filemark is inserted.

Abstract: A sequence controller includes a sequencer to which a basic clock is applied. The sequencer sequentially generates at a period of 125 &mgr;sec address signals for reading statements to be executed at a period of 125 &mgr;sec and one block of statements to be executed at a period of 10 msec or one block of statements to be executed at a period of 100 msec. A memory stores the above statements beforehand. The statements are selectively read out of the memory in accordance with the address signals and fed to a decoder. The decoder decodes the statements and generates control signals respectively corresponding to the statements and feeds the control signals to a switch. The switch controls each of a plurality of function registers on the basis of the respective control signal.

Abstract: A buffer access control circuit to access a buffer which is divided into an upper buffer and a lower buffer which are assigned the same address and a memory unit including the buffer access control circuit. The buffer access control circuit includes latch circuits which store data in response to upper and lower buffer access signals, and a first detection circuit which detects whether data latched by the latch circuits match. A modifying circuit inputs data to the first and second latches or inputs inverted data to the first and second latches when one of the upper and lower buffer access signals is generated and the detection circuit detects a match. In this manner, the buffer access control circuit is used to update an address one by one, without the use of a delay circuit when consecutively accessing the upper and lower buffers.

Abstract: A burst length discriminating circuit for use in a synchronous semiconductor memory with a burst mode, which receives the three least significant address signals IA0, IA1 and IA2 of an address, includes an inverter receiving the address signal IA2, a first D-latch for latching and holding the address signal IA0, a second D-latch for latching and holding the address signal IA1, and a third D-latch for latching and holding an output of the inverter. A decoder receives respective outputs of the first to third D-latches for selectively activating a burst length discrimination signal determined by a logical combination of the address signals IA0, IA1 and IA2, but for activating any burst length discrimination signal other than a burst length discrimination signal indicating the full page, when the outputs of all the first to third D-latches are at the high level.

Abstract: A data transfer apparatus is provided with a SRAM, in which storage positions are specified on the basis of the number of times synchronous data is transferred, for holding data in the specified storage positions; and a SRAM control unit having a plurality of counters, for controlling data storage and data reading in/from the SRAM, by generating storage addresses indicating the storage positions on the SRAM 6, and generating read addresses for reading data from the storage positions. Therefore, the number of accesses to a DRAM is reduced, whereby the system performance is improved. Further, the operating clock frequency of the apparatus can be increased without increasing the operating clock of the DRAM.

Abstract: Disclosed is an exclusive control method in an I/O subsystem having an exclusive controller which is provided with an exclusive control table and which permits a host interface to use the I/O device when the I/O device is not used by any other host interface while prohibiting the use when another host interface is using the I/O device.

Abstract: A processor and method of fetching an instruction from a memory are disclosed. According to the method of the present invention, a plurality of target addresses are determined utilizing a plurality of previously fetched instructions, and a sequential address is determined utilizing a last of the plurality of previously fetched instructions. Concurrently with the determination of the target addresses and the sequential address, a select signal specifying one of the plurality of target addresses or the sequential address is generated. The select signal is used to select one of the plurality of target addresses or the sequential address as a memory request address. The memory request address is then transmitted from the processor to the memory so that the memory will supply at least one instruction to the processor. By generating the target addresses and sequential address concurrently with the generation of the selection signal, instruction fetch latency is reduced.

Abstract: An apparatus and method are presented for increasing the throughput within a single-channel of a pipeline microprocessor. Back-to-back pairs of micro instructions are evaluated to determine if they can be combined for execution in parallel. If so, then they are combined and issued for concurrent execution. The apparatus includes a micro instruction queue that buffers and orders micro instructions for sequential execution by the pipeline microprocessor. Within the micro instruction queue, a second micro instruction is ordered to execute immediately following execution of a first micro instruction. Pairing logic is coupled to the micro instruction queue. The pairing logic combines the first and second micro instructions so that the first and second micro instructions are executed in parallel by the pipeline microprocessor.

Abstract: A highly flexible and complex BIST engine provides at-speed access, testing, characterization, and monitoring of on-chip memory arrays, independent of other chip circuitry such as a CPU core. Each BIST engine has a main control block, at least one address generation block having an address local control block and one or more address-data generation blocks, and at least one data generation block having a data local control block and one or more data generation blocks. Each of the local address and data control blocks are programmed independently to define operations that will be performed by the individual address and data generation blocks, respectively. The main control block in turn controls operation of the local address and data control blocks to effect desired testing, accessing, and monitoring of the on-chip memory arrays.

Abstract: A set-associative cache-management method utilizes both parallel reads and single-cycle single-set reads. The parallel reads involve accessing data from all cache sets in parallel before a tag match is determined. Once a tag match is determined, it is used to select the one of the accessed cache memory locations to be coupled to the processor for the read operation. Single-cycle single-set reads occur when the line address of one read operation matches the line address of a immediately preceding read operation satisfied from the cache. In such a case, only the set from which the previous read request was satisfied is accessed in the present read operation. If a sequential read operation is indicated, the same-set can also be accessed to the exclusion of the other sets provided the requested address does not correspond to the beginning of a line address. (In that case, the sequential read crosses a cache-line boundary.

Abstract: A method (50) of operating a computing system (10). The computing system comprises a cache memory (12b), and the cache memory has a predetermined number of cache lines. First, the method, for a plurality of write addresses, writes data (64) to the cache memory at a location corresponding to each of the plurality of write addresses. Second, the method cleans (70) a selected number (68) of lines in the cache memory. For each of the selected number of lines, the cleaning step evaluates a dirty indicator corresponding to data in the line and copies data from the line to another memory if the dirty indicator indicates the data in the line is dirty. Lastly, the selected number of lines which are cleaned is less than the predetermined number of cache lines.

Abstract: A method and apparatus are presented for implementing the next-address determination within a binary search algorithm. A binary search algorithm searches for a compared within a one dimensional sorted array of elements. Typically, a binary search algorithm comprises a comparator and a next address generator. The next address generator determines the address of the next array element (the “next address”) a comparator will search using both a “compared is greater” signal from the comparator and a signal which indicates the address of the last array the comparator searched (the “previous address”). The time needed to search an array for a compared inserts a delay in applications where a binary search algorithm is employed. One method of expediting the searching process is to minimize the number of gates between the input and output of the next address generator (the “critical path”).

Abstract: An Address Generation Unit (AGU) for a processor such as Digital Signal Processor that includes a data memory addressable to obtain X and Y operands and a program decoder. The AGU is connected to the data memory and the program decoder and includes two Arithmetic Logic Units that are used to generate the X and Y operands. Each alu a has a triplet of registers associated there with and include a linear path of a first DBLC adder. The first DBLC adder has an A input, a B input, a carry input connected to receive a first control signal, and a summation output. The linear path further includes a by pass connection for by passing the first DBLC adder. A multiplexer selects either the summation output or the by pass as a linear output. Each alu also includes a modulo path that is in parallel with the linear stage. The modulo path has a series connection of a Carry Sum Adder (csa) and a second DBLC adder with a modulo output. A second multiplexer selects either the linear output or the modulo output as a result.

Abstract: To provide an improved memory in which code or data can be read out in the original order even when it is successively accessed by a processor of a successive type according to addressing in a grey code system and a method of storing code/data in such memory. Code/data addressed in the original binary code system are stored in a memory in the form in which the original order and continuity are not lost even after the addresses are converted to a grey code system. Accordingly, a processor of successive type can read out code or data in the original order by consecutively outputting addresses according to a grey code address system. The power consumption of the address generator can be reduced in accessing to consecutive addresses by having addresses of the memory space expressed in a grey code.

Abstract: A method of synchronizing the start of sequential read cycles when reading data in a memory in a synchronous mode with sequential access uses the increment pulses as synchronization signals for the address counters of the memory cell array. Following each increment pulse, a dummy ATD pulse is generated. The dummy ATD pulse is undistinguishable from an ATD pulse generated upon detection of a switching of external address lines.

Abstract: An improved method and structure for generating addresses of a memory array facilitates the testing of a memory cell by generating the address of any adjacent memory cell to the memory cell under test. The address generation provides for movement to any adjacent memory cell, in any direction, including north, south, east, west, northeast, northwest, southeast, and southwest. The address of any memory cell, even the address of a non-adjacent memory cell, may be selectively generated by defining a current memory address, choosing one or more modes by which increment-generated, decrement-generated, or combination increment/decrement addresses that define a next memory address are generated, and generating the row address and the column address of the next memory address in accordance with interdependent row carry-out and column carry-out operations.

Abstract: A system, method, and program for detecting and assuring a row by column structure in a Dynamic Random Access Memory array is disclosed. By writing to and reading from each memory location of the DRAM array, memory integrity is assured. The number of columns in the DRAM array is identified by writing data to and reading data from addresses selected from a series of cell addresses. The series of cell addresses identify standard DRAM column structures. When the data written to and read from the cell address is identical, the column configuration of the DRAM arrays is identified. The number of rows in the memory array is then identified by writing data to and reading data from addresses selected from a second series of cell addresses. The second series of cell addresses identify standard DRAM row structures. When data written to and read from the cell address is identical, the row configuration of the DRAM array is identified and accordingly, the row by column structure and integrity of the DRAM array are known.

Abstract: The inventive state mechanism assigns N+1 tags to N versions of an object stored in N memory areas. Thus, one tag is unused. An additional tag is used as a null or uninitialized tag. The other tags are assigned in a particular precedence order to revisions as they are stored. Thus, each assigned tag, except the null tag, has both a unique predecessor as well as a unique successor tag. The last tag of the sequence is lower in precedence to the first tag of the sequence, and this forms the cyclic relationship. The unused tag is used to determine the tag that is to be assigned to the next revision. The unused tag is also used to determine which revision is the most current revision. The inventive state mechanism is used by a memory management controller in maintaining the revisions.

Abstract: A semiconductor storage device having a plurality of block-erase type non volatile memory chips classifies the memory chips into memory groups of a number equal to twice the number of buffer memories provided in the storage device and assigns logic sector addresses sequentially to sectors contained in one erase block of each memory group in such a manner that the logic sector addresses are sequenced in series to those in the corresponding erase block of the next succeeding memory group.

Abstract: When memory size is increased by a factor of 2N (where N is an integer equal to or greater than unity) in a protocol-based memory system where a memory controller and multiple bus interfaces are interconnected via a bus, there exists a mismatch of N bits between the address format of each bus interface and that of the memory controller. In an initialization method for the memory system, one of the bus interfaces is enabled and request packets are transmitted successively from the memory controller to the enabled bus interface. Each packet contains a unique device identifier for identifying each bus interface. The packets of successive 2N arrivals are received at the enabled bus interface and an identifier for this bus interface is established using the device identifier contained in a predetermined one of the received packets by ignoring one or more device identifiers contained in other 2N−1 received packets.

Abstract: A non-volatile memory system having a memory controller, an array of memory cells and a memory operation manager. The operation manager carries out memory program, read and erase operation upon receipt of program, read and erase instruction from the controller, typically over a system bus. The address block circuitry is provided in the manager which is capable of performing an memory operation on a single address or on multiple addresses depending upon the state of the address block circuitry as determined by the controller. Multiple addresses can be generated based upon a single address provided by the controller so that sectors of the memory can be programmed or read thereby simplifying memory operations and reducing the overhead of the memory controller.

Abstract: The present invention provides, at a lower cost, a highly reliable data reading method and data reading apparatus that can improve backward sequential reading performance. The disk drive is provided with a magnetic disk and a control section having an HDC, a RAM, an MPU controlling the operation of the entire HDD, including control of the HDC, a ROM, and an I/F for connecting to an external host device. The control section executes a backward reading detection step that detects backward reading, a step of receiving a command that reads a block of a first length from a first LBA, a step that reads a block of the first length from the first LBA when backward reading is detected, and a step that pre-fetches a second block from a second LBA smaller than the first LBA; when backward reading is detected, upon completion of the reading of data from the disk, the reading of data predicted to be requested by the next command begins immediately.

Abstract: A chipset is configured to communicate between one or more processors and other components of the computer system, including a main memory. The chipset communicates read memory operations initiated by the processors to the main memory, and returns the data provided therefrom to the processors. Additionally, the chipset includes circuitry configured to select a portion of the data and to generate a prefetch address using the data. Accordingly, a pointer included in the data can be used to generate a prefetch address. The prefetching does not rely on observing the data access pattern. Instead, the data being transferred in response to a memory operation is used to generate a prefetch address (i.e. “data-directed prefetching”). In one embodiment, various programmable features are included in the chipset to specify which portion of the data to select, when to perform prefetching, etc.

Abstract: The invention provides a volatile or non-volatile memory and a latching circuit wherein data held in a first memory location is used to address the next memory location, in addition to providing a synchronous portion of the code. Accordingly, the data at the next memory address is used as a succeeding address and a subsequent portion of the code. The data is organized to repeat when the data stored in the address location is equal to the starting address.

Abstract: An improved method and structure for generating addresses of a memory array facilitates the testing of a memory cell by generating the address of any adjacent memory cell to the memory cell under test. The address generation provides for movement to any adjacent memory cell, in any direction, including north, south, east, west, northeast, northwest, southeast, and southwest. The address of any memory cell, even the address of a non-adjacent memory cell, may be selectively generated by exercising a programmable initialization feature.

Abstract: A data processing system (15) including a synchronous random access memory (30) and a method for accessing the synchronous random access memory are disclosed. A digital processor (20) of the data processing system is coupled to a system clock circuit (65) that produces a system clock signal for controlling operation of the digital processor. Addressable storage cells within the synchronous random access memory are accessed in response to the system clock signal and an address select signal (ADS) to write data into the storage cells or read data out from the storage cells. Initial row and column addresses are latched into a row address buffer (48) and a column address buffer (49). The data are read out from the memory in an order corresponding to a control signal (WT) in synchronization with the system clock signal. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

Abstract: An improved address translation method and mechanism for memory management in a computer system is disclosed. A fast physical address is generated in parallel with a fully computed virtual-linear-physical address in a system using segmentation and optional paging. This fast physical address is used for a tentative or speculative memory reference, which reference can be canceled in the event the fast physical address does not match the fully computed address counterpart. In this manner, memory references can be accelerated in a computer system by avoiding a conventional translation scheme requiring two separate and sequential address translation operations—i.e. from virtual to linear, and from linear to physical.

Abstract: A system and method for interfacing between an input/output system, that includes a local computer bus, a processor connected to the local computer bus and an interface to a computer system bus, and a computer system having a main memory is provided. The system includes a memory system with a memory controller that controls access and storage of data. The system may initiate sequential or burst ordered blocks of data over the computer bus from the computer system in anticipation of random access requests for data by the processor. A system and method for interfacing a plurality of processors to a computer system having a system bus and a main memory is also provided.

Abstract: A computer system is described including a CPU core, a memory device storing non-cacheable data, and a bus interface unit (BIU) coupled between the CPU core and the memory device. The CPU core accesses the memory device via the BIU. The BIU includes a stream read buffer, and the system includes logic to determine when to enter a stream read buffer mode. includes a stream read buffer. Following at least one transaction accessing the non-cacheable data within the memory device, the BIU obtains a portion of the non-cacheable data from the memory device, and stores the portion within the stream read buffer. For example, the memory device may include multiple storage locations for storing the non-cacheable data, and the storage locations may have consecutive addresses. Following the least one transaction accessing the non-cacheable data, the BIU may obtain the contents of multiple, consecutively-addressed storage locations of the memory device, and store the contents within the stream read buffer.

Abstract: A network interface includes a multiplexer that selectively supplies either a stored address from an address holding register, or a reload address from a reload address holding register, to a random access buffer memory based on a done delay signal (DMA_DONE_DLY). The done delay signal is generated by an advance signal generator in response to detection of a target initiated termination request on the PCI bus during a DMA data transfer from the random access buffer memory to the target. if the PCI bus transfer is interrupted, the reload address is supplied to the random access buffer memory to enable data output holding registers to be reloaded with the data lost by the target during the interrupted DMA transfer. The array of data output holding registers are capable of recovering from the interrupted PCI bus transfer and output the data set which the target (e.g., the host system memory) expects to receive.

Abstract: A data processing system (15) including a synchronous random access memory (30) and a method for accessing the synchronous random access memory are disclosed. A digital processor (20) of the data processing system is coupled to with a system clock circuit (65) that produces a system clock signal for controlling operation of the digital processor. Addressable storage cells within the synchronous random access memory are accessed in response to the system clock signal and an address select signal (ADS) to write data into the storage cells or read data out from the storage cells. Initial row and column addresses are latched into a row address buffer (48) and a column address buffer (49). A number of data bits corresponding to a control signal such as a wrap length (WL) signal are read out from the memory in synchronization with the system clock signal. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

Abstract: A semiconductor circuit of the present invention comprises, a decoder responding a plurality of address signals to produce a plurality of decoded address signals, a plurality of switch circuits receiving the respective decoded address signals, each switch circuits outputting an output signal, a plurality of registers receiving the respective output signals, each registers outputting a latched output signal, and supplying the latched output signal to the switch circuits except the switch circuit corresponding to that particular latched output signal, and a control circuit generating a control signal in response to a part of the address signal, the switch circuit outputting one of the decoded address signal and the latched output signal as said output signal according to the control signal.

Abstract: The invention provides a method and apparatus that provides for a determination of a memory address for an object coordinate in a non-linear addressing scheme. To minimize computation complexity, the memory address of the object coordinate is based upon a previously computed address of an object coordinate that is in proximity to the given object coordinate.

Abstract: A linked data structure verification system to verify the integrity of at least one linked data structure simultaneously by way of a verification setup phase and an integrity verification phase. Individual nodes are retrieved from a memory device and examined seriatim in optimal memory device location order. Nodes are retrieved and examined in optimal memory device location order for maximum memory device retrieval performance. Expected and/or actual node information about nodes in a given linked data structure are temporarily stored as records in an integrity verification table for only as much time as is necessary to verify any part of the node information prior to excising one or more unnecessary records from the integrity verification table.

Abstract: The disclosure of the current invention describes the methods and systems for inputting and outputting to and from the large capacity memory cards which are used as external data storage and expanded random access memory.

Abstract: Disclosed is a method and a device to improve the data output speed of a memory associated with a central processing unit of a microcomputer, should the reading be done at consecutive addresses of the memory in the mode known as the “burst read” mode. The address register is of the type with incrementation controlled by a sequencing circuit. The read register is followed by a data register which records the contents of the read register so as to free this read register to record the contents of the memory cells that are selected by the incremented address.

Abstract: A read-only memory is connectable to a microcontroller data bus and address bus and includes memory circuits for storing a sequential array of code words executable by the microcontroller; memory address decoding circuits for selecting one of the array of code words, and circuits for conveying the selected one to the data bus when a read signal is received from the microcontroller. Circuits are provided for storing an address transmitted by the microcontroller when an address latch signal is received from the microcontroller, the stored address being connected to the memory address decoding circuits. The stored address is incremented each time a read signal is asserted.

Abstract: A prefetch controller includes a request address register containing an address associated with an access request, an address history table containing a history of accessed addresses, an adder generating a prefetch address, a plurality of subtracters each generating a difference between the address contained in the address history table and the address stored in the request address register, a selector selecting the output of one of the subtracters, and an address controller updating the address history table according to the address difference generated by the subtracter and issuing a prefetch request to cache memory. When a processor accesses data located at a regular interval, the prefetch controller predicts the address the processor is going to access and prefetches data at the address into the cache memory.

Abstract: An address generator for a solid state disk drive device includes a hardware multiplier logic circuit dedicated to computation of the address by multiplying a lock size by a logical block number, to obtain the start address for a memory array read or write operation. The dedicated multiplier circuit advantageously provides very quick computation of these relatively large numbers, which typically involves a 32 bit by 16 bit multiplication. The multiplier includes a shift register initially holding the logical block number which is shifted a particular number of times, the number of shift pulses representing a value of the block length. The output of the shift register is the desired address.

Abstract: A method and apparatus suspend a program operation in a nonvolatile writeable memory. The nonvolatile writeable memory includes a memory array, a command register and memory array control circuitry. The command register decodes a program suspend command and provides a suspend signal as an output. The memory array control circuitry is coupled to receive the suspend signal from the command register. The memory array control circuitry performs a program operation in which data is written to the memory array. The memory array control circuitry suspends the program operation upon receiving the suspend signal.

Abstract: A computer system with a multiplexed address bus that is shared by both system memory and by slave devices is described. The slave devices are incorporated into an existing system memory configuration by providing a bus controller to execute a two-cycle address sequence on the multiplexed address bus. The address sequence is followed by a transfer of data. A random latency can exist between the time of receiving address information and the time of receiving data corresponding to the address information. This random latency can be exploited by the system CPU for other computational purposes. The bus controller of the system executes multiple, or pipelined, data writes to the bus before an acknowledgement for the first data write is received. In this scheme, the acknowledgement for the first data write is typically sent during the same time period that the subsequent data writes are being received. Consequently, data transfer acknowledgements overlap data writes.

Abstract: Variable-length instructions are prepared for simultaneous decoding and execution of a plurality of instructions in parallel by reading multiple variable-length instructions from an instruction source and determining the starting point of each instruction so that multiple instructions are presented to a decoder simultaneously for decoding in parallel. Immediately upon accessing the multiple variable-length instructions from an instruction memory, a predecoder derives predecode information for each byte of the variable-length instructions by determining an instruction length indication for that byte, assuming each byte to be an opcode byte since the actual opcode byte is not identified. The predecoder associates an instruction length to each instruction byte. The instructions and predecode information are applied to an instruction buffer circuit in a memory-aligned format.

Abstract: A digital memory matrix having memory cells in rows and columns, addressing of the memory cells is accomplished by control devices which perform arbitrary jumps of address, thereby avoiding addressing on adjacent lines. The jump increment is selectable. The control devices are control chains, two of which are provided, and the outputs of the control chains are connected to linking elements that in turn are connected to the memory lines. The linking elements are provided in groups.

Abstract: The present invention is a method and circuit for providing a burst address counter with a fast burst-done signal. In a preferred embodiment, a synchronous memory device includes a counter for producing a sequence of burst addresses, based on an external address. In addition, the counter drives the burst-done signal to indicate completion of the burst sequence. The counter includes a register for receiving the external address, an incrementor for advancing the external address to produce the next address of the sequence of burst addresses, a minus-two subtractor for determining a second-to-last burst address of the burst sequence, and a comparator. By utilizing the minus-two subtractor, the comparator can determine the end of the burst sequence earlier than conventional counters. This is because the minus-two subtractor determines the next-to-last address of the sequence, which allows the comparator to start asserting the burst-done signal at an earlier time.

Abstract: A display apparatus performs pixel density conversion processing, such as enlargement, reduction, and rotation, on an original image and displays a resultant image an image processing apparatus and, more particularly, a processing apparatus, for performing a high-speed filtering operation, such as data interpolation, involving pixel density conversion processing, uses a memory having an arithmetic function for use in the high-speed filtering operation.

Abstract: A shared memory controller prevents a memory area in a shared memory from becoming unusable even if an error occurs in an address for performing read/write operations. Under the control of a write control unit, each time N units of data and an address indicative of a storage location next to this data is written into the shared memory, one of the written addresses is stored in a second memory provided separately from the shared memory. Each time N addresses are read from the shared memory, an address stored in the second memory is read to detect in a detector whether or not the address is erroneous. If an error is detected, the erroneous address is discarded.

Abstract: A semiconductor memory device is provided with a determination circuit and an address adder. The determination circuit determines whether a read start address selects upper-address banks B5-B8 or lower-address banks B1-B4. When the determination circuit determines that the lower-address banks are selected, the address adder increments a column address by 1. From the upper-address banks, data are read from the columns corresponding to the read start address. From the lower-address banks, data are read from the columns that are next to the columns corresponding to the read start address. Even when the upper-address banks are designated by the read start address, the data output from the lower-address banks corresponds to the next columns. Since there is no busy time during data output, successive access is enabled and the access cycle time can be as short as possible.

Abstract: A microprocessor is configured to execute a stride instruction. In response to the stride instruction, the microprocessor performs a series of load memory operations. The address corresponding to a particular load memory operation is the sum of a stride operand of the stride instruction and the address corresponding to another load memory operation immediately preceding the particular load memory operation in the series. A base address operand specifies the address of the first load memory operation in the series, and a repetition count operand specifies the number of load memory operations in the series. The cache lines corresponding to the series of load memory operations (i.e. the cache lines storing the bytes addressed by the load memory operations) are fetched into the data cache of the microprocessor in response to the series of load memory operations.