Abstract: This invention combines a multicore shared memory controller and an asynchronous protocol converting bridge to create a very efficient heterogeneous multi-processor system. After traversing the protocol converting bridge the commands travel through the regular processor port. This allows the interconnect to remain unchanged while having any combination of different processors connected. This invention tightly integrates all of the processors into the same memory controller/interconnect.

Abstract: The CDR circuit 100 includes first to second data delaying cells ID1, ID2. The CDR circuit 100 includes first to fourth oscillation delaying cells IC1, IC2, IC3, IC4. The CDR circuit 100 outputs a second data signal d2 at a data output terminal TDout as a recovery data signal Dout. The CDR circuit 100 outputs an oscillation clock signal a0 at a clock output terminal TRCK as a recovery clock signal RCK.

Abstract: A command processing apparatus and method are provided for optimally processing commands issued asynchronously from a plurality of masters to a storage apparatus including a plurality of banks, where each master issues commands for a bank 0 and a bank 1 alternately. The command processing apparatus includes buffer units that obtain commands issued from the plurality of masters, an arbitration unit that arbitrates the obtained commands, and an issuance unit that issues commands to the storage apparatus according to the arbitration. The arbitration unit reads the commands of the plurality of masters obtained in the buffer units, and selects one command as a result of arbitration. The arbitration unit waits until a next command of a master relating to the selected command becomes readable, and reads the next command. The issuance unit consecutively issues the selected command and the read command to the storage apparatus.

Abstract: Apparatus and methods are disclosed for power optimization in a wireless device. The apparatus and methods effect monitoring the amount of data stored in a data buffer that buffers data input to and data output from a processor. Dependent on the amount of data stored in the buffers parameters of a control function, such as a Dynamic Clock and Voltage Scaling (DCVS) function are modified based on the amount of data stored in the data buffer. By modifying or pre-empting the parameters of the control function, which controls at least processor frequency, the processor can process applications more dynamically over default parameter settings, especially in situations where one or more real-time activities having strict time constraints for completion are being handled by the processor as evinced by increased buffer depth. As a result, power usage is further optimized as the control function is more responsive to processing conditions.

Abstract: The present invention provides a method of processing information associated with off-line billed communications in a communications network. The method includes providing at least one charging data record to a rating engine. The charging data record(s) include information associated with at least one off-line communication and are provided in response to receiving the charging data record(s). The rating engine determines costs of the off-line communication(s) at a time determined based on at least one time control category associated with the charging data record(s). The method also includes modifying the charging data record(s) to include information indicative of the cost(s) of the off-line communication(s) determined by the rating engine.

Abstract: An electronic device can receive a request from an accessory to provide a user interface to be displayed by the accessory. The electronic device can determine whether an accessory has a first set of one or more user input devices or a second set of one or more user input devices. In accordance with a determination that the accessory has a first set of one or more user input devices, the electronic device can provide to the accessory a first user interface configured to be controlled with the first set of user input devices. In accordance with a determination that the accessory has a second set of one or more user input devices, the electronic device can provide to the accessory a second user interface, different from the first user interface, the second user interface configured to be controlled with the second set of user input devices.

Abstract: Illustrative embodiments include a method, system, and computer program product for accelerating functional verification in simulation testing of an integrated circuit (IC). Using a processor and a memory, a serial operation is replaced with a direct register access operation, wherein the serial operation is configured to perform bit shifting operation using a register in a simulation of the IC. The serial operation is blocked from manipulating the register in the simulation of the IC. Using the register in the simulation of the IC, the direct register access operation is performed in place of the serial operation.

Abstract: A trace generating unit according to an embodiment of the present invention generates parallel trace information by executing a sequential program code, in case that the above-described sequential program code is parallelized and executed. The sequential program code includes a plurality of processing codes, codes to record a start and an end of the execution for each processing code, and codes to record a start and an end of the execution for each thread. The parallel trace information includes an execution sequence of the threads and an execution sequence of the processing codes for each thread.

Abstract: A method includes determining a rate of resource occupancy of a constituent stage of an unbalanced instruction pipeline implemented in a processor through profiling an instruction code. The method also includes performing data processing at a maximum throughput at an optimum clock frequency based on the rate of resource occupancy.

Abstract: A circuit includes a phase detector circuit and a data detection circuit. The phase detector circuit generates first and second phase detection signals based on a data signal and a periodic signal. The data detection circuit includes logic circuitry that generates a logic signal based on the first and second phase detection signals. The data detection circuit also includes a plurality of delay elements that generate a series of delayed detection signals based on the logic signal. The data detection circuit generates a data detection signal indicating when the data signal contains data based on the series of delayed detection signals.

Abstract: A system and method for reducing an electrical load in a facility or building with an automated demand response server having a hierarchical grouping of demand stages and demand groups with associated timers that control the shedding of load in order to achieve the appropriate level of load reduction and ramping up devices in a controlled manner upon the expiration of a demand response event.

Abstract: An information processing unit includes a processing unit including a plurality of processor cores; and a power consumption reduction device configured to reduce power consumption of the processing unit. The power consumption reduction device measures the loads on threads that are running in the plurality of cores; checks the number of high load threads which are threads in a high load state and the number of low load threads which are threads in a low load state for each core, on the basis of the measuring results; selects, when there exists a core having high load threads whose number is less than a preset threshold on the number of high load threads, the core as a candidate core; and replaces the high load threads existing in the candidate core with the low load threads existing in other cores when the total number of the low load threads in a core other than the candidate core is not less than the number of the high load threads in the candidate core.

Abstract: Various methods and systems are provided for buffer-batch management for energy efficient networking. In one embodiment, among others, a system includes a host device including an interface with a network. A device driver monitors requests to transmit packets from the host device to the network, buffers the packets in memory of the host device when the host device network interface is estimated to be in a low power mode, and initiates transition of the host device network interface to a full power mode based at least in part upon predefined criteria associated with the buffered packets. The host device network interface may begin transmission of the buffered packets when the host device network interface enters the full power mode. The host device network interface may be a network interface controller such as, e.g., an Ethernet controller configured for Energy Efficient Ethernet operation.

Abstract: Embodiments of the present disclosure may provide methods and devices capable of synchronizing time between a credential device and an authentication service. In an embodiment, a change in a time value on a device may be detected. A time value may be retrieved from an authentication service, and a new time value generated based upon at least the time value retrieved from the authentication service. The new time value may be used to set a time value at the device, and/or to generate a time-based credential.

Abstract: Examples disclosed herein relate to an image sign classifier. In one implementation, a processor causes a user interface to be displayed to receive information related to a target sign type in an image. The processor may train an image sign classifier based on the information to recognize the target sign type and output information related to the trained classifier.

Abstract: A first circuit operates in synchronization with a first clock having a first frequency, and generates N parallel data sets for every cycle period of the first clock. An interface circuit time-division multiplexes the N data sets received from the first circuit. A second circuit processes the N data set thus time-division multiplexed, in synchronization with a second clock having a second frequency which is N times the first frequency. A judgment unit judges whether or not the N data sets are effective data which instructs a flip-flop group, configured as a state holding element included in the second circuit, to generate an effective state transition. In a cycle period in which the N data sets are ineffective, a data replacement unit replaces at least a part of the N data sets with current compensation data DCMP.

Abstract: A device according to some embodiments may include a housing configured for location external to a body of a subject. The device may also include at least one processor associated with the housing and configured for electrical communication with a power source, and an antenna associated with the at least one processor. The at least one processor may be configured to communicate with an implant circuit located within the body of the subject, cause the implant circuit to receive power in a first power mode and in a second power mode, wherein a first level of power delivered in the first power mode is less than a second level of power delivered in the second power mode, and wherein during a therapy period, power delivery in the first mode occurs over a total time that is greater than about 50% of the therapy period.

Abstract: Asynchronous bridge circuitry provides data communication between source circuitry 4 in a source clock domain and destination circuitry 12 in a destinations clock domain. The asynchronous bridge circuitry includes first-in-first-out buffer 20, transmission path circuitry 14, which has an input end coupled to the source circuitry and an output end coupled to the first-in-first-out buffer. The transmission path circuitry has a transmission delay corresponding to a plurality of source clock cycles. Write pointer circuitry 22 located within the source clock domain at the output end 18 of the transmission path circuitry so as to generate a write pointer for the first-in-first-out buffer. Transmission control circuitry 26 located within the source clock domain at the input end 16 of the transmission path circuitry is configured to generate a transmission control signal which controls whether or not the source circuitry is permitted to send data.

Abstract: Arrangements for restarting data transmission on a serial low-power inter-chip media bus (SLIMbus) are presented. A clock signal may be provided in an active mode to a component communicatively coupled with the SLIMbus. Immediately prior to the clock signal in the active mode being provided, the clock signal may have been in a paused mode. While the clock signal was in the paused mode at least until the clock signal is provided in the active mode, the data line may have been inactive (e.g., a toggle on the data line may not have been present). Frame synchronization data for a frame may be transmitted. The frame synchronization data for the frame, as received by the component, may not match expected frame synchronization data. Payload data may be transmitted as part of the frame to the component, wherein the payload data is expected to be read properly by the component.

Abstract: An integrated-circuit memory controller outputs to a memory device a first signal in a first state to enable operation of synchronous data transmission and reception circuits within the memory device. A transaction queue within the memory controller stores memory read and write requests that, to be serviced, require operation of the synchronous data transmission and reception circuits, respectively, within the memory device. Power control circuitry within the memory controller determines that the transaction queue has reached a predetermined state and, in response, outputs the first signal to the memory device in a second state to disable operation of the synchronous data transmission and reception circuits within the memory device.

Abstract: Methods for preventing activation of hardware backdoors installed in a digital circuit, the digital circuit comprising one or more hardware units to be protected. A timer is repeatedly initiated for a period less than a validation epoch, and the hardware units are reset upon expiration of the timer to prevent activation of a time-based backdoor. Data being sent to the hardware unit is encrypted in an encryption element to render it unrecognizable to a single-shot cheat code hardware backdoor present in the hardware unit. The instructions being sent to the hardware unit are reordered randomly or pseudo-randomly, with determined sequential restraints, using an reordering element, to render an activation instruction sequence embedded in the instructions unrecognizable to a sequence cheat code hardware backdoor present in the hardware unit.

Abstract: An edge interval measuring block measures a first same-edge interval. A bit number detector detects the number of bits in the first same-edge interval based on reference bit length information and detects a first number of bits in a same-value interval between consecutive bits of the same value by subtracting the number of bits in the known bit stream from the number of bits in the first same-edge interval. The edge interval measuring block then measures a second same-edge interval. The bit number detector detects the number of bits in the second same-edge interval based on the reference bit length information and detects a second number of bits in a bit stream of consecutive bits of the same value opposite to the value in the same-value interval by subtracting the first number of bits from the number of bits in the second same-edge interval.

Abstract: A method of changing an operating frequency for performing a dynamic voltage and frequency scaling on a central processing unit included in a system on-chip is provided. A previous maximum peak workload of the central processing unit is detected in a history period of the dynamic voltage and frequency scaling when the operating frequency of the central processing unit is determined to be increased, and an increased operating frequency is applied to the central processing unit. The increased operating frequency is calculated based on the previous maximum peak workload of the central processing unit.

Abstract: Techniques to manage operational parameters for a processor are described. For instance, a method includes monitoring performance values representing physical characteristics for multiple components of a computing platform, and managing a performance level for a processor based on the performance values and one or more operational parameters for the processor. The operational parameters may include one or more transitory operational parameters that cause the processor to temporarily exceed operational parameters set by a thermal design power limit. Other embodiments are described and claimed.

Abstract: The present invention relates to a computer system and a clock configuring method. The computer system comprises at least two nodes, wherein each of the at least two nodes includes a selecting module and a CPU, inputs to the selecting module of any node comprise a clock of the node and a clock output from other node, and an output terminal of the selecting module is connected to the CPU and an input terminal of the selecting module of other node; the computer system further comprises a clock controlling module, whose output terminal is connected to a control terminal of the selecting module to control the clocks of the at least two nodes to be the same clock. When clocks of plural nodes are abnormal, the computer system can still normally operate as long as there is a normal clock in the computer system.

Abstract: In order to reduce occurrence of a fetching error of a digital signal, caused by a power-source noise, there is provided a semiconductor device provided with a switching circuit for executing a switching operation according to a pulse control signal and a digital signal hold circuit for fetching a digital signal. The digital signal hold circuit includes a mask signal generation circuit for generating a mask signal from the pulse control signal, the mask signal being for use in keeping the digital signal from being fetched during a time period of power-source noise occurrence caused by the switching operation, and the digital signal is not fetched during the time period of power-source noise occurrence while the digital signal is fetched during a time period of power-source noise nonoccurrence.

Abstract: An embodiment of the invention provides a communication device (100) for processing data samples and comprises a communication entity (102) and a further communication entity (104) communicatively coupled to the communication entity (102) with a digital interface. The communication entity (102) comprises a timing generation unit (106) adapted for generating real-time related timing information for operating hardware components of the communication entity (102) when processing data samples. The further communication entity (104) is adapted for operating hardware components of the further communication entity (104) in a sample-driven way when processing data samples.

Abstract: Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits.

Abstract: A network node of a synchronous network, wherein said network node comprises a timing circuit which recovers a reference clock from a reception signal received by said network node from an upstream network node of said synchronous network and uses the recovered reference clock for a transmission signal transmitted by said network node to a downstream network node of said synchronous network; and a clock stability monitoring circuit which monitors internal control parameters (CP) of said timing circuit to detect an instability of the reference clock distributed within said synchronous network.

Abstract: Systems and methods are disclosed which relate to improving synchronization of clocks between a sender and a receiver communicating via an asynchronous serial interface. In a ring topology, a master device is connected to a plurality of slaves communicating using a bi-frequency encoded bit stream. A host device communicates with the master device using a non-return-to-zero data encoding. Each slave receives data from the master and sends it to the next slave in the ring unaltered unless the master indicates a requirement for a particular data, and transmits placeholder bits with a value of 0 around the ring. A particular slave can “fill-in” the placeholder bits with the information to be sent back to the master by inverting the placeholder bit. Clock synchronization between a receiving device and a transmitting device is improved using a fractional rate multiplier to generate a data sampling clock from a system clock.

Abstract: Example embodiments disclosed herein relate to storing event data and a time value in memory with an event logging module. Example embodiments of the event logging module include event command storage, clock command storage, and memory command storage.

Abstract: A method for setting addresses of slave devices in a communication network is provided. In the communication network, a master device identifies address-collided slave devices and requests the address-collided slave devices to return their unique identification data. The master device sets addresses of the address-collided slave devices so that each of the slave devices in the communication network has a different address from one another.

Abstract: In an information processing apparatus, a control unit includes a first clock device for providing the time of day. A physical domain includes a second clock device, and implements a logical domain that functions as a virtual information processing apparatus. The control unit controls a first time-of-day difference between the time of day of the first clock device and that of the second clock device. The physical domain controls a second time-of-day difference between the time of day of the second clock device and that of the logical domain. In the information processing apparatus, the time of day on the logical domain is controlled based on the first and second time-of-day differences.

Abstract: A single wire serial interface for power ICs and other devices is provided. To use the interface, a device is configured to include an EN/SET input pin. A counter within the device counts clock pulses sent to the EN/SET input pin. The output of the counter is passed to a ROM or other decoder circuit. The ROM selects an operational state for the device that corresponds to the value of the counter. In this way, control states may be selected for the device by sending corresponding clock pulses to the EN/SET pin. Holding the EN/SET pin high causes the device to maintain its operational state. Holding the EN/SET pin low for a predetermined timeout period resets the counter and causes the device to adopt a predetermined configuration (such as off) until new clock pulses are received at the EN/SET pin.

Abstract: Provided is a timing control device including: a storage unit that stores multiple pieces of timing control information including identification information and expected value data; a first selector that selectively outputs any of the multiple pieces of timing control information; a second selector that selectively outputs any of data items output from data output devices based on the identification information; a reference data generation unit that generates reference data based on expected value data and a data item output from the second selector in synchronization with a switching of the timing control information; a comparator that compares the reference data with the data item output from the second selector and outputs a coincidence signal when the reference data and the data item coincide with each other; and an output control unit that outputs a timing signal according to the coincidence signal.

Abstract: A novel integrated circuit (IC) that configurably distributes clocks from multiple clock sources to multiple sets of circuits is described. The IC includes multiple clock sources and multiple clock domains. Each clock domain includes a clock signal and a control signal. The clock signal is configurably selected from one of the multiple clock sources. The control signal is synchronized to the clock signal. The IC also includes multiple configurable circuits. A configurable circuit can configurably operate in one of the clock domains by selecting and using the control signal and the clock signal of the clock domain.

Abstract: A memory interface circuit for read operations is described. The circuit includes one or more controller circuits, one or more read data delay circuits for providing CAS latency compensation for byte lanes. In the system, control settings for the read data delay circuits for providing CAS latency compensation are determined and set using controller circuits according to a dynamic calibration procedure performed from time to time. In the system, determining and setting the control settings for the read data delay circuits for providing CAS latency compensation is performed independently and parallely in each of a plurality of byte lanes.

Abstract: A memory device is provided. The memory device includes a preamble disable memory and a memory controller. The preamble disable memory is arranged to store preamble disable data. The preamble disable data includes an indication as to whether a read preamble should be enabled or disabled. In response to a read command, if the preamble disable data includes an indication that the read preamble should be enabled, the memory controller provides the read preamble. Alternatively, in response to the read command, if the preamble disable data includes an indication that the read preamble should be disabled, the memory controller disables the read preamble.

Abstract: A clock frequency is controlled by determining a cumulative duty cycle according to a ratio of a cumulative time, during an interval, that the clock frequency has a frequency greater than or equal to a design frequency threshold value to a duration of the interval. A frequency of the clock frequency is controlled to be a first frequency value when the cumulative duty cycle is less than a first duty cycle threshold; and controlled to be a second frequency value substantially less than the first frequency value when the cumulative duty cycle is greater than a second duty cycle threshold. The second duty cycle threshold is greater than or equal to the first duty cycle threshold.

Abstract: A device configured to switch a clock speed for multiple links running at different clock speeds and a method for switching the clock signals are disclosed. A frequency divider derives a plurality of clock signals at different frequencies from a source clock signal. A clock switching controller selects a maximum data rate among data rates requested by a plurality of ports of links and outputs a transmit clock signal at the selected maximum data rate to the ports along with a clock enabling signal for each of the ports. Each of the clock enabling signals selectively enables the transmit clock signal for matching a data rate requested by each port. The clock speed may be selected and updated as required by the ports glitch-free in a known amount of time without interrupting data transfers on any of the other ports.

Abstract: A method whereby the frequency of the clock of an internal bus of a sink of High Definition Multimedia Interface (HDMI) data is reduced, and possibly deep color mode of a sink deactivated, in response to an inability of a source of HDMI data to read extended display identification data (EDID) and/or effect High Definition Content Protection (HDCP) authentication with the sink.

Abstract: A programmable logic device is provided that includes: a programmable interconnect adapted to route input signals through the device at a system clock rate; and a digital signal processor (DSP) block coupled to the interconnect, the DSP block including: a plurality of input ports; an input register coupled to the multiple input ports and adapted to sequentially register samples of the input signals from the interconnect received at the input ports at a multiple of the system clock rate; and a multiplier adapted to multiply the registered samples at the multiple of the system clock rate to produce an output signal.

Abstract: A microprocessor includes a plurality of semiconductor dies, a bus coupling the plurality of semiconductor dies, and a plurality of processing cores. A distinct subset of the processing cores is located on each of the semiconductor dies. Each die comprises a control unit configured to selectively control a respective clock signal to each of the subset of cores of the die. For each core of the subset, in response to the core writing a value to the control unit, the control unit is configured to turn off the respective clock signal to the core and to write the value over the bus to the control unit of the other die. Collectively all of the control units are configured to simultaneously turn on the clock signals to all of the processing cores after the clock signals have been turned off to all of the processing cores.

Abstract: A data processing apparatus includes: a plurality of processing units adapted to process data according to input operation clocks; and a control unit adapted to measure response times of the plurality of processing units when the operation clocks of a common frequency are supplied to the plurality of processing units, and to control a frequency of the operation clocks to be supplied to at least one of the plurality of processing units so that a plurality of measured response times become closer to each other.

Abstract: Methods, apparatuses, and computer program products for adaptive clock throttling for event processing are provided. Embodiments include an event processing system receiving a plurality of events from one or more components of the distributed processing system. Embodiments also include the event processing system determining that an arrival attribute of the plurality of events exceeds an arrival threshold. Embodiments also include the event processing system, adjusting, in response to determining that the arrival attribute of the plurality of events exceeds the arrival threshold, a clock speed of at least one of the event processing system and a component of the distributed processing system.

Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.

Abstract: A communication control device includes: a first processing unit that converts an electrical signal received by a communication channel into digital data and outputs the digital data, and in a second operation mode in which an amount of power supplied to the communication control device is lower than in a first operation mode, outputs a notification signal upon receiving an electrical signal indicating an arrival of packet data; a clock controller that, in the second operation mode, initiates supplying a clock signal upon receiving the notification signal; and a second processing unit that (i) has a receiving unit that extracts packet data from the digital data and outputs the extracted packet data, and (ii) in the second operation mode, stops receiving packet data during a time that the clock signal is not supplied, and upon reception of the clock signal, starts receiving packet data using the received clock signal.

Abstract: A method of communicating in an electronic system or apparatus is disclosed. The method includes using a processor to communicate with a peripheral. The method further includes using the peripheral to request a clock signal. The method also includes selectively control communication of the clock signal to the peripheral in response to the request.

Abstract: Collecting bandwidth data includes producing master and slave text files in response to simultaneous collection of data samples from a network device by servers, generating a clean data file by sorting data in the master and slave text files by the network device port, sorting data samples for the port by collection time, and for each of the samples: adding a designated interval of time to a time on the network device resulting in a target network device time whereby the time on the network device corresponds to a time the data sample was collected, examining data samples in the master and slave text files corresponding to the time the respective data samples were collected, selecting from one of the master and slave text files the sample with a collection time most closely matching the target network device time, and storing the selected sample in the clean data file.

Abstract: A data processing method and apparatus are provided. The data processing apparatus includes a converter module and a control module. The converter module receives a clock signal through a pin, and decides a bit value of the first data according to a length of a corresponding period of the clock signal. The control module determines whether to perform a bit writing operation for writing the bit value into a memory according to the clock signal and the first data.