For Reliability Enhancing Component (e.g., Testing Backup Spare, Or Fault Injection) Patents (Class 714/41)
  • Patent number: 9836224
    Abstract: A redundant array of independent disks (RAID) storage system, includes a RAID master controller receiving a RAID request selectively communicating the RAID request to one of a plurality of storage devices, wherein first and second storage devices are directly connected outside a data communication path including the host among the storage devices. The first storage device determines upon receiving the RAID request whether distribution of a RAID sub-request to the second storage device is necessary, such that upon determining that the distribution of a RAID sub-request is necessary, the first RAID controller communicates the RAID sub-request to the second storage device via the direct network connection.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: December 5, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Min Seo, Ju-Pyung Lee
  • Patent number: 9817608
    Abstract: A system and method for exposing volumes with underlying read-write mediums to user operations. When a medium is in the process of being replicated to a storage array, a volume which relies on the medium can be exposed to user operations (e.g., snapshots, read and write operations) once the portions of the medium which underlie the volume have been replicated. The volume can be exposed to user operations while one or more other portions of the medium are unfilled and while the medium is in an intermediate read-write state.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: November 14, 2017
    Assignee: Pure Storage, Inc.
    Inventors: Christopher Golden, Jianting Cao, David Grunwald, Malcolm Sharpe, Steve Hodgson
  • Patent number: 9768990
    Abstract: A device for manipulating interface signals includes a slave interface, which is connectable to a master interface of a control device, a master interface, which is connectable to a slave interface of a measuring device, and a circuit configuration, which is supplied with at least one data-input signal per interface, and which outputs a corresponding data-output signal per data-input signal to the respective other interface. The circuit configuration includes at least one manipulation unit, to which a data-input signal and a substitute-data signal are supplied and which outputs a corresponding data-output signal, as well as a protocol unit, to which at least one protocol-relevant interface signal is supplied and which, based on manipulation rules and information received with the at least one protocol-relevant interface signal, chooses when the at least one manipulation unit outputs the corresponding data-input signal or the substitute-data signal as data-output signal.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: September 19, 2017
    Assignee: DR. JOHANNES HEIDENHAIN GMBH
    Inventors: Stephan Kreuzer, Elmar Mayer, Udo Ollert
  • Patent number: 9702920
    Abstract: Systems and methods presented herein are generally directed to the location and/or identification of a circuit within a circuital system. In one embodiment, a transmitter is configured for inducing signals upon a plurality of circuit lines (e.g., power lines, communication lines, lighting circuits, etc.) with each circuit line having a unique signal to identify it from other circuit lines. Each signal may be induced upon an individual circuit line by means of a inductive coupling clip coupled about the circuit line. The transmitter may be used at a distribution point of the circuit lines, such as circuit breaker box. A receiver can then receive a signal from a distal point on the circuit line to acquire the unique signal induced thereon and identify determine which inductive coupling clip is coupled thereto. For example, the signal may be decoded to display a number of the circuit line being tested.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: July 11, 2017
    Assignee: Tasco Incorporated
    Inventor: Steven Thomas McCasland
  • Patent number: 9678816
    Abstract: Probes are employed to inject errors into code. In response to a function-entry trigger event, a probe writes a predefined test value to a return value register. The probe then cause function execution to be skipped such that the test value is returned in lieu of the value which would otherwise be returned by the function. Behavior after the error is injected may then be observed, data collected, etc. such that undesired behavior (e.g., crashes) can be identified and/or corrected. In an alternative embodiment, the probe which is triggered may write a test value to a given memory address.
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: June 13, 2017
    Assignee: VMware, Inc.
    Inventors: Radu Rugina, Vivek Mohan Thampi, Ricardo E. Gonzalez, Alok Kataria
  • Patent number: 9542287
    Abstract: Embodiments of the solid-state storage system provided herein are configured to perform improved mechanisms for testing of error recovery of solid state storage devices. In some embodiments, the system is configured to introduce or inject errors into data storage commands or operations performed in the non-volatile memory. Injected errors include corruption of data stored in the non-volatile memory, deliberate failure to execute storage operations, and errors injected into communication protocols used between various elements of the device. In some embodiments, injected errors can include direct errors that trigger an immediate execution of error recovery mechanisms and delayed errors that trigger execution of error recovery mechanisms at a later time. Error recovery mechanisms can be tested in an efficient, reliable, and deterministic manner to help ensure effective operation of storage devices. The integrity of non-volatile memory can also be tested.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: January 10, 2017
    Assignee: Western Digital Technologies, Inc.
    Inventor: Sebastien A. Jean
  • Patent number: 9489276
    Abstract: A method, system and computer program product are provided for implementing enhanced wear leveling in a stack of flash memory chips. A flash memory includes plurality of flash memory chips including a number N data chips and one or more spare chips. To even wear among the plurality of flash memory chips, a memory controller for the flash memory periodically transfers data from a data chip to a current spare chip, the current spare chip becomes a data chip and the selected data chip becomes the current spare chip. Over time, each chip in the stack becomes the spare chip. If a chip becomes nonfunctional, whatever chip is currently the spare chip becomes a permanent data chip and no more rotating is done.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: November 8, 2016
    Assignee: International Business Machines Corporation
    Inventors: Gary A. Tressler, Diyanesh Babu C. Vidyapoornachary
  • Patent number: 9483303
    Abstract: A computing device initiates execution of a first co-routine on the computing device. The first co-routine utilizes an execution stack in a memory of the computing device. A differential symmetric co-routine module pauses execution of the first co-routine and, subsequently, resumes execution of the first co-routine utilizing the same execution stack.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: November 1, 2016
    Assignee: Red Hat, Inc.
    Inventor: Nathaniel McCallum
  • Patent number: 9471451
    Abstract: A method, system and computer program product are provided for implementing enhanced wear leveling in a stack of flash memory chips. A flash memory includes plurality of flash memory chips including a number N data chips and one or more spare chips. To even wear among the plurality of flash memory chips, a memory controller for the flash memory periodically transfers data from a data chip to a current spare chip, the current spare chip becomes a data chip and the selected data chip becomes the current spare chip. Over time, each chip in the stack becomes the spare chip. If a chip becomes nonfunctional, whatever chip is currently the spare chip becomes a permanent data chip and no more rotating is done.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: October 18, 2016
    Assignee: International Business Machines Corporation
    Inventors: Gary A. Tressler, Diyanesh Babu C. Vidyapoornachary
  • Patent number: 9448966
    Abstract: System and method embodiments are provided to implement highly scalable and high availability (HA) clusters in massively parallel processing (MPP) systems. The embodiments include a method to build a highly scalable MPP HA cluster, which provides HA to the cluster while allowing it to scale to relatively larger number of nodes. An embodiment apparatus includes a plurality of data processing nodes distributed in a plurality of corresponding sub-clusters and configured to exchange heart-beat messages between each other within limit of each of the corresponding sub-clusters to maintain sub-cluster membership integrity and detect failures in the corresponding sub-clusters. The sub-clusters are arranged in a fan-out tree hierarchy and configured to prevent heart-beat messaging between each other.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: September 20, 2016
    Assignee: Futurewei Technologies, Inc.
    Inventors: Gangavara Prasad Varakur, Anil Chillarige
  • Patent number: 9344281
    Abstract: A secure provisioning manifest used to authenticate and securely communicate with peripherals attached to a computer is provided with techniques to withdraw the authentication and terminate the secure communications with any peripheral when operating parameters for the peripheral indicate that there is a security threat associated with the peripheral. A secure I/O module, that is separate from an operating system and transaction software executed by a processor of the computer, uses the secure provisioning manifest to establish a secure encrypted session for communicating with each peripheral attached to the computer when a peripheral is authenticated and able to establish a secure encrypted session. The secure I/O module uses current and known operating parameters for each peripheral to periodically determine if a peripheral has been compromised by a security threat.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 17, 2016
    Assignee: NCR Corporation
    Inventors: Erick Christian Kobres, Ron William Rogers
  • Patent number: 9263092
    Abstract: A method according to one embodiment includes monitoring a plurality of parameters relating to operation of a tape drive to collect data from the operation of the tape drive. A specification of one or more of the parameters to log during one or more collection windows is received. At least some of the data collected from the operation of the tape drive is logged to a memory during the one or more collection windows, where the at least some of the data collected is stored in a plurality of fields. The method further includes dynamically overlaying one or more of the fields with data corresponding to the one or more specified parameters.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: February 16, 2016
    Assignee: International Business Machines Corporation
    Inventors: Kevin D. Butt, Ernest S. Gale, Pamela R. Nylander-Hill
  • Patent number: 9256489
    Abstract: In an approach for determining a location of failure between interconnects/controller, a computer collects debug information simultaneously at a plurality of nodes coupled to an interconnect. Subsequent to collecting debug information, the computer analyzes the debug information collected simultaneously thereby determining which end of the interconnect caused the failure.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: February 9, 2016
    Assignee: International Business Machines Corporation
    Inventors: Ajay K. Mahajan, Venkatesh Sainath, Vishwanatha Subbanna
  • Patent number: 9224500
    Abstract: Embodiments described herein relate to systems and methods for testing and assembling memory modules. In at least one embodiment, the method comprises: assembling a memory module, the memory module comprising at least one memory device having one or more defective memory locations; wherein the assembling comprises storing the data that identifies the one or more defective memory locations on the memory device in a persistent store on the memory module, wherein the memory module comprises a microprocessor and persistent memory associated with the microprocessor, and wherein the persistent store on the memory module comprises the persistent memory associated with the microprocessor.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: December 29, 2015
    Assignee: KingTiger Technology (Canada) Inc.
    Inventors: Lawrence Wai Cheung Ho, Eric Sin Kwok Chiu, Bosco Chun Sang Lai, Sunny Lai-Ming Chang
  • Patent number: 9176713
    Abstract: A method, apparatus and program storage device that provides a user mode device interface for enabling software reuse. The user mode device interface allows device interface requests to be sent and received, including commands and data structures, via socket communication. A device state machine on the client side is implemented in a set of shared functions that can be incorporated by all applications that want to communicate to a particular service provider. The service provider offers the software functions over a user mode device interface via socket communication. The device state machine on the service provider side is embedded in the socket server implementation. The interaction between the state machines on both client and server sides ensures a device interface request is properly handled.
    Type: Grant
    Filed: November 30, 2005
    Date of Patent: November 3, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chiahong Chen, Radha K. Ramachandran, Cheng-Chung Song
  • Patent number: 9152532
    Abstract: The present disclosure relates to a method and system for configuring a computing system, such as a cloud computing system. A method includes selecting, based on a user selection received via a user interface, a workload for execution on a cluster of nodes of the computing system. The workload is selected from a plurality of available workloads including an actual workload and a synthetic test workload. The method further includes configuring the cluster of nodes of the computing system to execute the selected workload such that processing of the selected workload is distributed across the cluster of nodes. The synthetic test workload may be generated by a code synthesizer based on a set of user-defined workload parameters provided via a user interface that identify execution characteristics of the synthetic test workload.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: October 6, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mauricio Breternitz, Keith A. Lowery, Patryk Kaminski, Anton Chernoff
  • Patent number: 9148479
    Abstract: A computer-implemented method for determining the healthiness of nodes within computer clusters may include (1) identifying a computer cluster that includes a plurality of nodes configured to provide substantially continuous availability of at least one application, (2) identifying at least one operating system kernel installed on at least one of the nodes, (3) configuring the operating system kernel to (a) asynchronously monitor performance of the node and (b) determine, based at least in part on the node's performance, whether the node is sufficiently healthy to execute the application, (4) receiving a notification from the operating system kernel that indicates that the node is not sufficiently healthy to execute the application, and then (5) performing at least one action configured to enable the computer cluster to provide substantially continuous availability of the application despite the unhealthy node. Various other systems, methods, and computer-readable media are also disclosed.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: September 29, 2015
    Assignee: Symantec Corporation
    Inventors: Anand Bhalerao, Amit Gaurav, Amit Haridas Rangari, Vishal Thakur
  • Patent number: 9092312
    Abstract: A method includes modifying, at a bit error injection circuit, a multiplier value by a first value according to an occurrence of a first event. The method also includes, in response to a determination that the modified multiplier value matches a first threshold, modifying, at the bit error injection circuit, the offset value according to an occurrence of a second event. The method further includes, in response to a determination that the modified offset value matches a second threshold, asserting, at the bit error injection circuit, an error injection signal. The method further includes asserting a first error pattern to be transmitted via a bus lane based on the error injection signal.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: July 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Patrick J. Meaney, Michael B. Spear, Kenneth L. Wright
  • Patent number: 9092823
    Abstract: A method of detecting malware on a computer and comprising scanning a system memory of the computer, and/or code being injected into the system memory, for known strings indicative of banking trojans. These strings may be Universal Resource Locators and/or partial Universal Resource Locators.
    Type: Grant
    Filed: June 1, 2007
    Date of Patent: July 28, 2015
    Assignee: F-SECURE OYJ
    Inventor: Mika Ståhlberg
  • Patent number: 9069729
    Abstract: Method, system, apparatus and/or computer program for achieving transparent integration of high-availability services for distributed application programs. Loss-less migration of sub-programs from their respective primary nodes to backup nodes is performed transparently to a client which is connected to the primary node. Migration is performed by high-availability services which are configured for injecting registration codes, registering distributed applications, detecting execution failures, executing from backup nodes in response to failure, and other services. High-availability application services can be utilized by distributed applications having any desired number of sub-programs without the need of modifying or recompiling the application program and without the need of a custom loader. In one example embodiment, a transport driver is responsible for receiving messages, halting and flushing of messages, and for issuing messages directing sub-programs to continue after checkpointing.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: June 30, 2015
    Assignee: RED HAT, INC.
    Inventors: Allan Havemose, Ching-Yuk Paul Ngan
  • Patent number: 9026858
    Abstract: A testing server performs a test to check whether servers properly execute failover. The testing server includes a generation unit, a transmitting unit, a testing unit, a restoring unit, a judgment unit, and a power control unit. The generation unit generates an image file of an OS. The transmitting unit transmits the image file to to-be-tested servers. The testing unit injects a simulated fault into a server among the servers to which the image file is transmitted and performs a test. The restoring unit, each time the testing unit performs a test, restores a status of the to-be-tested server to a pre-failover status. The judgment unit judges whether the restoring unit properly restores the status. The power control unit, when the judgment unit judges that the status of the to-be-tested server is not properly restored, turns off power of the to-be-tested server and turns on the power again.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: May 5, 2015
    Assignee: Fujitsu Limited
    Inventors: Susumu Rikitake, Ikuo Shimada
  • Patent number: 9015530
    Abstract: In one embodiment, a virtual machine replication system may test a replica data set while continuing to replicate a primary data set. A data storage 250 may store a replica data set for a replica virtual machine 302 to back up a primary data set for a primary virtual machine 304. The data storage 250 may preserve a test point in time 322 in the replica data set using a test differencing disk 344. A processor 220 may execute a test virtual machine 342 that performs a test operation on the test point in time 322 while the replica data set continues to replicate the primary data set.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: April 21, 2015
    Inventors: Phani Chiruvolu, Vinod Atal, Gaurav Sinha
  • Patent number: 9003231
    Abstract: It is frequently difficult to generate multiple separate instances of a complex system. It is also difficult to restore the data state of these instances to a known state. Embodiments simplify the process by classifying the complex system under test in terms of its state components and service, by creating a new instance for testing, and by using copy-on write approaches to restore that new instance to the desired known state.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: April 7, 2015
    Assignee: Google Inc.
    Inventor: Joseph Graves
  • Patent number: 9003238
    Abstract: A method for error simulation in a data storage subsystem providing abstractions of one or more storage devices. The method includes dividing the data storage subsystem into two or more hierarchically organized subsystems, wherein the subsystems interact using IO Request Packets (IORPs), such that relatively higher level subsystems create and populate IORPs and pass them to relatively lower level subsystems for corresponding processing. The method further includes defining an IORP modifier configured to attach to matching IORPs based on one or more attributes of the IORP modifier and to modify at least one of the processing and one or more attributes of the IORP in order to simulate errors in the data storage subsystem.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: April 7, 2015
    Assignee: Compellent Technologies
    Inventors: Anthony J. Floeder, Lawrence A. Dean
  • Patent number: 8966318
    Abstract: A health services module can test availability of one or more applications installed in a virtual machine that is instantiated from a backup image of a virtual machine disk file. A health services module can be installed on a virtual machine to test one or more applications that a user wishes to validate. If the health services module indicates that the application(s) of the virtual machine are available, a guarantee of availability can be provided for the backup image of the virtual machine disk file. If the health services module indicates that the application(s) of the virtual machine are unavailable, no guarantee of availability can be given. The guarantee of availability can indicate that the backup image of the virtual machine disk file can be successfully restored, and that the application(s) of the virtual machine instantiated from the backup image are available to respond to a client request.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: February 24, 2015
    Assignee: Symantec Corporation
    Inventor: Amrish Shah
  • Patent number: 8954807
    Abstract: A fault-based software testing method and system are provided. The fault-based software testing method includes: generating a plurality of error programs by injecting faults into a testing target program; grouping the generated error programs into a plurality of groups with respect to respective test data, and selecting representative error programs with respect to the respective groups; and when an error is detected in the execution result of the representative error programs with respect to the corresponding test data, determining that errors are detected in all the error programs of the corresponding group.
    Type: Grant
    Filed: October 5, 2012
    Date of Patent: February 10, 2015
    Assignee: Electronics & Telecommunications Research Institute
    Inventors: Yu Seung Ma, Duk Kyun Woo, Seon Tae Kim, Pyeong Soo Mah
  • Patent number: 8954806
    Abstract: A method that determines the system impact of single event upset (SEU) and a single event upset (SEU) wrapper that controls a SEU controller is disclosed. The method injects faults into a component (e.g. FPGA, ASIC) of an operational system that is carrying live traffic and monitors the system's response to the faults to determine the impact of SEU on the system. The SEU wrapper sends the SEU controller a pattern scheme that includes information indicating when, where, how often, and/or how long to inject bursts of one or more faults into memory of the component of the system. A burst of faults contains faults that are consecutively injected into the array of memory blocks. After each fault in a burst is injected, one or more errors in one or more memory elements are detected and/or corrected. Information regarding the detection and/or the correction of an error is updated using registers that store counters. After injecting a burst of faults, the SEU controller waits for a predetermined amount of time.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: February 10, 2015
    Assignee: Cisco Technology, Inc.
    Inventors: Yie-Fong Dan, Shi-Jie Wen, Raymond Ng
  • Patent number: 8954582
    Abstract: In one embodiment, a management device receives one or more fate-sharing reports locally generated by one or more corresponding reporting nodes in a shared-media communication network, the fate-sharing reports indicating a degree of localized fate-sharing between one or more pairs of nodes local to the corresponding reporting nodes. The management device may then determine, globally from aggregating the fate-sharing reports, one or more fate-sharing groups indicating sets of nodes having a global degree of fate-sharing within the communication network. As such, the management device may then advertise the fate-sharing groups within the communication network, wherein nodes of the communication network are configured to select a plurality of next-hops that minimizes fate-sharing between the plurality of next-hops.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: February 10, 2015
    Assignee: Cisco Technology, Inc.
    Inventors: Jean-Philippe Vasseur, Jonathan W. Hui
  • Patent number: 8949653
    Abstract: Various systems and methods for evaluating and controlling high-availability configuration. For example, one method can involve detecting fault tolerance parameters that can be available within a datacenter. The method also involves identifying a set of fault tolerance parameters that applies to an application. Identifying the fault tolerance parameters that apply to the application involves detecting whether the application is associated with one or more high-availability applications. The method also involves generating an index value for the application. The index value is based on the fault tolerance parameters associated with the application and provides an objective measure of the fault tolerance of the application.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: February 3, 2015
    Assignee: Symantec Corporation
    Inventors: Rohan Kumar Kayan, Ravikant Ambadas Gedam, Santosh Kumar Konduru
  • Patent number: 8935571
    Abstract: Described herein are systems and methods related to a plug-in for a visual tool as a real-time knowledge transfer agent between network outages. One embodiment relates to a method comprises retrieving current outage data related to a current operation of a network, retrieving historical outage data related to a prior operation of the network, correlating the current outage data with the historical outage data, and constructing a resolution process plan for repairing a current outage based on correlations between the current outage data and the historical outage data.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: January 13, 2015
    Assignee: AT&T Intellectual Property I, L.P.
    Inventor: Brian Lee
  • Patent number: 8924792
    Abstract: A solution for validating a set of data protection solutions is provided. A validation scenario can be defined, which can include data corresponding to a set of attributes for the validation scenario. The attributes can include a time frame for the validation scenario. The validation scenario also can include a set of backup images to be validated, each of which is generated using one of the set of data protection solutions. The set of backup images can be identified using the time frame. A set of resource requirements for implementing the validation scenario can be determined based on the set of backup images and the set of attributes for the validation scenario.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: December 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kavita Chavda, Nagapramod S. Mandagere, Steven Pantridge, Ramani R. Routray
  • Patent number: 8918679
    Abstract: An apparatus for checking an error detection functionality of a data processing circuit, comprising an arithmetic logic unit, which provides an output datum based on an input datum, and an error detection circuit that executes the error detection functionality and detects an error based on the output datum during correct execution of the error detection functionality, and generates an error signal, if an error is present, which comprises a control circuit that passes the error signal through to an error signal output in a normal operating mode, and blocks the error signal in a checking mode, does not let the error signal pass to the error signal output, influences the arithmetic logic unit, the error detection circuit or the input datum such that the error detection circuit detects an error during correct execution of the error detection functionality, and, if no error signal is received in response to influencing, outputs an alarm signal indicating an incorrect execution of the error detection functionality.
    Type: Grant
    Filed: January 12, 2007
    Date of Patent: December 23, 2014
    Assignee: Infineon Technologies AG
    Inventors: Marcus Janke, Peter Laackmann
  • Patent number: 8914682
    Abstract: The present invention enables a safety management of safety measures as well as the non-destructive testing of safety-relevant registers which are required for the configuration of a system, wherein the test method according to the invention can be carried out during each operating phase of a system to be tested.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: December 16, 2014
    Assignee: Infineon Technologies AG
    Inventor: Holger Busch
  • Patent number: 8904226
    Abstract: A method begins by a processing module identifying a set of stored files that includes an original file and one or more back-up copies of the original file. The method continues with the processing module dispersed storage error encoding one of the set of stored files to produce a plurality of sets of encoded data slices. The method continues with the processing module facilitating storage of the plurality of sets of encoded data slices. The method continues with the processing module facilitating deletion of the set of stored files.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: December 2, 2014
    Assignee: Cleversafe, Inc.
    Inventors: Jason K. Resch, Gary W. Grube, Timothy W. Markison
  • Patent number: 8886999
    Abstract: A low cost error-based program testing apparatus and method are provided. The testing apparatus according to an embodiment of the present invention generates error programs by adding errors to a test target program, selects a test target error program associated with test data among the error programs using error information obtained through the error addition, receives the test data to execute the test target error program, and tests for presence/absence of the errors. Accordingly, it is possible to reduce a text execution time and testing costs.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: November 11, 2014
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Yu-Seung Ma, Seon-Tae Kim
  • Patent number: 8880619
    Abstract: A communications system includes a network engine that communicates with a plurality of a user subscribed mobile wireless communications devices via a communications network for sending and receiving emails. A direct access server is connected to the network engine for polling electronic mailboxes of users from an email source and retrieving electronic messages from the electronic mailboxes and pushing any electronic mailboxes to the network engine to selected users subscribed mobile wireless communications devices. The direct access server communicates with an email source using the internet message access protocol (IMAP) and IMAP-Idle supportable connections in a communications channel to accept real-time notifications. The direct access server verifies an Idle command functionality on the communications channel before relying on the communications channel for new mail notifications.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: November 4, 2014
    Assignee: BlackBerry Limited
    Inventor: Matthew Van Wely
  • Patent number: 8868989
    Abstract: A system for testing an error detection circuit includes a fault injection unit for operating the error detection circuit in a fault injection mode. A fault is inserted in either of a primary or a redundant processor. Output signals generated by the primary and redundant processors are compared and checked for a mismatch and the error detection circuit outputs a test signal based on the comparison result.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: October 21, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Amit Jindal, Nitin Singh
  • Patent number: 8856592
    Abstract: A system and method is provided for providing assured recovery for a distributed application. Replica servers associated with the distributed application may be coordinated to perform integrity testing together for the whole distributed application. The replica servers connect to each other in a manner similar to the connection between master servers associated with the distributed application, thereby preventing the replica servers from accessing and/or changing application data on the master servers during integrity testing.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: October 7, 2014
    Assignee: CA, Inc.
    Inventors: Hailin Peng, Zhenghua Xu, Victor Liu
  • Patent number: 8843786
    Abstract: An apparatus comprising an initiator circuit and a target circuit. The initiator circuit may be configured to (i) communicate with a network through a first interface and (ii) generate testing sequences to be sent to the network. The target circuit may be configured to (i) receive the testing sequences from the network through a second network interface and (ii) respond to the testing sequences.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: September 23, 2014
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Mahmoud K. Jibbe, Prakash Palanisamy
  • Patent number: 8839042
    Abstract: A system, apparatus, method, and computer program product for dynamically loading IT products and scaling those loads in a predictive manner are disclosed. Dynamic loading and scaling is performed by generating a load on a computing product with one or more first load generators, increasing the load over time until the first load generators reach their capacity for generating load, monitoring the capacity of the first load generators as the load is increased, provisioning one or more second load generators to generate additional load as any of the first load generators approaches its capacity, increasing the load generated by the second load generators over time until the one or more second load generators reach their capacity for generating load or the computing product reaches a performance goal, and continuing to provision second load generators until the computing product reaches the performance goal.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: September 16, 2014
    Assignee: CA, Inc.
    Inventors: Cameron David Bromley, John Joseph Michelsen, III, Ricardo Emilio Denis
  • Publication number: 20140189432
    Abstract: A Remote Metadata Center provides Distaster Recovery (DR) testing and metadata backup services to multiple business organizations. Metadata associated with local data backups performed at business organizations is transmitted to the Remote Metadata Center. Corresponding backup data is stored in a data storage system that is either stored locally at the business organization or at a data storage facility that is at a different location than the Remote Metadata Center and the business organization. DR testing can be staged from the Remote Data Center using the metadata received and optionally with assistance from an operator at the business organization and/or the data storage facility.
    Type: Application
    Filed: March 6, 2013
    Publication date: July 3, 2014
    Applicant: COMMVAULT SYSTEMS, INC.
    Inventors: Parag Gokhale, Sanjay Harakhchand Kripalani
  • Patent number: 8707084
    Abstract: A data center management unit (DCMU, 100) for managing and controlling power distribution to computers in a data center, includes a power inlet (101), a plurality of power outlets (111, 112, 113, 114, 115, 116, 117, 118) for providing power to respective ones of the computers, a processor (141), at least one wired data port (151, 152, 153, 154) for controlling one or more of the computers, and a network interface (155) enabling a data center administrator to manage the data center management unit (DCMU, 100) remotely via wired network connectivity. In addition the data center management unit (DCMU, 100) contains a redundant meshed wireless network interface (156). The data center management unit (DCMU, 100) is adapted to automatically switch to the redundant meshed wireless network interface as an alternative for the network interface (155) in situations where the wired network connectivity is lost.
    Type: Grant
    Filed: August 12, 2010
    Date of Patent: April 22, 2014
    Assignee: Racktivity NV
    Inventors: Wilbert Ingels, Niko Vinken
  • Patent number: 8707104
    Abstract: Embodiments of the solid-state storage system provided herein are configured to perform improved mechanisms for testing of error recovery of solid state storage devices. In some embodiments, the system is configured to introduce or inject errors into data storage commands or operations performed in the non-volatile memory. Injected errors include corruption of data stored in the non-volatile memory, deliberate failure to execute storage operations, and errors injected into communication protocols used between various elements of the device. In some embodiments, injected errors can include direct errors that trigger an immediate execution of error recovery mechanisms and delayed errors that trigger execution of error recovery mechanisms at a later time. Error recovery mechanisms can be tested in an efficient, reliable, and deterministic manner to help ensure effective operation of storage devices. The integrity of non-volatile memory can also be tested.
    Type: Grant
    Filed: November 15, 2011
    Date of Patent: April 22, 2014
    Assignee: Western Digital Technologies, Inc.
    Inventor: Sebastien A. Jean
  • Patent number: 8700946
    Abstract: A recover to cloud (R2C) service replicates a customer production environment to virtual data centers (VDCs) operated in a cloud service provider environment. Customers provision both a disaster recovery VDC and a test VDC. At A Time of Disaster (ATOD), the disaster VDC is made available to the customer through the cloud. The disaster VDC is allocated a first set of resources dedicated to the specific customer and to disaster recovery. The test VDC, brought on line at A Time of Test (ATOT), is allocated resources from second set of resources arranged in a shared pool, separate from the first set. Provisioning of the test VDC does not disturb critical resource assignments needed in the event of a disaster.
    Type: Grant
    Filed: October 27, 2011
    Date of Patent: April 15, 2014
    Assignee: SunGard Availability Services, LP
    Inventors: Chandra Reddy, Enyou Li
  • Patent number: 8689206
    Abstract: A continuously operating system is provided and includes a processor and a computer readable medium to which the processor is operatively coupled, the computer readable medium having executable instructions stored thereon which, when executed, cause the processor to continuously load an operating system and to simultaneously operate as at least first and second mechanisms. The first mechanism loads a new module, which is a new version of an in-memory module of the operating system, into the operating system, and the second mechanism isolates and interrupts current access to the in-memory module such that subsequent access is to the new module.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: April 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Eli M. Dow, Marie R. Laser, Jessie Yu
  • Patent number: 8645797
    Abstract: In one embodiment, a processor includes error injection circuitry separate and independent of debug circuitry of the processor. This circuitry can be used by a software developer to seed errors into a write-back path to system memory to emulate errors for purposes of validation of error recovery code of the software. The circuitry can include a register to store an address within the system memory at which an error is to be injected, a detection logic to detect when an instruction associated with the address is issued, and injection logic to cause the error to be injected into the address within the system memory responsive to the detection of the instruction. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: February 4, 2014
    Assignee: Intel Corporation
    Inventors: Theodros Yigzaw, Yen-Cheng Liu, Mohan J. Kumar, Jose A. Vargas
  • Patent number: 8645765
    Abstract: Method embodiments for triggering error injection into a function under test using a serialization resource are provided. A test process invokes the function under test immediately after relinquishing exclusive control of the serialization resource. An error-injection process injects the error into the running function after gaining exclusive control of the serialization resource from the test process. The error-injection process may add a delay to inject the error. If the processes are repeated, the error-injection process may vary the delay, perhaps randomly, over a specified time window to thoroughly exercise the function's error recovery routine.
    Type: Grant
    Filed: October 5, 2011
    Date of Patent: February 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Joel Leslie Masser, Eileen Patricia Tedesco
  • Patent number: 8645766
    Abstract: System, and computer program product embodiments for triggering error injection into a function under test using a serialization resource are provided. A test process invokes the function under test immediately after relinquishing exclusive control of the serialization resource. An error-injection process injects the error into the running function after gaining exclusive control of the serialization resource from the test process. The error-injection process may add a delay to inject the error. If the processes are repeated, the error-injection process may vary the delay, perhaps randomly, over a specified time window to thoroughly exercise the function's error recovery routine.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: February 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Joel L. Masser, Eileen P. Tedesco
  • Patent number: 8627163
    Abstract: Improved apparatus, systems and methods, such as those for testing an error correction code (ECC) encoder/decoder for solid-state memory devices, are provided. In one or more embodiments, the improved systems and methods deliberately inject errors into memory storage areas of memory devices to test the operation of the ECC encoder/decoder.
    Type: Grant
    Filed: March 25, 2008
    Date of Patent: January 7, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Yutaka Ito, Adrian Drexler, Brandi Jones
  • Publication number: 20130339800
    Abstract: A failover guaranty estimator module performs a proof by contradiction method showing that a cluster failover guaranty can be met for the cluster. For potential failures for which failover is guaranteed, the method assumes a particular host set of one or more hosts fails, leaving one or more working hosts. The method performs a per-failure host set method for the failure host set. The per-failure host set method determines an amount of memory usage within each working host of the assumed working host set that would guaranty that a largest of the virtual machines in the failure host set would be orphaned. The per-failure host set method determines if the virtual machines in the failure set, other than the largest virtual machine in that set, would force the determined amount of memory usage within working hosts, resulting in, the failover guaranty not being met.
    Type: Application
    Filed: June 13, 2012
    Publication date: December 19, 2013
    Applicant: Microsoft Corporation
    Inventor: Hilton Arnold Lange