Abstract: Methods and apparatus, including computer program products, implementing and using techniques for testing a data service on a computing cluster having several computing nodes. A test package is installed on a test administration machine and on one or more of the computing nodes in the computing cluster. Data service configuration information is collected for the data service to be tested. Computing cluster configuration information is collected. The data service configuration information and the computing cluster configuration information are distributed to one or more of the computing nodes in the computing cluster. The data service is tested on the computing cluster by applying one or more data service test suites in the test package to the data service. A report containing results of the application of one or more of the data service test suites to the data service is generated.

Abstract: An integrity verification manager (101) verifies the integrity of a backup (102) of a computer (103). The integrity verification manager (101) audits the computer (103), and stores information (107) concerning items of interest such as executing processes (109, 111) and open listening ports (113). The integrity verification manager (101) restores a backup (102) of the computer (103) to a virtual machine environment. The integrity verification manager (101) audits the restoration of the backup (102) in the virtual machine environment, and compares audit information (107) concerning the restoration to the stored audit information (107). Responsive to the results of the comparison, the integrity verification manager (101) determines whether the restoration succeeded or failed.

Abstract: A method of controlling a system is provided in which a control-data table is employed for facilitating operation of the system, and an inject-fault-data table is selectively used during testing of the system. Pursuant to the method, a security mechanism is provided to restrict the system's utilization of the inject-fault-data table. A security check by the security mechanism is to be satisfied for the system to access the inject-fault-data table. In an enhanced embodiment, the system is tested by substituting an inject-fault-data entry of the inject-fault-data table for a control-data entry of the control-data table as an input to the system. The testing verifies the response of the system to an emulated fault, which results from employing at least one inject-fault-data entry during testing of the system.

Abstract: A system and method is disclosed for performing error recovery in a data processing system that supports multiple processing partitions. One or more processors and I/O modules, as well as a portion of the address space of a main memory, is allocated to each partition. In this type of configuration, requests generated by units of multiple partitions are processed by the same queue and state logic of the main memory. When a failure occurs within one processing partition, one or more units are identified as being directly affected by the fault. All requests and responses from, and to, the affected units, as well as any logical residue of these requests and responses are removed from the shared memory queue and state logic in a manner that allows the other partition to continue issuing requests and responses to the memory in a normal manner that does not involve recovery operations.

Abstract: An error handling method is provided for processing adapter errors. Rather than executing a disruptive controller hardware reset, an error handling routine provides instructions for a reset operation to be loaded and executed from cache while the SDRAM is in self-refresh mode and therefore unusable.

Abstract: In a database system having a primary server side (10) and a secondary server side (30), a high availability data replicator (26, 46) transfers log entries from the primary side (10) to the secondary side (30) and replays the transferred log entries to synchronize the secondary side (30) with the primary side (10). R-tree index transfer threads (54, 56) copy user-defined routines, the user defined index, and index databases deployed on the primary server side (10) to the secondary server side (30) and deploy the copied user-defined routines, reconstruct the user-defined index, and copy data pages on the secondary side (30) to make the user-defined index consistent and usable on the secondary side (30).

Abstract: In one embodiment, and under control of resources belonging to a controller domain of a data center, a farm server for which a backup operation is to be performed is identified. Interfaces of backup services belonging to the controller domain are then virtually associated with the first farm network. Thereafter, the farm server and backup services are registered in a backup domain of the data center, the backup domain being associated with backup storage. Via the backup services that have been associated with the first farm network, and during execution of the backup operation by the farm server, movement of backup data from the first farm network to the backup storage is facilitated by the method. After completing the backup operation, the farm server and backup services are un-registered from the backup domain, and the interfaces of the backup services are de-associated from the first farm network.

Abstract: A method and system are disclosed for fault injection using Boundary Scan resources compliant with 1149.1, while operating in system mode. The system has two register circuits, one, for storing and updating fault selection data and another, for storing and updating fault injection values.

Abstract: Generating a protected content stream from a data stream provides enhanced security in short-range wireless communications networks. This protected content stream is transmitted across a first short-range communications link. In addition, information for converting the protected content stream into the data stream is transmitted across a second link. The first link may be an ultra wideband (UWB) link, while the second link may be a Bluetooth link.

Abstract: An information system is provided including a server, a data storage device and a connection device; and is characterized in that the connection device includes a memory unit for storing a test list in which are associated information identifying the data storage device to be tested and setting information relating to tests; and a test unit which upon input of the input/output request, references the test list and judges whether the destination of the input/output request is the data storage device to be tested, and if the destination of the input/output request is the storage device to be tested, outputs the input/output request to the transmission/reception unit after a prescribed length of time.

Abstract: In one embodiment of the present invention, a wireless platform may be managed by an operations, administration, and maintenance system which may include a configuration manager, a performance manager, an accounting manager, a fault manager, an event manager, and a notification manager.

Abstract: The invention relates to a system and method for facilitating programmable coverage domains for test case generation, feedback, and measurement. The system comprises a domain definition input file; user-defined coverage domain data entered into the domain definition input file; and a parser operable for translating the user-defined coverage domain data into machine-readable computer program code. The system further includes an internal coverage domain comprising: a union of enabled coverage domains extracted from the user-defined coverage domain data; a session component comprising a session update count for each domain element; and a history component comprising a history update count for each domain element. The system further comprises a testcase generator including an internal coverage feedback and measurement system.

Abstract: Methods are provided for testing storage devices and related devices for use in a clustered system. Storage devices may be pre-qualified before cluster software is installed for controlling the clustered system. Some implementations allow one or more storage devices in a cluster to be automatically tested in a variety of fault and non-fault scenarios.

Abstract: A method for identifying, managing, and signaling uncorrectable errors among a plurality of clusters of symmetric multiprocessors (SMPs) detects, manages and reports data errors. The method allows merging of newly detected errors, including memory, cache, control, address, and interface errors, into existing error status. Also, error status is distributed in several possible formats, including separate status signals, special UE (uncorrectable errors) ECC codewords, encoded data patterns, parity error injection, and response codepoints. The error status is also available for logging and analysis while the machine is operating, allowing for recovery and component failure isolation as soon as the errors are detected without stopping the machine.

Abstract: Techniques and devices are provided for injecting transactions within computer systems having a plurality of multi-processor clusters. Each cluster includes a plurality of nodes, including processors, a service processor and an interconnection controller interconnected by point-to-point intra-cluster links. The processors and the interconnection controller in each cluster make transactions via an intra-cluster transaction protocol. Inter-cluster links are formed between interconnection controllers of different clusters. Each of the processors and the interconnection controller in a cluster has a test interface for communicating with the service processor. The service processor is configured to make an injected transaction according to the intra-cluster transaction protocol via one of the test interfaces.

Abstract: An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.

Abstract: The present invention is directed to a system, method and software product for balancing resource services are always available to match the desired work to be done through the use of “sticky services.”. Sticky services are defined as services that you know you want to have available as resources and as such they need to be present in the environment of cooperative applications; it may be that you want these always present or it may be that you want them present whenever certain conditions occur (see NewWave policy service). The general assumption of distributed systems is to not count on the environment you want being present, or put another way assume failure will occur. Therefore distributed environments like Jini assume all services are transient and will be garbage collected when not in active use. For the inside out approach to work, a mechanism should exist that, when desired, counters the transit design assumptions.

Abstract: There is provided a high-availability duplexing or multiplexing information recorder where a process is not interrupted by a trouble of a drive or a medium. The information recorder is directed to write data instructed to be written from a host system in recording media of at least two drives. The recorder is configured to: detect an abnormality of each drive itself and an abnormality of the recording medium of each drive; cancel the writing of the data in the recording medium of the drive where an abnormality is detected or the drive having the recording medium where an abnormality is detected; and continue the writing of the data in the recording medium of the following drive without notifying any abnormality to the host system, as long as there is at least one drive where any abnormality is not detected and which has the recording medium where any abnormality is not detected.

Abstract: A method of verifying a monitoring and responsive infrastructure of a system is provided and described. The method includes setting a sensor to a simulation mode. Further, a test value is provided to simulate a real value outputted by the sensor. While in the simulation mode, the test value instead of the real value is sent to the monitoring and responsive infrastructure to invoke a response. Moreover, the response to the test value is verified. In an embodiment, the monitoring and responsive infrastructure is compliant with an Intelligent Platform Management Interface specification.

Abstract: A method of testing a target in a network by fault injection, includes: defining a transaction baseline; modifying at least one of an order and a structure of the transaction baseline to obtain a modified transaction with malformed grammar; and transmitting the modified transaction to a target. The method may further include, receiving a feedback from the target to determine fault occurrence. An apparatus for testing a target in a network by fault injection, includes: a driver configured to generate patterns, where a pattern can generate a plurality of packets for transmission to the target, the pattern being represented by an expression with a literal string and a wild character class; and a network interface coupled to the driver and configured to transmit and receive network traffic.

Abstract: The present invention provides a method and apparatus for synchronizing errors in a processor-based system. The method includes forming a sequence of a plurality of language elements, wherein the language elements are adapted to create errors in a system. The method further includes providing the sequence to the system.

Abstract: Various systems and methods for testing one or more servers using a distributed test system may involve a master agent synchronously transitioning multiple test agents through several state changes. In some embodiments, a method may involve configuring multiple test agents to execute a test by initiating a state change to a first state at each of the test agents. Each of the test agents is prepared to execute the test when in the first state. Each of the test agents simulates multiple clients of a server under test when executing the test. In response to each of the test agents confirming the state change to the first state, a state change to a second state may be initiated at each of the plurality of test agents. Each of the test agents executes the test when in the second state.

Abstract: A cache is configured to receive direct access transactions. Each direct access transaction explicitly specifies a cache storage entry to be accessed in response to the transaction. The cache may access the cache storage entry (bypassing the normal tag comparisons and hit determination used for memory transactions) and either read the data from the cache storage entry (for read transactions) or write data from the transaction to the cache storage entry (for write transactions). The direct access transactions may, for example, be used to perform testing of the cache memory. As another example, direct access transactions may be used to perform a reset of the cache (by writing known data to each cache entry). In embodiments employing error checking and correction (ECC) mechanisms, direct access write transactions could also be used to recover from uncorrectable ECC errors, by overwriting the failing data to eliminate the errant data.

Abstract: An image processing apparatus that is connected to a network generates information about a processing time expected to be required for rewriting firmware in the image processing apparatus to new firmware, and transmits the information via the network to an external apparatus.

Abstract: A system maintains a copy of data stored in a first memory device in a redundant distinct second memory device. Upon detecting an uncorrectable error in the first memory device, the system then relies on the copy of the data in the second memory device. The system, once it starts relying on the data in the second memory device, may then test the first memory device to determine if the uncorrectable error was due to a physical problem or a transient event. If the first memory device is then found to be working correctly, it may, in turn, become a redundant memory device for the second memory device.

Abstract: A storage system includes a group of storage devices which include back-up devices configured to assure appropriate response time. When a data request from a host computer arrives, and the number of failed devices has changed as shown by a device state management table, a determination is made regarding the number of devices from which to read data. This determination is made based on an indication of redundancy which indicates how many of the disk devices are allowed to be in a failed state at the time of data reading. Typically, the indication of redundancy is determined by the sum of the number of failed devices and a predetermined number. The determined number of devices are selected in accordance with a selection factor, and a selection result is written into a disk management table. Then, the reading process is executed with respect to the target disk devices.

Abstract: The snapshot capability moving into the SAN fabric and being provided as a snapshot service. A well-known address is utilized to receive snapshot commands. Each switch in the fabric connected to a host contains a front end or service interface to receive the snapshot command. Each switch of the fabric connected to a storage device used in the snapshot process contains a write interceptor module which cooperates with hardware in the switch to capture any write operations which would occur to the snapshot data area. The write interceptor then holds these particular write operations until the original blocks are transferred to a snapshot or separate area so that the original read data is maintained. Should a read operation occur to the snapshot device and the original data from requested location has been relocated, a snapshot server captures these commands and redirects the read operation to occur from the snapshot area.

Abstract: A diagnostic unit which detects instances of misconfiguration of a subscriber's PC is presented. Many problems experienced by PC subscribers attempting to access a network are related to misconfiguration of the subscriber's PC. The diagnostic unit is able to communicate with the subscriber's misconfigured PC through Fault Tolerant Protocol stacks. The diagnostic unit emulates services such as log-in, authentication, e-mail and the Internet to the subscriber. The diagnostic unit examines the traffic sent by the subscriber to detect instances of misconfiguration and reports the detected configuration of the subscriber's PC.

Abstract: A microprocessor 20a controls an electrical load group 12 responsive to content of a non-volatile program memory 25a and operation state of an input sensor group 11. A monitoring control circuit section 30a sequentially transmits a large number of question items with an inquiry packet, and compares response content from the microprocessor 20a with correct answer information to carry out an error determination. The microprocessor 20a diagnoses an interval of receiving an inquiry packet to monitor in reverse the monitoring operation of the monitoring control circuit section 30a. Thus, in an electronic control unit having a microprocessor built-in, a monitoring control circuit is obtained that alternatively executes at regular intervals a part of control programs to carry out operation inspection during operation.

Abstract: An error response test system and method with increased functionality and improved performance is provided. The error response test system provides the ability to inject errors into the application under test to test the error response of the application under test in an automated and efficient manner. The error response system injects errors into the application through a test mask variable. The test mask variable is added to the application under test. During normal operation, the test mask variable is set to allow the application under test to operate normally. During testing, the error response test system can change the test mask variable to introduce an error into the application under test. The error response system can then monitor the application under test to determine whether the application has the correct response to the error.

Abstract: A host is coupled to a cluster interconnection fabric which includes a fabric-attached I/O controller. The host includes a processor, a memory coupled to the processor and an operating system. The operating system includes a kernel and a fabric bus driver to provide an I/O bus abstraction to the kernel for the cluster interconnection fabric. The fabric bus driver presents the cluster interconnection fabric to the kernel as a local I/O bus, and presents the fabric-attached I/O controller to the kernel as a local I/O controller attached to a local I/O bus.

Abstract: A desired level of failover in a system is ensured by (i) capturing information about elements, such as components, modules, sub-systems, data, programs, routines, and/or information, etc. (referred to generally as “elements”), (ii) determining whether failover is compromised to an unacceptable degree, and (iii) persistently reporting compromised failover until proper remedial actions are taken.

Abstract: A system is disclosed in which an on-chip logic analyzer (OCLA) is included in an integrated circuit, such as a microprocessor. During debug modes, one or more sets of an on-chip cache memory are disabled from use by other circuitry in the integrated circuit, and reserved exclusively for use by the OCLA. Data stored in the reserved cache set can then be read out by the OCLA, and placed in a register that can be accessed by other logic internal or external to the integrated circuit. If the integrated circuit is operating under normal mode, the cache memory set can be used in conventional fashion by other circuitry with in the integrated circuit to enhance performance.

Abstract: A cable isolator is provided for automatically performing cable breaks for testing of host bus adapters. A workstation includes a host bus adapter, such as a Fibre Channel storage controller, to be tested. The host bus adapter is connected to one or more storage modules through the cable isolator. The cable isolator includes two transceivers, one of which is connected to the host bus adapter and the other being connected to the storage modules. The two transceivers are also connected to each other internally. The cable isolator also includes a programmable logic device or controller that is used to enable and disable the two transceivers at set intervals. The one or more output disable signals are then provided to the transceivers to perform the cable break. The cable isolator may be an expansion card installed within the workstation. Thus, the workstation may communicate with the cable isolator through an expansion bus.

Abstract: A system evaluates a data cleansing application. The system includes a collection of records cleansed by the data cleansing application, a plurality of dirtying functions for operating upon the collection to introduce errors to the collection, and a record of the errors introduced to the cleansed collection. The plurality of dirtying functions produces a collection of dirty records.

Abstract: The system and methods described herein relate to testing and verifying the fault tolerance in fault tolerant systems. Fault logic integrated into a fault tolerant system permits automated testing of fault paths in system firmware and hardware dedicated to handling fault scenarios. Advantages of the disclosed system and methods include the ability to inject errors without the need to modify system firmware or hardware. Errors can be injected in a controlled manner and asynchronously to normal system firmware execution which permits improved coverage of firmware error paths. The automated error injection capability disclosed is applicable in both the development and production of fault tolerant systems.

Abstract: A cable isolator is provided for automatically performing cable breaks for testing of host bus adapters. A workstation includes a host bus adapter, such as a Fibre Channel storage controller, to be tested. The host bus adapter is connected to one or more storage modules through the cable isolator. The cable isolator includes two transceivers, one of which is connected to the host bus adapter and the other being connected to the storage modules. The two transceivers are also connected to each other internally. The cable isolator also includes a programmable logic device or controller that is used to enable and disable the two transceivers at set intervals. When the cable connection is to be broken, the programmable logic device generates one or more output disable signals. The one or more output disable signals are then provided to the transceivers to perform the cable break. An on-time and an off-time may be set using switches or dials.

Abstract: The invention provides a method and system for persistent context-based behavior injection in a computing system, such as in a redundant storage system or another system having a layered or modular architecture. Behaviors that are injected can be specified to have triggering conditions, such that the behavior is not injected unless the conditions are true. Triggering conditions may include a selected ordering of conditions and a selected context for each behavior. In a system having a layered architecture, behavior injection might be used to evaluate correct responses in the face of cascaded errors in a specific context or thread, other errors that are related by context, concurrent errors, or multiple errors. Behavior injection uses non-volatile memory to preserve persistence of filter context information across possible system errors, for reporting of the results of behavior injection, and to preserve information across recovery from system errors. Multiple behavior injection threads are also provided.

Abstract: An integrated circuit (IC) and methods of manufacturing and operating ICs. In one embodiment, the IC includes: (1) a plurality of interchangeable hard macrocells, (2) at least one programmable logic block (PLB), (3) a bus intercoupling said plurality and said at least one programmable logic block and (4) a self-repair program, associated with said at least one programmable logic block, that causes said PLB to test at least some of said plurality and place at least a functioning one of said plurality into an operational status.

Abstract: A test mechanism for testing device driver hardening includes an intercept mechanism for intercepting device driver access calls from a device driver under test and an interface for configuring the intercept mechanism to inject faults according to a determined test pattern. This mechanism enables the arbitrary introduction of typical faults. These faults may be introduced totally asynchronously and so emulate real life. A test harness module can be linked in to a test build of the driver. The test harness can intercept all of the device access calls. It mimics the normal function of these calls accessing the offset address and propagating the appropriate data. A test application is able to interpret a test script and to compare device driver responses to injected faults.

Abstract: A storage assembly includes a plurality of multi-unit storage device is provided with a failover procedure that does not require hot-swap capability. Individual units are aggregated into a storage array by an aggregation procedure such as RAID. When a failure occurs data from the failed unit is transferred to a hot spare unit. Also, data from other units is transferred by simulating failure of those units and then the complete device can be removed. In small storage networks all the units may be aggregated as a single array and a spare auxiliary device is summoned and integrated into the array prior to the simulated failure. In larger systems there may be two layers of aggregation and failover is run by the second level of aggregation.

Abstract: A method of verifying that a disc recording and reproducing apparatus normally analyzes defect management area (DMA) information in a read or write mode, and a test apparatus for performing the method. The method includes operating the recording and reproducing apparatus in a read or write mode, using a test disc with test reference information, and checking whether the recording and reproducing apparatus operates in the read or write mode to verify the DMA information analyzing function of the recording and reproducing apparatus. Accordingly, a DMA information analyzing function of the disc recording and reproducing apparatus in the read or write mode can be tested.

Abstract: A network probe inserted between two nodes in point-to-point link synchronizes modes of operation between the two nodes. The probe utilizes IEEE 802.3u Clause 28 Auto-Negotiation to detect and advertise corresponding information regarding modes of operation for the nodes between which it is inserted in the point-to-point link, to achieve a highest priority common mode of operation between the nodes.

Abstract: A microprocessor runaway monitoring control circuit with which self-diagnosis of a watchdog timer WDT can be carried out safely and cheaply even during operation of the microprocessor (CPU). A microprocessor 101 supplies first and second watchdog clearing signals WD1 and WD2 to first and second watchdog timers WDT1 and WDT2, and when the both of the watchdog clearing signals WD1 and WD2 stop, the microprocessor 101 is reset by way of a logical connector circuit 122. The microprocessor 101 has failure diagnosing means 103 which intentionally stops the first watchdog clearing signal WD1 and diagnoses the response of the first watchdog timer WDT1 on the basis of a monitor signal MN1 and stops the second watchdog clearing signal WD2 and diagnoses the response of the second watchdog timer WDT2 on the basis of a monitor signal MN2, whereby diagnosis of the watchdog timers WDT1, WDT2 is carried out without the microprocessor 101 being stopped.

Abstract: The present invention is an I2C (inter-IC control) bridge device which implements a communication protocol layered on top of a standard I2C protocol. The layered protocol used by the bridge device is termed the “Layered I2C Protocol”—abbreviated “LIP”. Thus the bridge device is called a “LIP bridge device”. The LIP bridge device provides I2C address extension, data integrity checking, and fault detection and isolation when inserted between an I2C bus master and it's intended target I2C device. Each LIP bridge device has at least two attached I2C busses—a parent bus and a child bus. The LIP bridge operates as a slave on its parent bus, and a master of its child bus. The Layered I2C protocol is specified to operate on a bus between one or more bus masters and the parent bus of one or more LIP bridge devices. The child bus is used for attaching multiple I2C devices and/or one or more LIP bridge devices.

Abstract: A simulation system simulates an operation of a memory. This system includes an error generating step in addition to a memory operation simulating step. An error can easily be generated in a read/write operation of a memory model only by setting a memory address. A set of free bits, which is not used for the simulation of a memory operation, is used as a memory address for indicating the error generation. It is thus unnecessary to prepare a new description of a signal line exclusively for indication of error generation and it is possible to simulate a memory operation containing an error only by the normal descriptions of an address, data, and the like.

Abstract: A flat panel display system for an aircraft display includes a graphics rendering computer for rendering of anti-aliased graphical imaging data derived from aircraft sensors for full-field imaging on a cockpit display screen. A comparator processor independently generates, from the same sensor data, a selected subset or “points of light” of the display screen image and compares the points of light data to the data generated by the rendering computer for the same display screen pixel locations. The minimized processing requirements and simplified design of the comparator processor enable ready FAA certification of the comparator processor, whereas the extreme complexity and processing operations required of the rendering computer make FAA certification thereof unusually time consuming and expensive.

Abstract: Reliability and robustness of a cluster having a host connected thereto via a cluster interconnection fabric may be enhanced by determining if an error condition exists in an I/O controller connected to the host via the cluster interconnection fabric by attempting to communicate with it a first predetermined time period after an inquiry by an operating system as to whether or not an I/O controller driver stack should be unloaded and commanding the operating system to unload the I/O controller driver stack upon a determination that the error condition still exists. The determination as to whether the error condition still exists may be repeated a predetermined number of times prior to commanding the unloading of the I/O controller driver stack upon a determination that the error condition still exists.

Abstract: A multiprocessor system is disclosed that employs an apparatus and method for caging a redundant component to allow testing of the redundant component without interfering with normal system operation. In one embodiment the multiprocessor system includes at least two system controllers and a set of processing nodes interconnected by a network. The system controllers allocate and configure system resources, and the processing nodes each include a node interface that couple the nodes to the system controllers. The node interfaces can be individually and separately configured in a caged mode and an uncaged mode. In the uncaged mode, the node interface communicates information from either of the system controllers to other components in the processing node. In the caged mode, the node interface censors information from at least one of the system controllers.

Abstract: A system and method for selectively injecting parity errors into instructions of a data processing system when the instructions are copied from a read buffer to a first level cache. The parity errors are selectively injected according to programmable indicators, each programmable indicator being associated with one or more instructions stored in the read buffer. The error-injection system also includes programmable operating modes whereby error injection will occur during, for example, every copy back from the read buffer to the first level cache, or alternatively, during only a selected copy back sequence. The system allows for comprehensive testing of error detection and recovery logic in an instruction processor, and further allows for comprehensive testing of the logic associated with performing a data re-fetch from a second level cache or storage device.