Abstract: Disclosed are embodiments of a method and an associated first system for extending product life of a second system in the presence of phenomena that cause the exhibition of both performance degradation and recovery properties within system devices. The first system includes duplicate devices incorporated into the second system (e.g., on a shared bus). These duplicate devices are adapted to independently perform the same function within that second system. Reference signal generators, a reference signal comparator, a power controller and a state machine, working in combination, can be adapted to seamlessly switch performance of that same function within the second system between the duplicate devices based on a measurement of performance degradation to allow for device recovery. A predetermined policy accessible by the state machine dictates when and whether or not to initiate a switch.

Abstract: A method secures a memory in which individually read-accessible binary words are saved. The method includes defining a memory zone covering a plurality of words, calculating a cumulative signature according to all of the words in the memory zone, and storing the cumulative signature as an expected signature of the memory zone to check the integrity of data read in the memory. The method can be applied to the securing of smart cards.

Abstract: A fault zone definition mechanism groups components of an interconnect environment having a common point of dependence into a logical group defining a fault zone for the interconnect environment. The fault zone definition mechanism may be implemented in software, firmware or hardware, or a combination of two or more of software, firmware and hardware. A method for defining a fault zone is also disclosed.

Abstract: An automated method for facilitating management of a data processing environment is disclosed. In various embodiments, the method may include facilitating creation of a first memorialization, in digital form, of one or more changes detected on a data processing device of the data processing environment. In various embodiments, the method may further included facilitating comparison of the first memorialization to a second memorialization of one or more in-band changes that should have been made to the data processing device to facilitate detection of one or more out-of-band changes to the data processing device. Other embodiments of the present invention may include, but are not limited to, apparatus adapted to facilitate practice of the above-described method.

Abstract: A method and apparatus for testing mathematical programs where code coverage is exceedingly difficult to hit with random data test vectors (probability <2?64) is provided. To enable testing of the mathematical program, instructions in the mathematical program are trapped. Errors are injected through the use of any status/control flag where an error can be created and be rectified later by a reversible operation so that the result of the mathematical operation is not modified by the injected error.

Abstract: A system and method for efficient uncorrectable error detection in flash memory is described. A microcontroller including a non-volatile flash memory utilizes an Error Correction Code (ECC) having a certain error detection and correction bit strength. The user data is first processed by a hash function and hash data is stored with the user data. Then, the user data and hash data are processed by the ECC system. In detection, the hash ensures that a relatively low bit-strength ECC system did not incorrectly manipulate the user data. Such a hash integrity check provides an efficient, robust detection of incorrectly corrected user data resulting from errors beyond the correction but strength of the ECC system utilized.

Abstract: SRAM macro sparing allows for full chip function despite the loss of one or more SRAM macros. The controls and data flow for any single macro within a protected group are made available to the spare or spares for that group. This allows a defective or failed SRAM macro to be shut off and replaced by a spare macro, dramatically increasing manufacturing yield and decreasing field replacement rates. The larger the protected group, the fewer the number of spares required for similar improvements in yield, but also the more difficult the task of making all the controls and dataflow available to the spare(s). In the case of the Level 2 Cache chip for the planned IBM Z6 computer, there are 4 protected groups with 192 SRAM macros per group. Each protected group is supplanted with an additional 2 spare SRAM macros, along with sparing controls and dataflow that allow either spare to replace any of the 192 protected SRAM macros.

Abstract: Data is transparently migrated between groups of logical units of storage presented as virtual arrays. A source virtual array has at least one source virtual port coupled to a fabric. Each source virtual port having a source virtual port name and a source virtual port address. A destination virtual array has one or more destination virtual ports coupled to the fabric, each destination virtual port having a destination virtual port name and a destination virtual port address. All data resident on the source virtual array is copied to the destination virtual array. The destination virtual port names and LUN names and numbers are then exchanged with the source virtual port names and LUN names and numbers. The fabric then updates its name server database so that the database associates the source virtual port name with the destination virtual port address.

Abstract: A method identifies, prior to runtime, a first device that is added to a system. Further, the method generates, prior to runtime, a statically precompiled database for the device that provides a first set of error handling data. In addition, the method identifies, during runtime, a second device that is added to the system. Finally, the method generates, during runtime, a dynamically allocated database for the second device that provides a second set of error handling data.

Abstract: A method and system for testing a semiconductor device is disclosed. The method provides an integrated test program defined by a plurality of test items, and a test program defined by a sub-set of the test items. Test data is derived by batch sample testing of the semiconductor device, and an error rate for a test item is computed and then compared to a reference data value. On the basis of the comparison between the error rate and the reference data value, the test program may be modified in real-time.

Abstract: In a first aspect, a first method of injecting one or more errors in data flowing into or out of a chip is provided. The first method includes the steps of (1) generating an error injection pattern indicating one or more bits of data on which a pseudo-random error is to be inserted; and (2) generating an error injection trigger indicating when the pseudo-random error is to be inserted. Numerous other aspects are provided.

Abstract: A method, apparatus, and computer program product are disclosed for testing a data processing system's ability to recover from cache directory errors. A directory entry is stored into a cache directory. The directory entry includes an address tag and directory parity that is associated with that address tag. A cache entry is stored into a cache that is accessed using the cache directory. The cache entry includes information and cache parity that is associated with that information. The directory parity is altered to imply bad parity. The bad parity implies that the address tag that is associated with this parity is invalid. The information included in the cache entry is altered to be incorrect information. However, although the information is now incorrect, the cache parity continues to imply good parity which implies that the data is good. This good parity implies that the information that is associated with the parity is valid, even though it is not.

Abstract: The snapshot capability moving into the SAN fabric and being provided as a snapshot service. A well-known address is utilized to receive snapshot commands. Each switch in the fabric connected to a host contains a front end or service interface to receive the snapshot command. Each switch of the fabric connected to a storage device used in the snapshot process contains a write interceptor module which cooperates with hardware in the switch to capture any write operations which would occur to the snapshot data area. The write interceptor then holds these particular write operations until the original blocks are transferred to a snapshot or separate area so that the original read data is maintained. Should a read operation occur to the snapshot device and the original data from requested location has been relocated, a snapshot server captures these commands and redirects the read operation to occur from the snapshot area.

Abstract: A method of testing a target in a network by fault injection, includes: defining a transaction baseline; modifying at least one of an order and a structure of the transaction baseline to obtain a modified transaction with malformed grammar; and transmitting the modified transaction to a target. The method may further include, receiving a feedback from the target to determine fault occurrence. An apparatus for testing a target in a network by fault injection, includes: a driver configured to generate patterns, where a pattern can generate a plurality of packets for transmission to the target, the pattern being represented by an expression with a literal string and a wild character class; and a network interface coupled to the driver and configured to transmit and receive network traffic.

Abstract: A method for identifying names of uninformative functions in call-stack traces is described. The method comprises the steps of obtaining a set of call-stacks and information indicative of which call-stack traces in the set match a particular call-stack trace; for each matching call-stack trace pair, incrementing a false negative counter for each function name above a first matching function name in a respective call-stack trace pair; for each non-matching call-stack trace pair, incrementing a false positive counter for each function name above a first non-matching function name in a respective call-stack pair; incrementing a frequency counter for each function name appearing in each of the call-stack traces; calculating an aggregate value for each of the function names as a function of respective ones of the false positive counter, the false negative counter and the frequency counter; and identifying uninformative ones of the function names based on the respective aggregate values.

Abstract: This disk array device having at least one volume that reads and writes data based on an access request transmitted from a client device via a server device, includes: a failure generation unit for generating a simulated failure in one's own device; an access request transmission unit for transmitting the access request transmitted from the client device to the server device; and a verification unit for verifying the setting of the server device regarding the response to the failure based on the response of the server to the access request transmitted from the access request transmission unit in a state of where the failure is being generated with the failure generation unit.

Abstract: In one embodiment of the present invention, a computing system includes a plurality of systems coupled in a distributed infrastructure, and a resource allocator to allocate activities of an application to at least two of the systems. The distributed infrastructure may be a tightly coupled infrastructure and may include a virtualized application environment that emulates a runtime environment of the application, in such an embodiment.

Abstract: A system and method for injecting hardware errors into a microprocessor system is described. In one embodiment, a software interface between system software and system firmware is established. Software test and debug for software error handlers may thus be supported. The software interface may support both a query mode call and a seed mode call. When a query mode call is issued, it may request whether or not the system firmware and hardware support the injection of a specified kind of error. A return from this call may be used to make a list of supported errors for injection. When a seed mode call is issued, the corresponding error may be injected into the hardware.

Abstract: The snapshot capability moving into the SAN fabric and being provided as a snapshot service. A well-known address is utilized to receive snapshot commands. Each switch in the fabric connected to a host contains a front end or service interface to receive the snapshot command. Each switch of the fabric connected to a storage device used in the snapshot process contains a write interceptor module which cooperates with hardware in the switch to capture any write operations which would occur to the snapshot data area. The write interceptor then holds these particular write operations until the original blocks are transferred to a snapshot or separate area so that the original read data is maintained. Should a read operation occur to the snapshot device and the original data from requested location has been relocated, a snapshot server captures these commands and redirects the read operation to occur from the snapshot area.

Abstract: A system includes a cluster having a plurality of nodes wherein at least one of the nodes is a candidate node, a plurality of resource groups, a clustering mechanism executing on the cluster configured to activate a first resource group of the plurality of resource groups on the candidate node, and a resource group affinity of the plurality of resource groups, wherein the resource group affinity comprises a unidirectional association between the first resource group of the plurality of resource groups and a second resource group of the plurality of resource groups.

Abstract: A technique for controlling a system is provided in which a control-data table is employed for facilitating operation of the system, and an inject-fault-data table is selectively used during testing of the system. Pursuant to the technique, a security mechanism is provided to restrict the system's utilization of the inject-fault-data table. A security check by the security mechanism is to be satisfied for the system to access the inject-fault-data table. In an enhanced embodiment, the system is tested by substituting an inject-fault-data entry of the inject-fault-data table for a control-data entry of the control-data table as an input to the system. The testing verifies the response of the system to an emulated fault, which results from employing at least one inject-fault-data entry during testing of the system.

Abstract: The invention relates to a method for monitoring the execution of a program in a microcomputer of an electronic device, especially a sensor circuit for motor vehicles. According to the inventive method, the program processes input data and produces output data, copies a program in addition to the program which is executed, said copy being stored in an address area in the micro-computer other than the program, using the input data provided for the program. The output data of the copy is compared to the data of the program and an error message is produced if the programs are not consistent.

Abstract: The present invention is directed to the quantitative measurement of the autonomic capabilities of computing systems. A method in accordance with an embodiment of the present invention includes: subjecting the computing system to a workload; injecting a disturbance into the computing system; providing a notification that the computing system has detected a problem in response to the injected disturbance; determining an amount of time required to initiate a recovery procedure to address the detected problem; and determining an amount of time required to execute the recovery procedure.

Abstract: A method is provided for injecting faults into an operational system containing software and hardware components to be tested. A fault injection routine is stored in a memory location of the system. An interrupt service routine, preferably operational during normal operation of the system is provided with a pointer to the fault injection routine. A fault injection routine is executed from within the interrupt service routine. In one embodiment, the interrupt service routine provides a clock or timing function. In another embodiment, a number of fault injection subroutines are accessible by the fault injection routine. A value is passed to the fault injection routine indicating the particular fault injection subroutine to be employed.

Abstract: A simulation system includes glitch injection circuitry in one or more hardware design units to allow the injection of glitches or noise to evaluate the system's response to errors on signals between the hardware design units. The simulation system includes a stimulation module with a set of drivers to input simulation patterns into the design units. Some inputs to software models are driven by the outputs of software models of another design unit. The stimulation module can monitor these signals driven by the software model but it is difficult for the stimulation module to directly drive these signals. The added glitch circuitry allows injection of errors into the simulated hardware by the stimulation module on signals that are not directly driven by the stimulation module but are driven by the outputs of hardware design units.

Abstract: A data-processing apparatus, method and program product generally include identifying one or more SAS expanders and one or more link thereof associated with an SAS domain of a data-processing apparatus. Link and reset data can be automatically injected onto the link(s) and the SAS expander(s) associated with the SAS domain, in response to identifying the SAS expander(s) and one or more links thereof. The presence of the link(s) within the SAS domain can then be verified, in response to automatically injecting the link and reset data onto one or more links and one or more SAS expanders in order to test the links and the SAS expanders associated with the SAS domain.

Abstract: An apparatus operable with a host and a data storage component for detecting a storage device susceptible to failure under I/O workload is provided. The apparatus includes a selector component for selecting a pair of storage devices in the data storage component. A data migration control component is provided for initiating migration of data from a first to a second storage device of the pair of storage devices. An I/O workload mirroring component is provided for mirroring an I/O workload from a first of the pair of storage devices to a second of the pair of storage devices. A storage device failure detecting component for detecting failure of one of the pair of storage devices is also included. The selector component further comprises a timer component for periodically initiating the selecting.

Abstract: The snapshot capability moving into the SAN fabric and being provided as a snapshot service. A well-known address is utilized to receive snapshot commands. Each switch in the fabric connected to a host contains a front end or service interface to receive the snapshot command. Each switch of the fabric connected to a storage device used in the snapshot process contains a write interceptor module which cooperates with hardware in the switch to capture any write operations which would occur to the snapshot data area. The write interceptor then holds these particular write operations until the original blocks are transferred to a snapshot or separate area so that the original read data is maintained. Should a read operation occur to the snapshot device and the original data from requested location has been relocated, a snapshot server captures these commands and redirects the read operation to occur from the snapshot area.

Abstract: A transmitting device generates a data block including a first field having a first plurality of bits that includes an error detection portion and a second field having a second plurality of bits; selects an error injection mask based on the second plurality of bits; modifies the first plurality of bits with the error injection mask to generate a modified first plurality of bits; and transmits the data block to a receiving device. The receiving device decodes the second plurality of bits to generate decoding results; selects an error injection mask based on the decoding results; modifies the first plurality of bits using the error injection mask to generate a modified first plurality of bits that includes a resultant error detection value indicated in the error detection portion; and detects whether the decoding results for the second field are correct based on the resultant error detection value.

Abstract: A computer system comprising a processor configured to cause an operating system to be booted, a test module, and a component coupled to the test module and configured to receive a clock input is provided. The test module is configured to cause the clock input to be provided to the component at a first frequency, and the test module is configured to cause a first test to be performed on the component subsequent to the clock input being provided to the component at the first frequency and the operating system being booted.

Abstract: A method and a system for implementing the method are disclosed relating to archival storage of information in large numbers of disk units. The reliability of the stored information is checked periodically using data verification operations whose results are saved. These results establish the veracity of the data and enable compliance with various regulatory requirements. The techniques described enable the use of low cost disk drive technology, yet provide high assurance of data veracity. In a typical system, management information storage is provided in which data entries are associated with each of the disk drives to provide information with respect to the condition of the data on that drive and its last verification. The data verification operations are performed on the data during time periods when I/O accesses are not required.

Abstract: When a testing system is connected to a debug port of a tape drive unit or a SCSI bus, a self-checking test for a fabricating process is executed. When the testing system is not connected, the self-checking test for normal operation is executed. And in a test of a single card, a motor test and an MR head resistance test, which are tests of a mechanical structure portion, are omitted. In addition, in a box assembling process, the test contents are suppressed to a minimum prior to adjustments to the, tape head. Furthermore, in a test program, the status of a flag or an indication corresponding to a test executed in a next step is changed.

Abstract: This embodiment replaces the use of LBIST to get a pass or no-pass result. A selective signature feature is used to collect the top failing paths, by shmooing the chip over a cycle time. These paths can be stored on-chip or off-chip, for later use. Once the chip is running in the field for a certain time, the same procedure is performed to collect the top failing paths, and this is compared with the stored old paths. If the order of the top paths changes, it indicates that (for example) there is a path (not the slowest path before) that slows more than others, which could be potential reliability concern. Therefore, a potential reliability failure is identified in the field.

Abstract: According to one embodiment, a method comprises intercepting, at an interposition agent, requests for accessing a data storage device. The method further comprises determining, by the interposition agent, at least one of the requests to impact, and selectively simulating, by the interposition agent, a fault for the selected at least one of the requests. According to another embodiment, a system comprises at least one data storage device, and at least one requester operable to request access to the at least one data storage device. The system further comprises at least one interposition agent communicatively interposed between the requestor(s) and the data storage device(s) to intercept requests for access from the requestor(s) to the data storage device(s), wherein the interposition agent is operable to selectively determine ones of the intercepted requests to impact and selectively simulate a fault for the selected at least one of the requests.

Abstract: Systems and methods are disclosed for parallel testing one or more wireless devices using a single wireless command, each device including a processor and memory coupled to the processor. The system includes a tester adapted to exercise the wireless devices, including: a transceiver adapted to communicate with each wireless device; and a computer coupled to the transceiver, the computer adapted to test all wireless devices in parallel by issuing a single test command using a wireless signal, the computer adapted to store test patterns and test results.

Abstract: A system for testing components of a simulator has a slave device. A master controller is coupled to the slave device. The master controller transmits chip select and data signals to the slave device for testing a component of the simulator. A computer system is coupled to the master controller. The computer system displays at least one image of a control panel. A cursor of the computer system is placed on a desired component on the at least one image of the control panel. A test signal from the computer system is sent to the master controller for testing the component of the simulator.

Abstract: Method and apparatus for channel monitoring, channel throughput restoration and system testing in relation to channel monitoring and channel throughput restoration is described. A failure status of a channel is identified. The channel and at least one engine associated with the failure status is disabled. A client application assigned such a channel is notified that the channel has been disabled. The at least one engine and the channel associated with the failure status is restored. Additionally, the client application is allowed to destroy and reconstruct command status and state of the channel. Additionally, error information for the failure status is stored. Other aspects include: error injection which may be used for testing ability to detect an error and recover; and a graphical user interface for rendering mode selection for increasing channel throughput.

Abstract: Disclosed are embodiments of a method and an associated first system for extending product life of a second system in the presence of phenomena that cause the exhibition of both performance degradation and recovery properties within system devices. The first system includes duplicate devices incorporated into the second system (e.g., on a shared bus). These duplicate devices are adapted to independently perform the same function within that second system. Reference signal generators, a reference signal comparator, a power controller and a state machine, working in combination, can be adapted to seamlessly switch performance of that same function within the second system between the duplicate devices based on a measurement of performance degradation to allow for device recovery. A predetermined policy accessible by the state machine dictates when and whether or not to initiate a switch.

Abstract: A simulation system includes glitch injection circuitry in one or more hardware design units to allow the injection of glitches or noise to evaluate the system's response to errors on signals between the hardware design units. The simulation system includes a stimulation module with a set of drivers to input simulation patterns into the design units. Some inputs to software models are driven by the outputs of software models of another design unit. The stimulation module can monitor these signals driven by the software model but it is difficult for the stimulation module to directly drive these signals. The added glitch circuitry allows injection of errors into the simulated hardware by the stimulation module on signals that are not directly driven by the stimulation module but are driven by the outputs of hardware design units.

Abstract: Methods and systems are provided for testing distributed computer applications using finite state machines. A finite state machine definition for use in a distributed computer system is combined with the fault injections definitions contained within a fault injection campaign that is created for testing the computer application employing that finite state machine. The definition and combination of the finite state machine definition and the fault injection campaign is carried out automatically or manually, for example using a graphical user interface. This combination creates at least one modified finite state machine definition containing the desired injected faults. The modified finite state machine definition is separate from the originally identified finite state machine definition, and the originally identified finite state machine remains intact without injected faults.

Abstract: A method, apparatus, and computer program product are disclosed for testing a data processing system's ability to recover from cache directory errors. A directory entry is stored into a cache directory. The directory entry includes an address tag and directory parity that is associated with that address tag. A cache entry is stored into a cache that is accessed using the cache directory. The cache entry includes information and cache parity that is associated with that information. The directory parity is altered to imply bad parity. The bad parity implies that the address tag that is associated with this parity is invalid. The information included in the cache entry is altered to be incorrect information. However, although the information is now incorrect, the cache parity continues to imply good parity which implies that the data is good. This good parity implies that the information that is associated with the parity is valid, even though it is not.

Abstract: A method and device are provided that use a sequencer in the device to control interactions on an interface bus. The sequencer is programmed to interrupt a co-processor before execution of a command. Based on the interrupt signal and a stored error mode page, a false error condition is initiated by further programming the sequencer to operate abnormally. After recovery from the error condition, the sequencer is reprogrammed to operate normally.

Abstract: A system and method for injecting faults are described. Faults may be injected into a process to determine if a given module handles the fault properly.

Abstract: A storage system includes a group of storage devices which include back-up devices configured to assure appropriate response time. When a data request from a host computer arrives, and the number of failed devices has changed as shown by a device state management table, a determination is made regarding the number of devices from which to read data. This determination is made based on an indication of redundancy which indicates how many of the disk devices are allowed to be in a failed state at the time of data reading. Typically, the indication of redundancy is determined by the sum of the number of failed devices and a predetermined number. The determined number of devices are selected in accordance with a selection factor, and a selection result is written into a disk management table. Then, the reading process is executed with respect to the target disk devices.

Abstract: Method and system for forcing PCI-Express errors in a downstream path and upstream path is provided. The downstream path method includes enabling an error forcing function; determining if an additional stimulus is used for enabling an error condition; sending the additional stimulus to trigger error detection; and detecting a forced error condition at a qualifying event. The upstream path method includes enabling an error forcing function; determining if an additional stimulus is used for enabling an error condition; sending a stimulus to trigger error detection; inserting a forced error condition at a qualifying event; wherein a downstream PCI-Express device inserts the error condition; and detecting the forced error condition; wherein an upstream PCI-Express device detects the forced error condition.

Abstract: The snapshot capability moving into the SAN fabric and being provided as a snapshot service. A well-known address is utilized to receive snapshot commands. Each switch in the fabric connected to a host contains a front end or service interface to receive the snapshot command. Each switch of the fabric connected to a storage device used in the snapshot process contains a write interceptor module which cooperates with hardware in the switch to capture any write operations which would occur to the snapshot data area. The write interceptor then holds these particular write operations until the original blocks are transferred to a snapshot or separate area so that the original read data is maintained. Should a read operation occur to the snapshot device and the original data from requested location has been relocated, a snapshot server captures these commands and redirects the read operation to occur from the snapshot area.

Abstract: The invention provides a method and system for persistent context-based behavior injection in a computing system, such as in a redundant storage system or another system having a layered or modular architecture. Behaviors that are injected can be specified to have triggering conditions, such that the behavior is not injected unless the conditions are true. Triggering conditions may include a selected ordering of conditions and a selected context for each behavior. In a system having a layered architecture, behavior injection might be used to evaluate correct responses in the face of cascaded errors in a specific context or thread, other errors that are related by context, concurrent errors, or multiple errors. Behavior injection uses non-volatile memory to preserve persistence of filter context information across possible system errors, for reporting of the results of behavior injection, and to preserve information across recovery from system errors. Multiple behavior injection threads are also provided.

Abstract: In a database system having a primary server side (10) and a secondary server side (30), a high availability data replicator (26, 46) transfers log entries from the primary side (10) to the secondary side (30) and replays the transferred log entries to synchronize the secondary side (30) with the primary side (10). R-tree index transfer threads (54, 56) copy user-defined routines, the user defined index, and index databases deployed on the primary server side (10) to the secondary server side (30) and deploy the copied user-defined routines, reconstruct the user-defined index, and copy data pages on the secondary side (30) to make the user-defined index consistent and usable on the secondary side (30).

Abstract: The present disclosure details a system, apparatus and method for reducing the redundant handling of distributed network events. In one aspect, a proxy node is selected from a plurality of network nodes and an associated network management station (“NMS”) preferably addresses only the distributed events received from the proxy node. In an alternate embodiment, non-proxy nodes may be limited to reporting node-specific events to the NMS, resulting in a reduction of the number of distributed events received and processed by the NMS to those sent by the proxy node. The proxy node may be selected by the NMS or by the network nodes, in alternate implementations. Availability of the proxy node may be monitored and ensured by the network nodes or by the NMS. The selection of a proxy node is generally repeated upon the addition of nodes to the network or a lapse in proxy node availability.

Abstract: A method and architecture for improving the usability and manufacturing yield of a microprocessor having a large on-chip n-way set associative cache. The architecture provides a method for working around defects in the portion of the die allocated to the data array of the cache. In particular, by adding a plurality of muxes to a way or ways in the data array of an associative cache having the shorter paths to the access control logic, each way in a bank can be selectively replaced or remapped to the ways with the shorter paths without adding any latency to the system. This selective remapping of separate ways in individual banks of the set associative cache provides a more efficient way to absorb defects and allows more defects to be absorbed in the data array of a set associative cache.