Abstract: A solution for validating a set of data protection solutions is provided. A validation scenario can be defined, which can include data corresponding to a set of attributes for the validation scenario. The attributes can include a time frame for the validation scenario. The validation scenario also can include a set of backup images to be validated, each of which is generated using one of the set of data protection solutions. The set of backup images can be identified using the time frame. A set of resource requirements for implementing the validation scenario can be determined based on the set of backup images and the set of attributes for the validation scenario.

Abstract: A reset method performs a software reset in a state in which data in a volatile memory is retained, when an abnormality is generated in a monitoring apparatus. Hardware of the monitoring apparatus may include a function to perform a hardware reset in a state in which the data in the volatile memory is retained, but the software reset is performed with respect to the hardware that does not include such a hardware reset function. The volatile memory may store control information for controlling a host computer monitored by the monitoring apparatus, in addition to data including fault check materials to be retained when the fault is generated. The monitoring apparatus may read the fault information from the hardware to judge whether an abnormal value is reached.

Abstract: A media player may include a media reader to read media content from a recording medium inserted into the media reader. The media player may also include a media analysis component to identify one or more valid portions of the recording medium containing media content and one or more invalid portions of the recording medium without media content. In one embodiment, the media player includes an archival component to store the media content from the one or more valid portions in a storage medium and a playback component to play back the one or more valid portions of the media content from the storage medium concurrently with the identification of the one or more valid portions by the media analysis component and the storage of the media content by the archival component.

Abstract: A method and system for dynamically injecting errors to a user design is disclosed. In one embodiment, the user design having internal states and parameters is run in a design verification system. A reconfigurable design monitor monitors a plurality of error conditions based on the internal states and parameters of the user design and generates a trigger event when a predefined error condition is met. The reconfigurable design monitor transmits a trigger event to an error injector. The error injector injects dynamic errors associated with the triggering event to the user design via a control path to test the user design under the predefined error condition.

Abstract: An information processing apparatus includes active units and a standby unit. In the active units and the standby unit, CPUs and DIMMs are divided into a plurality of logical partitions, which are controlled to be diagnosed respectively by diagnosing units. A scheduling unit periodically diagnoses the CPUs and the DIMMs of the standby unit in each of the partitions in turn. If a fault occurs on the active units side, a switching controlling unit controls a partition not being diagnosed in the standby unit to be embedded in an active unit system of the information processing apparatus. The scheduling unit instructs a diagnosis with a smaller number of diagnosis items as a diagnosis performed at reboot after the standby unit is embedded.

Abstract: Analysis tools are used for resolving a service request for software performance problems. Ranking of the analysis tools includes measuring a plurality of times to resolution of a plurality of service requests for software performance problems after runnings of a plurality of analysis tools are initiated; capturing sets of errors in the plurality of service requests; storing identities of the plurality of analysis tools with the times to resolution of the service requests and the sets of errors; determining an average time to resolution of each of the plurality of analysis tools for each set of errors; organizing the plurality of analysis tools into one or more categories using the sets of errors; and ranking the analysis tools within each category using the average times to resolution of the analysis tools within the category.

Abstract: One embodiment of the present invention provides a system that inserts faults to test code paths. The system starts by placing fault-inserting method calls at join points within methods in program code. The system then executes the program code during a testing process. As a method is executed during the testing process, the system executes the corresponding fault-inserting method. This fault-inserting method checks a configuration database to determine whether a fault is to be simulated for the method and, if so, simulates a fault for the method.

Abstract: An electronic circuit includes first and second circuits that include corresponding built-in-self-test (BIST) engines to perform memory testing operations on corresponding first and second memory block and generate first and second memory repair data. A multiplexer receives the first and second memory repair data and selectively transmits the first memory repair data during a first test cycle and the second memory repair data during a second test cycle. A shadow register buffers the first memory repair data during the first test cycle and a fuse processor sequentially receives and stores the first and second memory repair data during the second test cycle.

Abstract: An apparatus comprising an initiator circuit and a target circuit. The initiator circuit may be configured to (i) communicate with a network through a first interface and (ii) generate testing sequences to be sent to the network. The target circuit may be configured to (i) receive the testing sequences from the network through a second network interface and (ii) respond to the testing sequences.

Abstract: A method, system, and computer usable program product for energy-efficient soft error failure detection and masking are provided in the illustrative embodiments. A soft error is injected to occur during execution of a set of instructions. If an output of the execution of the set of instructions is incorrect, a record is made of the instruction that was affected by the injected soft error and led to the incorrect result. This identified instruction is designated as vulnerable to the soft error. Several soft errors are injected with different input data sets over several executions of the same set of instructions, and a probability of each instruction in the instruction set is computed, the probability of an instruction accounting for the vulnerability of the execution of the instruction sets to errors that affect the instruction. A report including several probabilities of instruction vulnerabilities is produced.

Abstract: The invention provides a highly resilient network infrastructure that provides connectivity between a main network such as the Internet and a subnetwork such as a server-based (e.g., web server) local area network. In accordance with the invention, a network interface incorporated into a server hosting center provides a resilient architecture that achieves redundancy in each of three different layers of the Open System Interconnect (OSI) stack protocol (i.e., physical interface, data link, and network layers). For every network device that is active as a primary communication tool for a group of subnetworks, the same device is a backup for another group of subnetworks. Based on the same connection-oriented switching technology (e.g., asynchronous transfer mode (ATM)) found in high-speed, broadband Internet backbones such as that provided by InternetMCI, the network interface architecture provides a high degree of resiliency, reliability and scalability.

Abstract: A coprocessor includes a calculation unit for executing at least one command, and a securization device. The securization device includes an error detection circuit for monitoring the execution of the command so as to detect any execution error, putting the coprocessor into an error mode by default as soon as the execution of the command begins, and lifting the error mode at the end of the execution of the command if no error has been detected, an event detection circuit for monitoring the appearance of at least one event to be detected, and a masking circuit for masking the error mode while the event to be detected does not happen, and declaring the error mode to the outside of the coprocessor if the event to be detected happens while the coprocessor is in the error mode. Application in particular but not exclusively to coprocessors embedded in integrated circuits for smart cards.

Abstract: A testbed for testing health of software includes an input model, a hardware model, and a resource modeler. The input model represents an input system used in conjunction with the software. The hardware model represents one or more hardware components used in conjunction with the software. The resource modeler is coupled to the input model and the hardware model, and is configured to estimate effects on the software of conditions of the hardware components, the input system, or both.

Abstract: A method begins with the specific computing device token sending a distributed storage network (DSN) access request to DSN memory via the generic computing device. The DSN access request identifies specific computing device operation information that is stored as one or more of-sets of encoded data slices in the DSN memory. The method continues with the specific computing device token receiving the one or more of sets of encoded data slices from the DSN memory via the generic computing device and decoding the one or more of sets of encoded data slices to retrieve the specific computing device operation information. The method continues with enabling the generic computing device to function as a specific computing device in accordance with the specific computing device operation information.

Abstract: The present disclosure provides testing of a storage system. The test may compare the storage array controller LUNs which may be configured to be accessible by a host with the LUNs which are currently available to prevent a zero path scenario from occurring. The test may verify at least one path exists for each LUN to a storage controller of a storage array before injecting an error into another storage controller of the storage array. The present disclosure also provides verification of the configuration of a storage system. The configuration verification may verify that the storage array controller LUNs which are configured to be accessible by a host are actually accessible by the host. If the configuration verification is unable to verify the configuration of storage system, the configuration verification may display an error.

Abstract: A system for protecting, controlling, and monitoring substation devices of a power system, includes a spare protection and control unit that, when there is a failure in a protection and control unit from among protection and control units that perform a protection and control operation for the substation devices, downloads unit information including software and a device setting value of failed protection and control unit from a database unit and functions as an alternative unit for the failed protection and control unit.

Abstract: An apparatus, system, and method are disclosed for injecting noise onto a link of a network. The apparatus, system, and method include, providing a noise injector card, connecting the noise injector card to the link, receiving a control signal to activate the noise injector card, switching a switch of the noise injector card, and injecting noise onto the link.

Abstract: An enterprise disaster recovery system, including a processor for running at least one data application that reads data from at least one data disk and writes data to the at least one data disk over a period of time, a recovery test engine that (i) generates in parallel a plurality of processing stacks corresponding to a respective plurality of previous points in time, each stack operative to process a command to read data at a designated address from a designated data disk and return data at the designated address in an image of the designated data disk at the previous point in time corresponding to the stack, and (ii) that generates in parallel a plurality of logs of commands issued by the at least one data application to write data into designated addresses of designated data disks, each log corresponding to a respective previous point in time.

Abstract: Apparatus and methods for Cyclic Redundancy Check (CRC) error injection between storage controllers and storage devices in a storage system. A plurality of bridge devices are configured in a storage system each coupled persistently coupled to a corresponding one of the plurality of storage devices. Each bridge device may couple to one or more Serial Attached SCSI (SAS) initiators for transferring exchanges between one or more SAS initiators and the attached target storage device. Each bridge device receives parameters from a SAS initiator or an administrative client directing the bridge regarding injection of CRC errors. A log memory in each bridge may log information regarding the injected CRC errors.

Abstract: An automated emergency power supply system (EPSS) and testing solution that records generator load values and engine exhaust temperature values to evaluate whether an EPSS test satisfies legislated test criteria. The EPSS test is carried out under software control, which initiates a test by instructing an automatic transfer switch (ATS) to change its status to a test status, causing the essential loads to be powered by a generator instead of a main utility power source. Power monitors record the ATS and generator status during the test as well as electrical parameter data from the ATS and generator and exhaust temperature data and other engine parameter data from the generator. When the test is concluded, the ATS is instructed to return the status to normal so that power delivery is resumed from the main power source. The electrical and engine parameter data is analyzed and compared against legislated test criteria to determine a pass/fail result of the EPSS test.

Abstract: A floating net inspection method includes: providing a netlist which describes a circuit structure of an application circuit, the application circuit including a plurality of transistors; coupling a power supply port and a signal input port of the application circuit to voltage sources, respectively; generating test voltages respectively through the voltage sources, such that the test voltages are applied to the transistors, the test voltages being larger than a reference voltage; and determining whether a connecting node of one of the transistors is floating on the basis of whether a voltage of the connecting node is larger than the reference voltage.

Abstract: A mechanism for performing verification of template integrity of monitoring templates used for customized monitoring of system activities. A method of embodiments of the invention includes calculating a first hash code for a monitoring template, the monitoring template to customize a performance monitor to serve as a universal monitor to facilitate a plurality of monitoring tools to perform monitoring of activities of a plurality of system components of the computer system, extracting the first hash code from the monitoring template, and calculating a second hash code for the monitoring template. The method further includes verifying integrity of the monitoring template by comparing the first hash code with the second hash code, and the integrity of the monitoring template is determined to be satisfactory if the first hash code matches the second hash code.

Abstract: A method begins by a processing module identifying a set of stored files that includes an original file and one or more back-up copies of the original file. The method continues with the processing module dispersed storage error encoding one of the set of stored files to produce a plurality of sets of encoded data slices. The method continues with the processing module facilitating storage of the plurality of sets of encoded data slices. The method continues with the processing module facilitating deletion of the set of stored files.

Abstract: An embodiment is a method and apparatus to save data during power failure. A power supply generator generates operating voltages to a circuit from a generator supply source. A power monitor monitors a normal supply voltage and a backup supply voltage to provide a normal supply voltage to the generator supply source in a normal mode and to provide a backup supply voltage to the generator supply source in a power failure mode. A data transfer circuit transfers data from a volatile memory in the circuit to a non-volatile memory during the power failure mode.

Abstract: This invention is to provide a technology for taking out trace information externally without lacking under the condition of limited output bandwidth. A semiconductor integrated circuit provided includes: a processing unit which can perform arithmetic processing according to a predetermined program and can output trace information with respect to the arithmetic processing; and a trace compression unit which can compress the trace information outputted from the processing unit. The trace compression unit includes a storage device, a comparator unit which can compare trace information stored in the storage device and the trace information newly outputted from the processing unit, and a trace information compression controller which can compress trace information to be externally outputted, based on the comparison result of the comparator unit.

Abstract: A system and method for accurately modeling a fault log is provided for validating one or more elements of fault detection and logging logic for a real-time fault log of a digital system such as, for instance, a computer processor. The method includes injecting one or more known faults into a data path and/or a control path of the computer processor and spawning an individual tracking thread for each of the injected faults. The tracking threads may be synchronized at a predefined synchronization point that is selected as a function of a collective logging delay representing the time required for each of the injected faults to reach a real-time logging point within the computer processor. Once synchronized, the tracking threads may be input into a fault logging specification for fault behavior and/or system impact modeling and fault prioritization for use in generating a fault log model for comparison to the real-time fault log maintained within the computer processor.

Abstract: Provided are a method and apparatus for evaluating the effectiveness of a test case used for a program test on the basis of error detection capability. The method includes: receiving a target program used for evaluating the effectiveness of the test case; generating an error program by inputting errors to the target program; detecting the errors by executing the test case on the generated error program; and calculating evaluation points of the test case using a ratio of the number of the detected errors to the number of the input errors. Thus, the capability of the test case used for a program test to detect errors can be evaluated.

Abstract: Various method, system, and computer program product embodiments for implementing selective write-protect by a processor in a data storage system within a plurality of redundant storage systems for disaster recovery testing are provided. In one such embodiment, a write-protect state is initiated within at least one of the plurality of redundant storage systems. An available plurality of categories, including at least one write-protect exclusion category, is configured within a management interface of the data storage system, such that during the disaster recovery testing a storage volume categorized in the write-protect exclusion category is excluded from write protection.

Abstract: Device, system, and method of storage controller simulating data mirroring. For example, an apparatus for simulating data mirroring includes: a storage controller to control a primary storage unit that has data stored therein, wherein the storage controller is able to simulate a process of mirroring data stored in the primary storage unit in response to a mirroring simulation command.

Abstract: Example embodiments provide various techniques for creating a test bed for testing failover and failback operations. In an example, data is stored on a primary storage system, while a backup copy of the data is stored on a secondary storage system. A test bed may be created by replicating the data on the primary storage system and replicating the backup copy on the secondary storage system. The replicated copies of the data and the backup copy, as well as a process used to backup the data, comprise the test bed, which may be used to test the failover and failback operations.

Abstract: Disclosed is a design structure for an associated first system for extending product life of a second system in the presence of phenomena that cause the exhibition of both performance degradation and recovery properties within system devices. The first system includes duplicate devices incorporated into the second system (e.g., on a shared bus). These duplicate devices are adapted to independently perform the same function within that second system. Reference signal generators, a reference signal comparator, a power controller and a state machine, working in combination, can be adapted to seamlessly switch performance of that same function within the second system between the duplicate devices based on a measurement of performance degradation to allow for device recovery. A predetermined policy accessible by the state machine dictates when and whether or not to initiate a switch.

Abstract: A method, system and article of manufacture are disclosed for error recovery in a replicated state machine. A batch of inputs is input to the machine, and the machine uses a multitude of components for processing those inputs. Also, during this processing, one of said components generates an exception. The method comprises the steps of after the exception, rolling the state machine back to a defined point in the operation of the machine; preemptively failing said one of the components; re-executing the input batch in the state machine; and handling any failure, during the re-executing step, of the one of the components using a defined error handling procedure. The rolling, preemptively failing, re-executing and handling steps are repeated until the input batch runs to completion without generating any exception in any of the components that are not preemptively failed.

Abstract: In one embodiment, a method includes receiving a request message at a local node in a communications network from a remote node in the communication network. The request message holds data that indicates a request for a particular service from the local node. A load metric that indicates a current processing load at the local node is determined. A response delay time, for responding to the request message, is determined based on the load metric. A response message is sent after the response delay time. The response message indicates the local node is able to provide the particular service for the remote node. The delay time allows the local node to make it more likely that a less busy node will respond earlier in time to a request message from the same remote node and provide the particular service.

Abstract: In one embodiment, a method comprises executing respective workload management processes within a plurality of computing compartments to allocate at least processor resources to applications executed within the plurality of computing compartments, selecting a master workload management process to reallocate processor resources between the plurality of computing compartments in response to requests from the workload management processes to receive additional resources, monitoring operations of the master workload management process by the other workload management processes, detecting, by the other workload management processes, when the master workload management process becomes inoperable, and selecting a replacement master workload management process by the other workload management processes in response to the detecting.

Abstract: In a digital video system, high availability distribution is provided using spare modules such as an integrated receiver decoder, multimedia transcoder and streaming module in support of the primary modules. The primary modules multicast status messages which are monitored by the spare modules. When failure of a primary module is detected, the spare module takes over the role of the failed module, for example by joining the same multicast groups as the failed module and taking over processing of the streams of the failed module. Multiple redundancy schemes are described.

Abstract: Recreating errors in a network device. In one embodiment, a method for recreating an error condition in a network device includes capturing a first set of commands sent to a network device; identifying an error condition in the network device, the error condition corresponding to the captured first set of commands; and sending a second set of commands to the network device in a second attempt to recreate the error condition. The second set of commands includes the first set of commands as well as additional commands that are configured to place the network device in substantially the same state as at the time that the first set of commands was sent to the network device.

Abstract: A coprocessor includes a calculation unit for executing at least one command, and a securization device. The securization device includes an error detection circuit for monitoring the execution of the command so as to detect any execution error, putting the coprocessor into an error mode by default as soon as the execution of the command begins, and lifting the error mode at the end of the execution of the command if no error has been detected, an event detection circuit for monitoring the appearance of at least one event to be detected, and a masking circuit for masking the error mode while the event to be detected does not happen, and declaring the error mode to the outside of the coprocessor if the event to be detected happens while the coprocessor is in the error mode. Application in particular but not exclusively to coprocessors embedded in integrated circuits for smart cards.

Abstract: The present invention relates to a coprocessor comprising a calculation unit for executing a command, and a securization device for monitoring the execution of the command and supplying an error signal having an active value as soon as the execution of the command begins and an inactive value at the end of the execution of the command, if no abnormal progress in the execution of the command has been detected. The coprocessor further comprises means for preventing access to at least one unit of the coprocessor, while the error signal is on the active value. Application is provided particularly but not exclusively to the protection of integrated circuits for smart cards against attacks by fault injection.

Abstract: A method for monitoring of the functionality of an EDP system that is monitored in portions thereof by respectively associated agents that are designed to evaluate errors and to send error messages should increase the operating security in an EDP system. Each agent is monitored by a simulated error being sent to the agent and the reaction of the agent being evaluated.

Abstract: A method and system for injecting a deterministic fault into storage shelves in a storage subsystem. The method comprises injecting a known fault condition on demand into a hardware component in a storage shelf to cause a failure of the storage shelf. The hardware component incorporates a circuit that is configurable to select between a normal operating condition and a faulty condition of the hardware component. The method further comprises verifying that a reported failure is consistent with the known fault condition.

Abstract: An information processing system containing middleware and backend server software components is augmented with the ability to validate the behavior of the middleware system when one or more backend servers are unavailable, based on dynamic reconfiguration of the network layer protocol software component in the operating system underlying the middleware software component.

Abstract: In an embodiment, a node comprises a packet scheduler configured to schedule packets to be transmitted on a link and an interface circuit coupled to the packet scheduler and configured to transmit the packets on the link. The interface circuit is configured to generate error detection data covering the packets, wherein the error detection data is transmitted between packets on the link. The interface circuit is configured to cover up to N packets with one transmission of error detection data, where N is an integer >=2. The number of packets covered with one transmission of error detection data is determined by the interface circuit dependent on an availability of packets to transmit. In another embodiment, the interface circuit is configured to dynamically vary a frequency of transmission of the error detection data on the link based on an amount of bandwidth being consumed on the link.

Abstract: A method uses an integrated circuit having a debug status register. The integrated circuit is for being debugged by a hardware debugger external to the integrated circuit and has a processing unit for executing debug software. The debug status register is coupled to the processing unit and is for being coupled to the hardware debugger. The method includes updating the debug status register with hardware status flags arising from running the hardware debugger and software status flags arising from running the debug software. The method further includes masking locations in the debug status register where the hardware status flags are located from being read by the debug software while allowing the hardware status flags and the software status flags to be read by the hardware debugger. This is particularly useful in using the hardware debugger in debugging the debug software.

Abstract: The snapshot capability moving into the SAN fabric and being provided as a snapshot service. A well-known address is utilized to receive snapshot commands. Each switch in the fabric connected to a host contains a front end or service interface to receive the snapshot command. Each switch of the fabric connected to a storage device used in the snapshot process contains a write interceptor module which cooperates with hardware in the switch to capture any write operations which would occur to the snapshot data area. The write interceptor then holds these particular write operations until the original blocks are transferred to a snapshot or separate area so that the original read data is maintained. Should a read operation occur to the snapshot device and the original data from requested location has been relocated, a snapshot server captures these commands and redirects the read operation to occur from the snapshot area.

Abstract: A method and system for verifying computer system drivers such as kernel mode drivers. A driver verifier sets up tests for specified drivers and monitors the driver's behavior for selected violations that cause system crashes. In one test, the driver verifier allocates a driver's memory pool allocations from a special pool bounded by inaccessible memory space to test for the driver's accessing memory outside of the allocation. The driver verifier also marks the space as inaccessible when it is deallocated, detecting a driver that accesses deallocated space. The driver verifier may also provide extreme memory pressure on a specific driver, or randomly fail requests for pool memory. The driver verifier also checks call parameters for violations, performs checks to ensure a driver cleans up timers when deallocating memory and cleans up memory and other resources when unloaded. An I/O verifier is also described for verifying drivers use of I/O request packets.

Abstract: Fault injection in dynamic random access memory (‘DRAM’) modules for performing built-in self-tests (‘BISTs’) including establishing, in the mode registers of the DRAM modules by the memory controller through the shared address bus, an injection of a fault into one or more signal lines of a DRAM module, the fault characterized by a fault type; writing data by the memory controller through a data bus to the DRAM modules, the data identifying a particular DRAM module; and responsive to receiving the data, injecting, by the particular DRAM module, the fault characterized by the fault type into the one or more signal lines of the particular DRAM module.

Abstract: A method for facilitating management of a data processing environment is disclosed. In various embodiments, the method may include facilitating homogeneous monitoring of a plurality of heterogeneous data processing nodes of the data processing environment, the homogeneous monitoring including facilitating detecting one or more changes of one or more elements of the plurality of heterogeneous data processing nodes. In various embodiments, the method may further include facilitating performing one or more actions in response to detecting the one or more changes. Other embodiments of the present invention may include, but are not limited to, apparatuses and systems adapted to facilitate practice of the above-described method.

Abstract: A memory error injector is defined to include a connector for enabling connection with a standard memory module receptacle. The memory error injector also includes a standard memory block defined to interface with the connector and operate in accordance with a standard memory specification. The memory error injector further includes error injection logic defined to force data transmitted to or from a specified memory location within the standard memory block to a fixed state, for a first number of access cycles addressed to the specified memory location. The error injection logic is defined to force the data to the fixed state during transmission of the data between the connector and the standard memory block.

Abstract: Method and apparatus for channel monitoring, channel throughput restoration and system testing in relation to channel monitoring and channel throughput restoration is described. A failure status of a channel is identified. The channel and at least one engine associated with the failure status is disabled. A client application assigned such a channel is notified that the channel has been disabled. The at least one engine and the channel associated with the failure status is restored. Additionally, the client application is allowed to destroy and reconstruct command status and state of the channel. Additionally, error information for the failure status is stored. Other aspects include: error injection which may be used for testing ability to detect an error and recover; and a graphical user interface for rendering mode selection for increasing channel throughput.

Abstract: In an embodiment, a node comprises a packet scheduler configured to schedule packets to be transmitted on a link and an interface circuit coupled to the packet scheduler and configured to transmit the packets on the link. The interface circuit is configured to generate error detection data covering the packets, wherein the error detection data is transmitted between packets on the link. The interface circuit is configured to cover up to N packets with one transmission of error detection data, where N is an integer >=2. The number of packets covered with one transmission of error detection data is determined by the interface circuit dependent on an availability of packets to transmit. In another embodiment, the interface circuit is configured to dynamically vary a frequency of transmission of the error detection data on the link based on an amount of bandwidth being consumed on the link.