Abstract: An electronic control device includes: a processing unit that performs a predetermined process in accordance with a program; a watchdog timer that includes a time counter reset by a pulse signal output at a given period from the processing unit and outputs a signal having levels inverted depending on whether an overflow occurs; and a latch circuit that latches the signal output from the watchdog timer and outputs a signal obtained through the latching as a first output enable signal. The processing unit stops the output of the pulse signal, when diagnosing a malfunction of the watchdog timer, and diagnoses the malfunction of the watchdog timer based on the first output enable signal output from the latch circuit, after stopping the output of the pulse signal.

Abstract: A watchdog timer including a first register that stores a first overflow time, a second register that stores a second overflow time, a detector and a counter that continues to count a clock signal to the first overflow time. When the detector detects an execution of a program for a flash memory, the counter clears a count value and continues to count the clock signal to the second overflow time.

Abstract: Methods and apparatus to provide failure detection are disclosed herein. An example method to synchronize data operations between multiple workload units in a computing device to facilitate failure detection includes identifying a number of first data operations to write data from a computing node in a first workload unit to locations that are not in a local cache of the computing node and are not in a memory of the first workload unit, the first data operations corresponding to a set of computing instructions that are assigned to the first workload unit and, when a flag in the first workload unit has been set to a first value, synchronizing the first data operations with second data operations by a second workload unit.

Abstract: [This invention] inhibits the response time of the storage control apparatus from being longer even if the response time of the storage apparatus is long. The disk adapter (DKA), receiving a read message from the channel adapter (CHA), sets the timeout time in accordance with specified conditions, and tries to read data from the storage apparatus 4. As the timeout time, either the normal value or the shortened value is selected. If a timeout error occurs, the read job is reset, and correction read is started.

Abstract: A method and apparatus to operate a watchdog timer having a first time out period in a processing system. The watchdog timer receives an indication of a change in a mode of operation in the processing system. In response to the change in the mode of operation of the processing system, the watchdog timer changes the time out period to a second time out period corresponding to the new mode of operation.

Abstract: A method for decreasing the risk of monitoring data failing to be stored includes periodically sending a test message from the monitoring device to a Networked Storage Device, NSD, generating an NSD fail signal in the monitoring device if events following the sending of the test message indicates that the NSD is not operating properly, and sending, in response to the NSD fail signal, a fail message from the monitoring device for detection outside housing of monitoring device.

Abstract: Described herein are methods for transitioning control between a first and second controller of a storage system. In such transition, the first controller transmits a message to a memory element shared by the first and second controllers, the message capable of notifying the second controller of an imminent failure of the first controller. The second controller receives the message from the shared memory element, the message notifying the second controller of an imminent failure of the first controller. Subsequent to transmitting the message to the shared memory element, the first controller becomes unavailable to facilitate access to the storage devices of the storage system. Subsequent to receiving the message from the shared memory element, the second controller becomes available to facilitate access to the storage devices of the storage system.

Abstract: Described herein are techniques for transitioning control between a first and second controller of a storage system. In such transition, the first controller transmits a message to a memory element shared by the first and second controllers, the message capable of notifying the second controller of an imminent failure of the first controller. The second controller receives the message from the shared memory element, the message notifying the second controller of an imminent failure of the first controller. Subsequent to transmitting the message to the shared memory element, the first controller becomes unavailable to facilitate access to the storage devices of the storage system. Subsequent to receiving the message from the shared memory element, the second controller becomes available to facilitate access to the storage devices of the storage system.

Abstract: Methods and apparatuses for fault detection in a component associated with an application programming interface platform are provided. In an embodiment, the component is determined to have been invoked to process a transaction. A forward progress counter is monitored to determine whether the component is processing the transaction, wherein the forward progress counter increments at determined intervals when the component is processing the transaction. A test transaction is executed for the component when a determination is made that the forward progress counter has not incremented for a threshold fault period. A fault alarm indicator is generated based on the determination that the forward progress counter has not incremented for the threshold fault period.

Abstract: A method, system and computer program product for providing high availability to a hybrid application server environment containing non-Java® containers. Each hybrid application server in the cluster includes a Java® container and a non-Java® container hosting Java® and non-Java® applications, respectively. Upon detecting the non-Java® container becoming unavailable (failing), an object, such as an MBean, identifies and deactivates those Java® application(s) that are dependent on the non-Java® application(s) deployed in the unavailable non-Java® container using dependency information stored in an application framework. The deactivated Java® application(s) are marked as being unavailable. A routing agent continues to send requests to those Java® application(s) that are not marked as being unavailable within that hybrid application server containing the unavailable non-Java® container.

Abstract: A diagnosis circuit 1 monitors a watchdog timer 2 and supplies a diagnosis result signal 1 indicating whether a monitoring result is normal or not to a diagnosis circuit 2. A diagnosis circuit 3 monitors a watchdog timer 1 and supplies a diagnosis result signal 3 indicating whether a monitoring result is normal or not to the diagnosis circuit 2. The diagnosis circuit 2 determines that the diagnosis circuit 1 or the watchdog timer 2 is abnormal when the diagnosis result signal 1 does not have a value indicating normal. Further, the diagnosis circuit 2 determines that the diagnosis circuit 3 or the watchdog timer 1 is abnormal when the diagnosis result signal 3 does not have a value indicating normal.

Abstract: Embodiments relate to multi-contact sensor devices and operating methods thereof that can reduce or eliminate offset error. In embodiments, sensor devices can comprise three or more contacts, and multiple such sensor devices can be combined. The sensor devices can comprise Hall sensor devices, such as vertical Hall devices, or other sensor types in embodiments. Operating modes can be implemented for the multi-contact sensor devices which offer significant modifications of and improvements over conventional spinning current principles, including reduced residual offset.

Abstract: A method of monitoring a processing circuit is disclosed. The processing circuit is operable, in a normal operation mode, to generate a sequence of trigger commands, with at least one trigger command of the sequence of trigger commands including time information. At least one window sequence with a closed window period and an open window period is generated such that the duration of the closed window period and/or the open window period is defined, at least in part, by the time information. It is detected if one trigger command is received within the open window period of the at least one sequence.

Abstract: An automatic alarm system is described that is triggered by the lack of event at one or more portable remote unit(s). The system includes an electromagnetic interface from a plurality of portable units to a central command and monitoring element. This automatic triggering of an alarm condition adds security to the users of the system since it is not always feasible to explicitly trigger an alarm when in danger.

Abstract: A method for operating an electronic device that is supplied with electric power by a continuous energy accumulator. A predetermined ending of the first program is monitored in a program step by a second program. If the first program is not switched off as predetermined, the second program generates an error message which is displayed immediately when the device is switched on again.

Abstract: A memory 225 stores the log information of respective cores 116 to 118. If an abnormality occurs in any core, each core writes the log information, being stored in the memory 225, thereof into a backup storage device 126. Thus, the log information of cores other than the core in which the abnormality occurs can be saved in the backup storage device 126.

Abstract: A microcomputer or microcontroller with a watchdog timer-counter also has an external reset signal generator. When the central processing unit of the microcomputer or microcontroller fails to execute its control program correctly, the watchdog timer-counter generates an internal reset signal for a first interval, resetting the central processing unit, and the external reset signal generator generates an external reset signal for a second interval, different from the first interval. The length of the second interval can be set to match the requirements of external peripheral devices to which the external reset signal is supplied.

Abstract: A diagnosis circuit 1 monitors a watchdog timer 2 and supplies a diagnosis result signal 1 indicating whether a monitoring result is normal or not to a diagnosis circuit 2. A diagnosis circuit 3 monitors a watchdog timer 1 and supplies a diagnosis result signal 3 indicating whether a monitoring result is normal or not to the diagnosis circuit 2. The diagnosis circuit 2 determines that the diagnosis circuit 1 or the watchdog timer 2 is abnormal when the diagnosis result signal 1 does not have a value indicating normal. Further, the diagnosis circuit 2 determines that the diagnosis circuit 3 or the watchdog timer 1 is abnormal when the diagnosis result signal 3 does not have a value indicating normal.

Abstract: Upon receiving a particular data unit by a receiving layer of a wireless device, it is detected that a previous data unit earlier in sequence to the particular data unit has not yet been received by the receiving layer. A timer is started in response to the detecting, where the timer has a time-out period that is variable dependent upon a parameter associated with receipt of the particular data unit. Upon expiration of the timer based on the timeout period, the receiving layer generates an error indication.

Abstract: According to one embodiment, a method for detecting a periodic error, the method detecting a periodic processing error of a module controlled by a processor, the processor controlling a periodic processing by booting a peripheral module, the peripheral module outputting periodic triggers with a predetermined interval includes storing a first count value acquired from a counter, a second count value when the processing is started, and a third count value when the processing is completed, calculating a processing time on a basis of the three count values, and comparing the processing time with the predetermined interval to determine whether the periodic processing error occurs.

Abstract: A system includes at least one monitored device collect data detect and detect an error in the data, a central server, and at least one local server communicatively coupled to the monitored device and the central server. The local server is configured to receive the data and an indication of the error detected from the monitored device, determine a solution for use in resolving the error, transmit instructions to perform the solution to the monitored device, and transmit the error and the solution to the central server for storage.

Abstract: An information processing apparatus includes a processing unit, a power supply control unit configured to control powering on and off of the processing unit, and a controller unit configured to access the processing unit irrespective of a power supply state of the processing unit. The power supply control unit powers off a processing unit that is not in use, powers on a processing unit that is accessed by the controller unit, and outputs a predetermined control signal to the controller unit. The controller unit recognizes that an error occurs in a case where, after accessing a processing unit, the controller unit does not receive a response from the accessed processing unit until a time-out time elapses, and delays recognizing the error when the control signal is received.

Abstract: The embodiments provide a way to predict when a storage device will be accessed. In order to enhance performance, the storage device may proactively prepare for the access operation, and thus, minimize the access-time response of the storage device. The user behavior is recorded over time and collected into a dataset. In one embodiment, the intervals between the data points in the dataset are calculated and arranged into a matrix. Patterns in the matrix are recognized and used to recognize the next likely access by the user. The storage device may then take various actions, such as drive spin up, in anticipation of the next predicted access to minimize access-time response.

Abstract: Controlling a device having a shared processing resource includes ascertaining a supervision timer value for a client service that uses the shared processing resource. The client service is caused to make a server request and a supervision timer is set to cause a timeout after a supervision timer value time period. Ascertaining the supervision timer value includes ascertaining which of a number of use scenarios represents an operation state of the device, the use scenarios being at least in part distinguished from one another by which services are presently active, including the client service. Each of the plurality of services utilizes the shared processing resource when active. One supervision timer value is selected from a number of values each associated with the client service, selection being made at least partly as a function of the ascertained use scenario. The value is retrieved from the set of stored supervision timer values.

Abstract: A method for maintaining reliable communication on a link between an expander and a storage device is provided. The method includes detecting, by a processor coupled to the link, an error corresponding to the link, and maintaining a count of detected errors for the link, by the processor. The method also includes determining, by the processor, if the count of detected errors is above a first error threshold. If the count of detected errors is not above the first error threshold, then the method repeats the detecting, maintaining, and determining steps. If the count of detected errors is above the first error threshold, then the method provides the processor placing the storage device into a segregated zone.

Abstract: A device provides an ager ring that ages entries associated with managed resource of a device, and determines whether a particular entry associated with a particular managed resource of the device is to be updated. The device also updates, when the particular entry is to be aged out in a particular time frame, the particular entry in the ager ring based on a bucket offset and a current time bucket associated with the particular entry and based on a current time, a refresh timeout, and a maximum timeout associated with the ager ring. The device further updates, when the particular entry is being aged during processing, the particular entry in the ager ring based on a new bucket, the current time bucket, and the bucket offset associated with the particular entry and based on the maximum timeout associated with the ager ring.

Abstract: Due to software bugs, hardware bugs, power fluctuations, cosmic rays, and various other causes, computing systems may from time to time enter various types of error states. This disclosure relates generally to the field of watchdog timers configured to take corrective action when a computing system enters such an error state. In various embodiments, this disclosure provides systems, methods, apparatuses, and computer-readable media for multi-tier watchdog timers. Such multi-tier watchdog timers may be configured to take different levels of corrective action at different times and/or under different conditions.

Abstract: In a method for correcting errors occurring in attention (AT) commands of a mobile device, the mobile device includes a first user identity module (UIM) chipset, a second UIM chipset, a buffer and a timer. The method sets a response time for a communication between the first UIM chipset and the second chipset according to an AT command, backups the AT command into the buffer, and counts a communication time using the timer. When the communication time exceeds the response time, the method restarts the first UIM chipset using a watchdog timer and restarts the second UIM chipset by resetting voltage levels of I/O pins of the second UIM chipset. The method further clears the communication data stored in the buffer, reads the AT command from the buffer and resends the AT command to control the first UIM chipset to communicate with the UIM second chipset normally.

Abstract: At least two task servers connect to a database server. The database server includes a task list. A task server accesses the task list to search a task which is an earliest presenting task. When the searched task has not been executed, the task server marks the searched task with a serial number of the task. The task server records an execution start time of the searched task. When a time of executing the searched task is more than a predefined time, the task server prompts a user to deal with an error of the task server.

Abstract: In an embodiment, provided is a communication device connected to time servers via a network with transfer devices. In the communication device: a network controller receives a message containing time information counted by the time server and containing a network identifier, and obtains a receiving timing of the message; a network processing unit, when the network identifier in the message does not match with any network identifier, destroys the message; a protocol processing unit, when the network identifier has a match, calculates a time error by the time information in the message and the receiving timing, detects whether a first time server is malfunctioning, and when detected the first time server malfunctioning, outputs the time error calculated by a network identifier assigned to a second time server; a servo calculates an operation amount by the time error; and a clock varies a clock rate according to the operation amount.

Abstract: A technique automatically handles a failure during online data migration from a source array to a target array. While a host initially accesses data from the source array using multipath I/O software, the technique involves (i) transitioning the source array to a passive mode, and the target array to an active mode, and (ii) beginning a data transfer operation which transfers data from the source array to the target array. The technique further involves modifying the data on both the target array and the source array in response to modification commands sent to the target array from the host while the data transfer operation is ongoing. The technique further involves automatically failing back to providing access to the data from the source array in response to an event in which the target array loses communication with the source array for a predefined amount of time.

Abstract: Various exemplary embodiments relate to a method and related network node including one or more of the following: receiving, at a policy and charging rules node (PCRN), a request from a requesting node for an establishment of a first service data flow (SDF); generating a first rule set for implementing the first SDF in response to the request; transmitting a first rule of the rule set to a first node for installation of the first rule; waiting for a period of time for a response from the first node; determining from the response whether installation of the first rule at the first node failed or succeeded; and if installation of the first rule succeeded, transmitting a second rule of the first rule set to a second node for installation of the second rule.

Abstract: A method for monitoring at least two microcontrollers using a watchdog is described. The watchdog is associated with a first microcontroller and monitors the communication of a message from the first microcontroller within a time interval of a predefined duration. The message communicated to the watchdog by the first microcontroller contains a contribution which is formed on account of communication between the first microcontroller and a second microcontroller connected to the latter and on the basis of which the watchdog checks the proper method of operation of the second microcontroller. The disclosure also describes a circuit arrangement and a battery with a battery management unit which are configured to carry out the method according to the disclosure.

Abstract: A method for event management in asynchronous work processing including timing at least one step in an asynchronous work process, wherein the at least one step is performed by an application and the at least one step has an expected time of completion; determining an error preventing step completion in response to the expected time of completion expiring; correcting the error; and re-performing the at least one step.

Abstract: Embodiments of the present invention provide an apparatus and a method for recording a reboot reason of equipment. Besides a first watchdog provided for triggering a global reset of the equipment, the apparatus provided by the present invention further includes a second watchdog. The second watchdog is used to trigger a logic chip to record a value representing the reboot reason of power-down in a storage array after the equipment is powered on. Thus, reboot reason of the equipment could recorded as power-down reboot.

Abstract: Selection of a minimum voltage and/or maximum clock frequency in an integrated circuit is described. Selection of the minimum voltage and/or maximum clock frequency is accomplished by generating a timing error prediction signal and a timing error detection signal in a timing error module that is placed in a critical path in the integrated circuit.

Abstract: A computer apparatus includes a managing unit realizing virtual computers including device driver virtual computers and user virtual computers, the user virtual computers communicating with various devices via the device driver virtual computers. Error detection information is received from one of the virtual computers upon detection of error in one of the device drivers used for communication with one of the devices in one of the virtual computers. One or more types of the virtual computers and the contents of recovery process corresponding to the type of device driver and the type of error indicated in the received error detection information are acquired from error recovery control information. A recovery instruction is transmitted to one or more of the virtual computers identified by the one or more acquired types of virtual computers in order to cause the one or more identified virtual computers to perform the acquired contents of the recovery process.

Abstract: Some embodiments of the present disclosure relate to a watchdog timer having an enhanced functionality that enables the watchdog timer to monitor a process flow of the microprocessor on a task-by-task basis that enables a simple output signal to be used to determine if the watchdog timer is malfunctioning. The watchdog timer has a state machine that increments a state variable from an initial value over a watchdog period. A deterministic service request, received from a microprocessor, controls operation of the watchdog timer. The deterministic service request has an indicator of a monitoring operation to be performed, a password, and an estimated state variable. A comparison element determines if the microprocessor is operating properly based upon a comparison of the received password to an expected password and the received estimated state variable to an actual state variable.

Abstract: A CPU (1) of an information processing apparatus (8) executes software stored in a DRAM (7). A watchdog timer (2) monitors the operation of the software. A hardware monitoring device (4) monitors the state of hardware provided in the information processing apparatus (8). Results of the monitoring are managed by a management LSI chip (3). A non-volatile memory (6) is where failure information is saved. If no watchdog toggles are received for a given period of time, the watchdog timer (2) notifies the CPU (1) with an NMI signal and starts the second round of time counting. The CPU (1) collects failure information from the management LSI (3). The CPU (1) is rebooted through cold reset when failure information collection is completed, and through hot reset when failure information collection is incomplete. In the case of hot reset, the CPU (1) collects failure information after rebooted.

Abstract: A method for determining an operational status of a terminal includes transmitting, from a first processor to a second processor, a request for determining a status of the second processor; executing a timer operation for a time period; determining that the second processor is in a hang state if a response message is not received from the second processor within the time period; and transmitting a reboot command for rebooting the second processor. A terminal includes a first processor to transmit a status request message to a second processor, to initialize a timer to run until expiration of a time period, and to transmit a reboot command to a power management unit if the response message is not received within the time period; and the second processor to transmit a response message prior to expiration of the time period if the second processor is operating normally.

Abstract: A computer program product for handling communication link problems between a first communication means and a second communication means. Data signals, control signals and/or error information are transferred between the first communication means and the second communication means using the communication link. The method includes activating a static identification pattern in the first communication means representing an error information, and stopping a clock signal (Clk) inside the first communication means to freeze a present error condition, in response to a communication link problem being detected, and transferring the activated static identification pattern permanently and/or repeatedly to the second communication means using the communication link.

Abstract: An indication of a start of an execution of a process can be received, and a time counter associated with measuring a time elapsed can be initiated by the execution of the process. The time elapsed by the execution of the process can be compared with a predetermined threshold timeout value, and a report indicating the time elapsed by the execution of the process and whether the elapsed time exceeded the predetermined threshold timeout value can be automatically generated.

Abstract: An integrated circuit 114 includes processing pipeline circuitry 40 comprising a plurality of pipeline stages 44, 46, 48 separated by respective signal value storage circuitry 48, 50, 52. Timing detection circuitry 54, 56, 58 coupled to the processing pipeline circuitry serves to detect as timing violations any signal transitions arrive at the signal value storage circuits outside respective nominal timing windows. Error detection circuitry 66 triggers an error correcting response if the timing detection circuitry indicates a predetermined pattern comprising a plurality of timing violations spread over a plurality of clock cycles of a clock signal CK controlling the processing pipeline circuitry. The predetermined pattern may be two consecutive timing violations.

Abstract: During initial access in which a control unit 8 accesses a disk device 3 for a first time following execution of a command, the control unit 8 waits for an access response from the disk device 3 until a first timeout value, which is set at a time for completing access to the disk device 3, is counted, and during an access retry subsequent to the initial access, the control unit 8 waits for an access response from the disk device 3 until a second timeout value, which is larger than the first timeout value and set at a time required to specify a source of an access error, is counted.

Abstract: A content data recording apparatus includes a code addition unit adding an error correction code to an input content data, a data storing unit temporarily storing the content data, and outputting it, a plurality of nonvolatile memories that enable writing/reading of the content data, a generator generating a write address and a read address, a read buffer temporarily storing the read content data, and outputting it, an error correction unit correcting an error of the content data based on the error correction code, and giving correction impossible notification when the error is not corrected by the error correction code, and a controller carrying out a read control for reading content data from the nonvolatile memories, and carrying out a first rewrite control for controlling the data storing unit so that the data storing unit again outputs content data, and writing the content data again output to the nonvolatile memories.

Abstract: Method or apparatus for passive process monitoring is described. One aspect of the invention relates to monitoring a process executing on a computer system. An operating system is instructed to report at least one event related to process termination. Termination of the process is detected in response to a reported instance of the at least one event by the operating system. A notification is provided to an agent in the computer system that the process has terminated.

Abstract: A method including requesting access to a resource governed by a spinlock; determining an allocation of the resource to a further requester; determining an expiration of a time limit for the spinlock, if the resource is allocated to the further requester; and initiating a fault recovery, if the time limit is expired.

Abstract: A redundancy manager manages commands to peripheral devices in a computer system. These peripheral devices have multiple pathways connecting it to the computer system. The redundancy manager determines the number of independent pathways connected to the peripheral device, presents only one logical device to the operating system and any device driver and any other command or device processing logic in the command path before the redundancy manager. For each incoming command, the redundancy manager determines which pathways are properly functioning and selects the best pathway for the command based at least partly upon a penalty model where a path may be temporarily penalized by not including the pathway in the path selection process for a predetermined time. The redundancy manager further reroutes the command to an alternate path and resets the device for an alternate path that is not penalized or has otherwise failed.

Abstract: Described is an improved method, system, and computer program product for preventing concurrent access and processing of data by multiple threads. The inventive approach may be applied to prevent concurrent access in resequencers.

Abstract: A mechanism is provided for monitoring and verifying a clock state of a chip that does not write out clock state information. Responsive to identifying an access to the chip, the access is scanned to identify a chip register and a clock domain that will be accessed. A determination is made as to whether a bit of a clock trust unit associated with the chip register and the clock domain indicates whether to trust a clock state associated with the bit in a logical clock state unit. Responsive to the bit of the clock trust unit indicating that the clock state associated with the bit in the logical clock state unit is trusted, the clock state from the logical clock state unit is identified. Responsive to the clock state matching the clock state required by the access, the access is forwarded to the chip for execution.