Abstract: The disk controller has a plurality of channel control units, a plurality of cache memories, a plurality of disk control units, and a plurality of internal switch units. Each channel control unit or disk control unit sends to one of the cache memory units a request packet requesting execution of processing. The cache memory unit sends a response packet in response to the received request packet. Each internal switch unit monitors the request packet sent from the channel control unit or disk control unit, and judges whether or not the response packet to the request packet has passed through the internal switch unit within a first given time period since the passage of the request packet. In the case where the response packet has not passed through the internal switch unit within the first given time period, the internal switch unit sends a failure notification.

Abstract: A multiple redundant computer system includes three primary processor modules (PPM) and three redundant processor modules (RPM) operating synchronously. Primary and redundant processor modules are dissimilar in hardware and software for decreasing the probability of a common cause system failure. Each primary and redundant processor module receives input data from associated primary and redundant input modules respectively, executes control program and transfers output data to an output module. The output module produces a system output as the result of 2-out-of-3 voting among output data generated by PPMs. In response to PPMs hard failures, the output module still produces the system output as the result of 2-out-of-3 voting among output data generated by any combination of the PPM and the RPM. As such, the system is able to operate properly even though five-out-of six processor modules have failed.

Abstract: Provided is a method and system for detecting languishing messages of a storage operating system. Requests to access or manipulate data are received as messages by the storage operating system. The messages are processed after the acquisition of resources. If the resources cannot be acquired, then the messages wait on data structures of the storage operating system. An independent thread of the storage operating system identifies messages that are languishing. Information related to the languishing message is recorded and actions to permit messages to continue waiting or cause storage operating system downtime result.

Abstract: A data relay device relays a read request from a source device to a destination device and relays data corresponding to the read request from the destination device to the source device. The data relay device monitors elapsed time from a time point at which a read request is relayed to the destination device. When the elapsed time reaches warning time or error time, the data relay device sends a warning message or an error message to the source device.

Abstract: Embodiments of the present invention provide a method, system and computer program product for de-centralized nodal failover handling in a high availability computing architecture. The system can include multiple different nodes coupled to one another in a cluster over a computer communications network including an initial lead node and remaining auxiliary nodes. The system further can include a messaging service coupled to each of the nodes and nodal failover handling logic coupled to each of the nodes and to the messaging service. The logic can include program code enabled to periodically receive heartbeat messages from the messaging service for the initial lead node and to subsequently detect a lapse in the heartbeat messages, to post within a message to the messaging service a request to become a replacement lead node in response to detecting the lapse in the heartbeat messages, and to periodically post heartbeat messages to the messaging service as the replacement lead node for the initial lead node.

Abstract: To reset only the CPU in a component in an abnormal condition without affecting CPUs of components in a normal condition, a multi-component system, in which a plurality of components each including at least a CPU are connected via a common bus to each other, includes a first reset signal generating unit which generates a reset signal by a switch operation to send the reset signal to respective components and a judge unit which is disposed in each component to determine whether or not resetting of a CPU is allowed. The judge unit inhibits, if the CPU is in a normal condition, the resetting of the CPU in response to the reset signal and resets, if the CPU is in an abnormal condition, the CPU in response to the reset signal.

Abstract: A failover method for a cluster computer system in which a plurality of computers sharing a resource are connected by a heartbeat path for providing each computer with lines for monitoring operations of the other computers and a reset path. Resetting may be conducted based upon a registered priority for resetting the computers.

Abstract: A semiconductor device comprises: a task state storage configured to store an executing state of a processing task of software executed by a CPU and to output an executing state signal to show the executing state of the processing task; a task validity judging section configured to acquire an interruption signal corresponding to the processing task based on a control of the CPU and the execution state signal, and to output a valid signal when the processing task is executed validly; a clear signal output section configured to output a clear signal in response to the valid signal; and a watchdog timer configured to clear a timer count value when the clear signal is acquired within a prescribed time and to output a reset signal when the clear signal is not acquired within the prescribed time.

Abstract: An integrated microprocessor system for safety-critical control systems, comprising at least two microprocessor system modules each comprising at least one processor core, a read/write memory and a memory protection unit, and a read-only memory which is jointly assigned to the processor cores of the microprocessor system modules. Each of the microprocessor system modules executes a main program and a monitoring program which may comprise a plurality of subprograms. If the memory protection unit detects unauthorized operations by one of the programs for accessing a separate address area (A, B) of another program, then the respective memory protection unit assigns a separate address area (A, B) of the read/write memory to the main program and to the monitoring program.

Abstract: Method and apparatus to provide bottleneck processing in a continuous data protection system having journaling. In an exemplary embodiment, system parameter information is collected and analyzed to output bottleneck information.

Abstract: A gaming machine includes a processor adapted to execute a program of a game; a biometric reader configured to capture first biometric data from the player, and a trusted cache. The trusted cache includes a nonvolatile memory that is configured to store the first biometric data; a context data save engine configured to save the context of the program to the nonvolatile memory and to associate the stored first biometric data with the saved context of the program upon the processor receiving a request from the player to suspend game play, and a context data recovery engine configured to recover the saved context from the nonvolatile memory and to cause continued execution of the program from the recovered saved context upon the biometric reader capturing second biometric data from the player that matches the stored first biometric data and receiving a request from the player to resume game play.

Abstract: A transmission device including at least one transmitter/receiver unit that is coupled to another transmission device via a communication line, a power supply unit that supplies power to the at least one transmitter/receiver unit, and a control unit that notifies the another transmission device about first sleep start information specifying time at which an operating mode of the at least one transmitter/receiver unit is to be changed to a sleep mode and that stops the supply of power from the power supply unit to the at least one transmitter/receiver unit at the time specified by the first sleep start information.

Abstract: An apparatus and method for train control utilizing virtual lock stepping are disclosed. In accordance with the illustrative embodiment, an improved method of train control utilizes identical software applications executing on redundant processors. The redundant processors are maintained in virtual lock step to ensure the safety integrity of the overall system being controlled. In accordance with the illustrative embodiment, one software process is a master and one software process is a slave. The master and the slave both independently execute application logic based upon detected events (e.g., input data, etc.). In order to ensure that any anomalies that might result in a hazard are detected in the timeliest manner, and that false anomalies are minimized, the redundant software processes must process the same event within a specified time frame.

Abstract: A processing device includes a timer and a processor core configured to execute an instruction during a debug session. The processing device further includes a timer control module configured to selectively enable/disable the timer based on a characteristic of the instruction. Another processing device includes a timer, a processor core configured to single step execute a sequence of instructions during a debug session, and a timer control module configured to selectively enable/disable the timer during single step execution of each instruction of the sequence of instructions.

Abstract: A method of validating multi-cluster computer interconnects includes calculating a cable interconnect table associated with the multi-cluster computer, and distributing the cable interconnect table to a first transceiver in the first computer cluster and a second transceiver in the second computer cluster. The method also includes connecting a first end of a cable to the first transceiver and a second end of the cable to the second transceiver, transmitting a first neighbor identification from the first cluster to the second cluster, and a second neighbor identification from the second cluster to the first cluster, comparing the first neighbor identification with a desired first neighbor identification from the cable interconnect table to establish a first comparison result and the second neighbor identification with a desired second identification from the cable interconnect table to establish a second comparison result, and generating an alert based on the first and second comparison results.

Abstract: There is described a method for monitoring the functionality of an automation system of a plant comprising at least one main processor, parts of the plant being monitored and controlled using a user software, which is constructed of a number of program modules and which is run on the main processor. A co-processor is assigned to the main processor, and a message is transmitted from the main processor to the co-processor. When received, this message is used by the co-processor to start a monitoring time. When a subsequent message is received, this monitoring time is reset before said monitoring time has elapsed, otherwise a fault is identified once the monitoring time has elapsed.

Abstract: After applications installed in a DSC and PD printer establish a communication procedure, the DSC issues a request to the PD printer. A time required for data transfer involved in the request is predicted. An elapse time until a response is received from the PD printer in response to the request is estimated on the basis of the predicted time. If no response is returned from the PD printer within the estimated elapse time, the request is disabled.

Abstract: A data processing system ensures maximum reaction times. A novel and significantly improved way of ascertaining, checking and/or observing maximum reaction times in data processing systems includes complex or distributed, safe and/or nonsafe systems, particularly between a safe input signal and the corresponding safe output signal, in a flexible and universally applicable manner. Input and/or output data, which are present on the input side of users incorporated in the system, are read in synchronously during each data cycle and checked in relation to currency parameters, which are based on at least one data cycle and associated with the input and/or output data An error is identified in response to a defined discrepancy being reached between at least one currency parameter and a defined currency threshold, and a defined function, particularly a safety-oriented function, are triggered in response to identification of an error.

Abstract: A timing measurement circuit inside a memory chip delays balanced test signals for generating delayed test signals. Each of the delayed test signals is input a corresponding input pin of a memory subsystem of the memory chip. By adjusting delay amount of the delayed test signals, AC timing parameters of the memory subsystem are tested and measured. When the timing measurement circuit is in ring oscillation, a resolution thereof is measured.

Abstract: A clock supply method for supplying a clock to a plurality of processing units includes supplying a clock from a first clock supply unit to processing units forming a first group as a primary clock and to processing units forming a second group as a standby clock; supplying a clock from a second clock supply unit including a clock source different from that of the first clock supply unit to the processing units forming the second group as a primary clock and to the processing units forming the first group as a standby clock; and when a processing unit in the first or second group detects an abnormality of the primary clock, switching the standby clock into use in place of the primary clock being supplied to the processing units that has detected the abnormality belongs; wherein the first and second clock supply units supply clocks with the same frequency.

Abstract: A rapid Byzantine self-stabilizing clock synchronization protocol that self-stabilizes from any state, tolerates bursts of transient failures, and deterministically converges within a linear convergence time with respect to the self-stabilization period. Upon self-stabilization, all good clocks proceed synchronously. The Byzantine self-stabilizing clock synchronization protocol does not rely on any assumptions about the initial state of the clocks. Furthermore, there is neither a central clock nor an externally generated pulse system. The protocol converges deterministically, is scalable, and self-stabilizes in a short amount of time. The convergence time is linear with respect to the self-stabilization period.

Abstract: Recovery is provided in a timing network. A configuration is defined for that network, and in that configuration, an active primary server is identified that provides a clock source for the network. Additionally, an alternate server is identified that can perform the role of the active primary server, should the active primary server fail. In response to a failure of the primary server, the alternate server detects the failure and performs takeover of the primary server.

Abstract: In a particular embodiment, a storage device includes a data storage medium and a read/write circuit coupled the data storage medium via a communication channel. The read/write circuit includes a formatter circuit to receive a read back signal related to data stored on the data storage medium and to produce an output vector related to the read back signal. The read/write circuit further includes a multiple-input multiple-output (MIMO) equalizer coupled to the formatter circuit and adapted to generate an equalized output vector related to the output vector. The read/write circuit also includes a MIMO detector coupled to the MIMO equalizer and adapted to generate hard bit decisions based on the equalized output vector.

Abstract: A system for detecting a work status of a computer system is provided. The system includes a super input/output (Super I/O) chipset, a complex programmable logic device (CPLD), a South Bridge chipset and a device driver. The device driver is configured for driving the Super I/O chipset to generate and send a start signal to the CPLD, and is further configured for driving the Super I/O chipset to periodically generate and send a test signal to the CPLD. The CPLD is configured for receiving the start signal and triggering a clock to start timing from an initial time, monitoring whether a predetermined amount of test signals have been received in a predetermined time, and is further configured for sending a reboot signal to the South Bridge chipset when the predetermined amount of test signals have not been received in the predetermined time. The South Bridge chipset is configured for rebooting the computer system when receiving the reboot signal. A related method is also provided.

Abstract: Devices and methods for microprocessor supervision in a special purpose computer system are provided. One illustrative embodiment includes a first watchdog timer internal to the microprocessor and a second watchdog timer external to the microprocessor. In some cases, the internal watchdog timer may be initiated prior to or during the operating system startup and the external watchdog timer may be initiated after the operating system is up and running. The internal watchdog timer may have a relatively longer timer duration than the external watchdog timer, but is not required in all embodiments. In some embodiments, the internal watchdog timer may monitor the microprocessor's startup sequence and the internal watchdog timer and/or external watchdog timer may monitor the microprocessor when the operating system is up and running. If the microprocessor faults at any time during startup or while the operating system is up and running, the internal and/or external watchdog timer may trigger a microprocessor reset.

Abstract: The present invention relates to computers executing in time-share mode, under the control of their operating systems, a number of separate and independent application programs. The present invention relates in particular to the networks of onboard computer networks of IMA type executing application programs written independently of the hardware specifications of the computers and not permanently resident in the computers. The method of the present invention associates with the digital core of each computer of the network a monitoring state machine operating independently and in having the monitoring state machine monitor the correct observance by the associated computer of the time sequencing of the tasks and memory partition allocations. Furthermore, the monitoring state machines can be configured to execute monitoring service applications of time-out or watchdog type to which the application programs executed by the computers of the network can subscribe.

Abstract: An interrupt control circuit has a condition storage circuit for storing and outputting a reference time and an error detection circuit for outputting a signal indicating error detection when an interrupt request is not generated within a period from a predetermined time till the reference time elapses.

Abstract: An apparatus and method for reducing false triggering of a signal due to an electrostatic discharge event are disclosed. The method includes detecting a high voltage on a signal received at an input of a delay circuit and delaying the signal between the input of the delay circuit and an output of the delay circuit for a predetermined amount of time. If a low voltage is detected on the signal after the predetermined amount of time, the high voltage is prevented from propagating to the output of the delay circuit.

Abstract: A circuit arrangement for supporting and monitoring a microcontroller, which is constructed externally of the microcontroller, comprises a watchdog circuit for monitoring the microcontroller, which circuit outputs an error signal if not reset by the microcontroller within a watchdog period, and an interrupt circuit, which feeds important system messages to the microcontroller as interrupt events for processing. In order correctly to combine interrupt processing and watchdog operation, the watchdog circuit is connected to the interrupt circuit and cooperates therewith in such a way that the interrupt circuit feeds at most a predetermined number of interrupt events to the microcontroller within a watchdog period.

Abstract: One process of a processing environment maintains state on behalf of another process of the processing environment, and uses that state to determine if a problem exists with the another process. The one process is a non-volatile process, while the another process is a volatile process.

Abstract: Static timing analysis attempts to exhaustively analyze all critical paths of a design. With ever decreasing geometries and ever increasing design complexity, manually identifying timing violations with standard static timing analysis can be very complex and time consuming. A static timing analysis tool can advantageously manage multiple runs having different modes and corners and automatically merge the results generated by the runs. The STA tool can perform the runs either in parallel or in series. Advantageously, the STA tool can save the full timing analysis generated by each run and then extract information from these saved results to form merged results for the design. These merged results can provide different levels of analysis coverage, supply path information at various levels of detail, allow selectable accessibility to information, and highlight propagation of timing changes/violations in the design.

Abstract: The disk controller has a plurality of channel control units, a plurality of cache memories, a plurality of disk control units, and a plurality of internal switch units. Each channel control unit or disk control unit sends to one of the cache memory units a request packet requesting execution of processing. The cache memory unit sends a response packet in response to the received request packet. Each internal switch unit monitors the request packet sent from the channel control unit or disk control unit, and judges whether or not the response packet to the request packet has passed through the internal switch unit within a first given time period since the passage of the request packet. In the case where the response packet has not passed through the internal switch unit within the first given time period, the internal switch unit sends a failure notification.

Abstract: The present invention offers an advanced control software verification technology, particularly, an assertion-based verification technology, by providing a control microcomputer verification device and vehicle-mounted control device that exhibit improved verification efficiency. Assertion-based verification is performed with a verification device that has a hardware configuration in which the verification device is independent of a CPU core of a microcomputer but operates in parallel with the CPU core of the microcomputer, which sequentially executes control software. The hardware to be employed to achieve the above purpose is a finite state machine based on microprogrammed control. An interrupt factor is branched immediately before an interrupt controller for the microcomputer and used as a transition input. When an abnormal transition is detected, a warning is output to the microcomputer as an interrupt or output to the outside in the form of a signal.

Abstract: A CPU reads a clear pattern held in a register in a watchdog timer when a system is booted up or reset, thereby determining whether or not the boot-up or the reset is a reset performed by the system or a reset due to runaway of a program to be executed and performing a process for booting up the system so as not to restart the task in which the runaway has occurred.

Abstract: An electronic device and wireless base station for maintaining a persistent connection is provided. In an embodiment, a system includes an electronic device that connects to a web-server via a physical link that is bandwidth-constrained. The physical link also includes a wireless base station and at least one network address translation (“NAT”) router that is configured to terminate idle connections between the client and the web-server. One of the electronic device and the wireless base station is configured to send keep-alive packets to the web-server in order to reduce the likelihood of the NAT router terminating the connection. The keep-alive packets are sent on a variable basis that is intended to reduce bandwidth consumption while ensuring that the NAT router does not deem the connection idle and terminate the connection.

Abstract: A method and apparatus for testing a data transfer system. The method comprises the steps of storing a first table, the first table noting at least a time of issuance of at least one command and a time of completion of the command and comparing the time of issuance of the command and the time of completion of the command. A timeout condition is registered if the processor determines that a time longer than a predetermined time elapsed between the time of issuance of the command and the time of completion of the command.

Abstract: An invention is disclosed for a computer software timeout algorithm that reduces the amount of list manipulation needed to satisfy system or network requirements for scheduling and cancelling timeout requests to determine whether the expiration time has been reached for execution of an input/output (I/O) request, thereby requiring action to cancel the I/O operation if it has not yet been completed.

Abstract: The present invention supports container-provided EJB timer service that allows EJB instances dealing with timed events to create and register for a timer, which is scheduled to send notifications either at a specific time and/or after a specific elapsed duration, or at specific recurring intervals. When the timer expires, certain business logic inside the EJB instance will be invoked to handle the timeout event. When the cancel method of a timer is called, the timer may cease to exist. The timer is capable of retrying failed timeout under certain conditions when the current invocation of timeout logic fails. In addition, the timer is capable of monitoring the access from multiple registered EJB instances enrolled in transactions under multi-threaded environment, and restricting the access to the timer from EJB instances in certain threads until the current transaction accessing the timer commits to prevent a potential conflicting situation.

Abstract: A method for monitoring a system, having a control unit defined as a master and a number of control units defined as slaves, with the aid of a monitoring module, in which in reply to an inquiry from the master and the slaves a response is given in each instance and a joint response provided on the basis of these responses is checked by the monitoring module.

Abstract: A system and method for detecting and handling errors in a computer system are disclosed. The invention is configurable to permit selecting of timelength or time out values, assigned interrupts to be generated and error recover procedures so that failures of system events can be promptly detected and recovered from. The watchdog timer is started with a timelength or time out value and generates an interrupt (i.e., is triggered) if the period of time set as the timelength passes without receiving a reset. The watchdog timer interface interacts and controls the hardware based timer to obtain this watchdog timer functionality. The hardware based timer is generally a high precision timer that exists in hardware architecture for a computer system and is usable by system software. The watchdog timer interface controls and sets various parameters and/or registers of the hardware based timer in order to provide the desired functionality of a watchdog timer.

Abstract: A network storage appliance is disclosed. The appliance includes a chassis enclosing a backplane, and a server enclosed in the chassis and coupled to the backplane. The appliance also includes storage controllers enclosed in the chassis, each coupled to the backplane, which control transfer of data between the server and storage devices coupled to the storage controllers. The storage controllers also control transfer of data between the storage devices and computers networked to the appliance and external to the appliance. The storage controllers and the server comprise a plurality of hot-replaceable blades. Any one of the plurality of blades may be replaced during operation of the appliance without loss of access to the storage devices by the computers. In one embodiment, the server executes storage application software, such as backup software for backing up data on the storage devices, such as to a tape device networked to the server.

Abstract: A method of reading a data block from a sector of a recording media is described. The data block from the sector of the recording channel is decoded with an ECC decoder (first trial). The data block is re-decoded (second trial) using an adjusted timing recovery block that is adjusted based on the decoded data block, if the number of errors exceeded an error correction capability of the ECC decoder on the first trial. In one embodiment, the data block is reread from the same sector of the recording channel using the adjusted timing recovery block that is adjusted based on the re-decoded data block. The data block is subsequently jointly decoded with the waveforms obtained from the second trial by a possibly modified sequence detector, if the number of errors exceeded the error correction capability of the ECC decoder during the second trial.

Abstract: A method, apparatus, and system of improved handling of clustered media errors in raid environment are disclosed. In one embodiment, a method includes starting a command timer when a firmware accepts a command from a host, tracking an amount of time the command spends on handling of a clustered media error through the command timer, and stopping the command timer when at least one of the command is completed and a time limit expires. The method may complete a read as a success when a host IO is a read command. The method may complete a write as a success, after writing parity, and data when the host IO may be a write command.

Abstract: An administrator can specify a script sequence including one or more system scripts and database scripts. A graphical user interface is provided to allow the administrator to specify an execution order of individual scripts in the script sequence and a timeout interval for when the script sequence will complete. Once the script sequence is specified, the script sequence can be run without further intervention by the administrator.

Abstract: The invention relates to a recovery of a hardware module of an electronic device from a malfunction state. The hardware module is connected via a signal line to a recovery component of the device, a state of the signal line being controlled by the hardware module. The recovery component monitors a state of the signal line. Whenever the signal line is detected not to assume a predetermined state during a predetermined period of time, the recovery component causes a hardware reset of the hardware module.

Abstract: Networks and methods are disclosed for synchronizing time stamps of peer devices. In one embodiment, a first communication node comprised of peer devices is connected to a second communication node. The first and second communication nodes communicate according to a protocol that requires monotonically increasing time stamps. When in operation, a peer device transmits a message to the second communication node with a time stamp. If the peer device receives an error response from the second communication node indicating that the time stamp does not comprise an increasing time stamp, then the peer device increases the time stamp. The peer device then transmits the message to the second communication node with the increased time stamp. This process continues each time the peer device receives an error response from the second communication node until the time stamp is increased sufficiently to comprise a monotonically increasing time stamp.

Abstract: A method for monitoring a process execution of a plurality of sequentially executed processes starts one of a plurality of timers in cyclic permutation when one of the processes is started, and outputs a first error signal when a period of time recorded by one of the timers exceeds a predefined maximum period of time.

Abstract: The present invention provides a computer implemented method and apparatus for unmounting file systems from a plurality of file servers. The method comprises of issuing an unmount command targeting a file system of a first server among the plurality of file servers. The timeout period is then expired without receiving an unmount acknowledgement associated with the unmount command. Thus, the timeout period is associated with an allowable time for the file system to acknowledge unmounting. In response to expiring the timeout period, a ping is transmitted to the first server among the plurality of file servers. The ping timeout then expires based on a failure to receive a ping acknowledgment corresponding to the ping. This action marks the first server for a later retry of unmounting to form a marked set based on the first server.

Abstract: An apparatus for testing an IC device includes a test signal generator for generating a predefined sequence of test signals that are input to the IC device. A timing skew monitor is provided for monitoring the test signals input in the IC device and a signal output from the IC device for a predetermined time period, and creating an array indicating an execution or a nonexecution of signal timing combinations of one of the test signals relative to at least one of the other test signals within the predetermined time period by the IC device. A determination as to whether the desired signal timing combinations of the test signals have been executed by the IC device is made by an operator.

Abstract: A backplane interface adapter with error control and redundant fabric for a high-performance network switch. The error control may be provided by an administrative module that includes a level monitor, a stripe synchronization error detector, a flow controller, and a control character presence tracker. The redundant fabric transceiver of the backplane interface adapter improves the adapter's ability to properly and consistently receive narrow input cells carrying packets of data and output wide striped cells to a switching fabric.