Abstract: Upon a receipt of an advance notice, an active system computer on which asynchronous replication is performed with a standby system computer stops a business application and transmits to the standby system computer transmission start information indicating start of data synchronization, data accumulated in a transmission queue 118, and transmission completion information indicating completion of the data synchronization in this order. The standby system computer generates and holds first reliability guarantee information indicating that the data received before the transmission start information upon a receipt of the transmission start information, and generates and holds second reliability guarantee information indicating that the data received before the transmission completion information is reliable data upon a receipt of the transmission completion information.

Abstract: An apparatus, system, and method are disclosed for probing a computer process. A probe parameter module determines a process identifier, a probe interval, and a probe action. The process identifier uniquely identifies a computer process. A start timer module starts a timer with a timer interval in response to the computer process entering an executing state on a processor core. The timer interval is based on the probe interval and on an amount of time elapsed between a probe start time and the computer process entering the executing state on the processor core. An action module executes the probe action in response to the timer satisfying the timer interval while the computer process is in the executing state on the processor core.

Abstract: A facility is provided to enable operator message commands from multiple, distinct sources to be provided to a coupling facility of a computing environment for processing. These commands are used, for instance, to perform actions on the coupling facility, and may be received from consoles coupled to the coupling facility, as well as logical partitions or other systems coupled thereto. Responsive to performing the commands, responses are returned to the initiators of the commands.

Abstract: A method includes capturing data that is representative of actions performed by each of a plurality of human user operated clients as they interact with an online software application, loading at least one or more portions of the captured data into one or more automated simulation clients, and using the one or more automated simulation clients to perform load testing of an online server system. A system includes a data capturing stage, one or more automated simulation clients, and a configuration stage.

Abstract: A wake-up signal test system to test a wake-up signal output by a platform controller hub (PCH) of a motherboard includes a test card and an oscillograph. The test card includes a board with an edge connector, and a button. The button is connected between a first ground pin and a first wake-up signal pin of the edge connector. When the edge connector is inserted into a peripheral component interconnect express (PCIe) socket of the motherboard, the first ground pin is connected to a second ground pin of the PCIe socket, the first wake-up signal pin is connected to a second wake-up pin of the PCIe socket. When the button is pressed, the first wake-up signal pin is connected to the first ground pin to output a low level signal to the PCH to wake up the motherboard. The oscillograph displays a voltage state of the low level signal.

Abstract: A system includes a computer(s) coupled to a data storage device(s) that stores a training data repository and a predictive model repository. The training data repository includes retained data samples from initial training data and from previously received data sets. The predictive model repository includes at least one updateable trained predictive model that was trained with the initial training data and retrained with the previously received data sets. A new data set is received. A richness score is assigned to each of the data samples in the set and to the retained data samples that indicates how information rich a data sample is for determining accuracy of the trained predictive model. A set of test data is selected based on ranking by richness score the retained data samples and the new data set. The trained predictive model is accuracy tested using the test data and an accuracy score determined.

Abstract: An automation process verifies that a test bed includes a set of devices specified by at least one script which are to be executed by the automation process on the test bed. The test bed is locked and the set of devices is allocated to the automation process. Performance data collection and logging for the set of devices is started and the at least one script is executed on the set of devices. After executing the at least one script, the set of devices is de-allocated and the test bed is unlocked. A notification is generated indicating that the at least one script has been executed.

Abstract: Methods and apparatuses are described for assigning random values to a set of random variables so that the assigned random values satisfy a set of constraints. An embodiment can receive a set of constraints, wherein each constraint is defined over one or more random variables from a set of random variables. Next, the embodiment can generate a circuit model based on the set of constraints, wherein assignable values for at least one node in the circuit model are represented in multiple value systems. The embodiment can then assign random values to the set of random variables based on the circuit model.

Abstract: An embodiment providing one or more improvements includes a memory loading system and method for at least managing testing of a memory unit using a memory test system and responsive to at least completion of testing and passing the testing, loading non-testing content into the memory unit for delivery to a customer.

Abstract: A particular system includes a processor and a network interface configured to send and receive messages via a network using an asynchronous computer communication protocol. The system may include two or more buffers, such as an ingress buffer and an egress buffer. The system may include a memory accessible to the processor. The memory may include first node instructions that are executable by the processor to implement one or more functions of a first node. The memory may also include one or more script callbacks. The script callbacks may be executable by the processor to at least one of provide: the first content to a test script to be modified before the first content is provided to the first node instructions from the ingress buffer, and provide the second content to the test script to be modified before the outgoing message is provided to the egress buffer.

Abstract: A method is provided in which a first error test may be performed on a memory that includes an integrated error correcting code (ECC) portion. The functionality of the ECC portion may be bypassed in the first error test. A second error test may be performed on the memory, where the second error test includes testing the functionality of the ECC portion. Also provided is an apparatus including a memory device and an error correcting code (ECC) circuit. The apparatus also includes a first switching device adapted to select a first input signal or a second input signal and a second switching device adapted to select one of a signal from the memory device or a signal from a portion of the ECC circuit. Also provided are computer readable storage devices encoded with data for adapting a manufacturing facility to create the apparatus and for adapting a processor to perform the method above.

Abstract: A storage system provides highly flexible data layouts that can be tailored based on reliability considerations. The system allocates reliability values to logical containers at an upper logical level of the system based, for example, on objectives established by reliability SLOs. Based on the reliability value, the system identifies a specific parity group from a lower physical storage level of the system for storing data corresponding to the logical container. After selecting a parity group, the system allocates the data to physical storage blocks within the parity group. In embodiments, the system attaches the reliability value information to the parity group and the physical storage units storing the data. In this manner, the underlying physical layer has a semantic understanding of reliability considerations related to the data stored at the logical level.

Abstract: Scan chains are used to detect faults in integrated circuits but with the size of today's circuits, it is difficult to detect and locate scan chain faults, especially when the scan data in and scan data out have been compressed. A method for debugging scan chains includes selecting a scan chain for debugging using a scan chain selection block and then providing scan test vectors to the selected scan chain. The scan test vectors undergo various scan test stages to generate scan response vectors. The scan response vectors are compared with ideal response vectors to identify a failing scan chain.

Abstract: A Test Wrapper and associated Test Access Mechanism (TAM) architecture for facilitating testing of IP blocks integrated on a System on a Chip (SoC). The TAM architecture includes a Test Controller and one or more Test Wrappers that are integrated on the SoC proximate to IP blocks. Test data and commands corresponding to input from an external tester are packaged by the Test Controller and sent to one or more Test Wrappers via an interconnect fabric. The Test Wrappers interface with one or more IP test ports to provide test data, control, and/or stimulus signals to the IP blocks to facilitate circuit-level testing of the IP blocks. Test results for the circuit-level tests are returned to the Test Controller via the fabric. Test Wrappers may be configured to pass through interconnect signals, enabling functional testing of IP blocks to be facilitated via test packages and test results transmitted between the Test Controller and the IP blocks via the fabric.

Abstract: A Test Access Mechanism (TAM) architecture for facilitating testing of IP blocks integrated on a System on a Chip (SoC). The TAM architecture includes a Test Controller and one or more Test Wrappers that are integrated on the SoC proximate to IP blocks. Test data and commands corresponding to input from an external tester are packaged by the Test Controller and sent to the Test Wrappers via an interconnect fabric. The Test Wrappers employ one or more test ports to provide test data, control, and/or stimulus signals to the IP block to facilitate circuit-level testing of the IP block. Test results for the circuit-level tests are returned to the Test Controller via the fabric. Test Wrappers may be configured to pass through interconnect signals, enabling functional testing of IP blocks to be facilitated via test packages and test results transmitted between the Test Controller and the IP blocks via the fabric.

Abstract: Static data race analysis of at least a portion of a multi-threaded application in order to identify potential data race defects in the multi-threaded application. The static data race analysis includes intra-component static analysis as well as inter-component static analysis. The intra-component static analysis for a given component involves identifying a set of memory accesses operations in the component. For each of at least one of the set of memory access operations, the analysis determines whether there is a data race protection element associated with the memory access command.

Abstract: A trouble prediction apparatus includes a trouble-occurred device information storage unit that stores therein trouble occurrence information of trouble-occurred devices in which a trouble has occurred out of a plurality of management target devices; a calculating unit that calculates a trouble occurrence probability based on the trouble occurrence information; and a predicting unit that predicts a trouble of a prediction target device out of the management target devices by referring to the trouble occurrence probability.

Abstract: In examples, apparatus and methods are provided for an integrated circuit. The integrated circuit includes a first integrated circuit portion having a main power domain and a second integrated circuit portion having a collapsible power domain. The integrated circuit also has a level shifter having an input coupled to the second circuit portion and an output coupled to the first integrated circuit portion. The level shifter is configured to hold constant the level shifter output when power to the collapsible power domain is collapsed. A quiescent drain current measurement circuit can be coupled to test at least a part of the second integrated circuit portion. A boundary scan register can be coupled between the level shifter output and the first integrated circuit portion. The integrated circuit can also include a power management circuit.

Abstract: System, method and computer program product for a multiprocessing system to offer selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). Each paired microprocessor or processor cores that provide one highly reliable thread for high-reliability connect with a system components such as a memory “nest” (or memory hierarchy), an optional system controller, and optional interrupt controller, optional I/O or peripheral devices, etc. The memory nest is attached to a selective pairing facility via a switch or a bus.

Abstract: A communication apparatus includes a first unit that transmits predetermined data to an external apparatus, a second unit that transmits a command to the external apparatus, and a control unit that controls the second unit to transmit a first command and a second command to the external apparatus. The control unit controls the first unit not to transmit the predetermined data to the external apparatus if the external apparatus is not in a power-on state. Further, if the external apparatus is in the power-on state, the control unit controls the first unit to transmit the predetermined data to the external apparatus after the second command is transmitted to the external apparatus.

Abstract: A keyboard module testing system includes a computer host, a test frame, an encoding program and a main test program. The encoding program and the main test program are both installed in the computer host. The test frame is connected with the keyboard module and the computer host for generating plural key codes. The encoding program is used for assigning plural key codes to respective keys. According to the plural key codes, the main test program can recognize which key is being tested.

Abstract: A method for resetting and reenumerating a Universal Serial Bus (USB) device, an Electrical Fast Transient/Burst (EFTB) unit of a USB device for resetting and reenumerating the USB device and a USB device are described. In one embodiment, a method for resetting and reenumerating a USB device involves detecting a USB reset command from a host device at a USB device, setting a reset flag in the USB device in response to the detecting of the USB reset command, determining if the USB device is in a corrupted state in response to the reset flag, and causing a Single Ended Zero (SE0) signal to be issued to reset the USB device out of the corrupted state and reenumerate the USB device back to the host device if the USB device is determined to be in the corrupted state. Other embodiments are also described.

Abstract: According to one embodiment, a system for creating a list of related defects in a network environment includes a processor, and a computer readable storage medium having computer readable program code embodied therewith. The computer readable program code includes computer readable program code that, when executed by the processor, causes the system to acquire a device list related to devices in multiple paths of a network, computer readable program code that, when executed by the processor, causes the system to query one or more information sources using the device list to retrieve defect data from the one or more information, sources, computer readable program code that, when executed by the processor, causes the system to create a list of related defects based on the retrieved defect data, and computer readable program code that, when executed by the processor, causes the system to output the list of related defects.

Abstract: A fault tolerant scannable glitch latch for use with scan chains that enable reset, debug and repairability of machines and parts is described. A scan shift enable signal controls a switch such that a stuck-at zero fault on a data input line is prevented from driving voltage to a state node or pulling the state node high during a scan chain operation. Propagation of the stuck-at zero fault is therefore eliminated. The scan shift enable signal also controls a switch that enables a parallel path to ground for the scan data and state node which would otherwise have been driven high due to the stuck-at zero fault.

Abstract: A “Compatibility Tester” extracts observable behaviors from different system implementations (e.g., software, operating systems, device drivers, hardware interfaces, etc.), then performs compatibility testing via comparisons of the extracted behaviors. Traces (e.g., bus level signals between controllers and hardware devices or commands between software components) representing observable behaviors of different implementations of a system are captured. Temporal and structural rules are then mined from these traces. The mined rules (or a model constructed from those rules) are used by a “Rule Checking” process that determines whether reference rules (mined from a known compatible system) are compatible with rules mined from test traces of a second system. Invalid rules are flagged as behavioral compatibility bugs.

Abstract: Systems and methods are provided for improving fidelity of a quantum operation on a quantum bit of interest. A controlled quantum gate operation, controlled by the quantum bit of interest, id performed on an ancillary quantum bit. An energy state of the ancillary quantum bit is measured to facilitate the improvement of the fidelity of the quantum operation.

Abstract: Disclosed is a method and apparatus for realizing an effective service adaptation in consideration of delay factors possibly generated in combining (or compositing) already existing Web services in constituting a composite Web service. A failure or delay in executing a Web service is predicted in consideration of features (or factors) of QoS of Web services constituting a composite Web service, and a substitute Web service is executed or a speculative execution is performed to thus stably and quickly constitute a composite Web service.

Abstract: Embodiments include a file system data structure and file system recognition APIs that may allow an operating system to identify a partition of a storage device as having a valid file system, even if the operating system does not know how to access the file system a priori. File systems can implement these data structures in a standardized, known location within a partition on the storage device such that an operating system may use APIs or other functions to examine the known location for the presence of these data structures. Information on how to interpret the data structure may be obtained using a network or other source.

Abstract: The system and method for diagnosing information technology systems in multiple virtual parallel universes described herein may create virtualized parallel universes that represent a problematic information technology system. The virtualized parallel universes may then be diagnosed to identify potential solutions to a problem experienced in the problematic information technology system (i.e., the parallel universes may be diagnosed without disrupting the live problematic system). For example, the problematic information technology system may be cloned in response to a diagnostic request associated therewith to create various virtualized parallel universes representing the problematic information technology system. The parallel universes may then conduct various problem resolution steps to identify a potential solution to the problem, which may then be applied to the problematic information technology system to resolve the problem associated therewith.

Abstract: Utilize a pattern generator to write a predetermined logic voltage to each memory cell of a memory chip. Read a predetermined logic voltage stored in the memory cell. Compare the predetermined logic voltage stored in the memory cell with the predetermined logic voltage to determine if the memory cell is a good memory cell or not and store a determination result corresponding to the memory cell in a data latch of the memory chip. And determine if the memory chip is a good memory chip or not according to determination results of all memory cells of the memory chip stored in the data latch of the memory chip.

Abstract: Methods, circuits and systems are provided to test data paths that traverse multiple clock domains using a common capture clock that is applied to multiple domains. Test data is launched to a first clock domain, and each of the clock domains is selected to receive the common capture clock signal while the test data propagates through the selected clock domain. The test data is capture after it has propagated through each of the multiple domains in response to the shared domains. Applying a common capture clock to each of the different domains eliminates hold time errors that might otherwise occur as the data transitions from one clock domain to another.

Abstract: One embodiment provides a method for scalable predictive failure analysis. Embodiments of the method may include gathering memory information for memory on a user computer system having at least one processor. Further, the method includes selecting one or more memory-related parameters. Further still, the method includes calculating based on the gathering and the selecting, a single bit error value for the scalable predictive failure analysis through calculations for each of the one or more memory-related parameters that utilize the memory information. Yet further, the method includes setting, based on the calculating, the single bit error value for the user computer system.

Abstract: According to one embodiment, a certain amount of data is held in the memory cells, and after a state of the data held in the memory cell is transferred into an indefinite state, data autonomously held in the memory cell is read, and a change of the threshold voltage of transistors is diagnosed on the basis of the distribution of the data autonomously held in the memory cell.

Abstract: A method and a device for handling exceptions in an embedded system are disclosed. The method comprises: establishing an exception callback linked list for an application program when the application program is running; registering an exception handling function and the corresponding relation between the exception handling function and the exception information into the exception callback linked list by the application program; when the exception is captured, searching the corresponding relation between the exception handling function and the exception information to locate an exception handling function matching the captured exception, according to the exception information of the captured exception; after a matched exception handling function is located, calling and executing the matched exception handling function to perform the exception handling.

Abstract: Systems, methods, and machine readable and executable instructions are provided for replaying captured network traffic. A method for replaying captured network traffic can include replaying multiple captured network traffic files simultaneously on the same network device, the captured network traffic files including original network traffic captured from N original connections between C original clients and S original servers. During replaying, rewriting IF addresses and/or port number information of data packets comprising the original network traffic to reflect test network traffic from M test connections between X test clients and Y test servers, where at least X is different than C or Y is different than S. The method further includes modifying checksums, during replaying, to correct values corresponding to the rewritten IF addresses and port number information. N, C, S, M, X, and Y are positive integers.

Abstract: A component in a graph-based computation having data processing components connected by linking elements representing data flows is updated by receiving a rule specification, generating a transform for transforming data based on the rule specification, associating the transform with a component in the graph-based computation, and in response to determining that a new rule specification has been received or an existing rule specification has been edited, updating the transform associated with the component in the graph-based computation according to the new or edited rule specification. A computation is tested by receiving a rule specification including a set of rule cases, receiving a set of test cases, each test case containing a value for one or more of the potential inputs, and for each test case, identifying one of the rule cases that will generate an output given the input values of the test case.

Abstract: Soft error detection is performed by computation of states based on formal methods and by simulating a synthesized target identification logic together with the design. Soft errors may be simulated in response to detecting that a simulated state of the design is comprised by the states. A BDD representation of the design may be utilized to determine the states. A Boolean satisfiability problem may be defined and solved using an all-SAT solver in order to determine the states.

Abstract: Techniques are described for increasing a lifetime of blocks of memory. In operation, respective life expectancy scores for each of the blocks are calculated based at least in part on a respective number of times each of the blocks is respectively erased, and further based at least in part on at least one other factor that affects the lifetime of the blocks. An order to write and recycle the blocks is determined, based at least in part on at least some of the respective lifetime expectancy scores. A total amount of the blocks that are erased and written is minimized while lifetime expectancy score variation between the blocks is equalized.

Abstract: A method for controlling a test process of an electronic device using a data processing device creates test control data to test the electronic device, selects a test item of the electronic device sequentially according to test bits in the test control data, and modifies a test bit corresponding to the selected test item to obtain modified test control data if the electronic device passes the selected test item. The method further compares the modified test control data with the created test control data if all the test items have been performed to determine if the electronic device passes the test process, and outputs a signal indicating success if the electronic device passes the test process.

Abstract: A computer startup test apparatus for turning on a computer automatically, includes a control module, a switch module, and a startup module. The control module is configured to output control signals, data signals and clock signals. The switch module is configured to receive the control signals, and turn on the computer according to the received control signals. The startup module is configured to receive the data signals and clock signals, and restarts the computer according to the received data signals and clock signals. The control module stores a predetermined test time. The control module records abnormal information and test times when the computer restarts, and outputs the control signals to turn on the computer using the switch module when the computer cannot restart.

Abstract: A system and method is provided for providing assured recovery for a distributed application. Replica servers associated with the distributed application may be coordinated to perform integrity testing together for the whole distributed application. The replica servers connect to each other in a manner similar to the connection between master servers associated with the distributed application, thereby preventing the replica servers from accessing and/or changing application data on the master servers during integrity testing.

Abstract: A structure, and corresponding operating techniques, are presented for the internal controller to memory circuit interface for memory systems such a flash memory card or other similarly structured devices. The interface between the controller circuit and memory circuit (or circuits) includes a feedback process where the amount of error that arises due to controller-memory transfers is monitored and the transfer characteristics (such as clock rate, drive strength, etc.) can be modified accordingly. For example, in addition to transferring a set of data, the transmitting side also generates and transmits a corresponding hash value for the set of data. When the set of data is received on the other side, a hash value is also generated there and compared to the received hash value to determine if these was transmission error. If there is no error, the transfer rate could, for example, be increased, while if there were error, it could be decreased.

Abstract: A healthcare communication system includes a first plurality of computer devices operable as a nurse call system. The first plurality of computer devices has core nurse call functionality. The system also includes a second plurality of computer devices communicatively coupled to the first plurality of computer devices. The first plurality of computer devices are interconnected logically and/or physically in a tiered architecture arrangement to provide fault isolation among the tiers so that faults occurring in computer devices of one tier don't affect the operability of computer devices in other tiers and so that faults occurring in any of the second plurality of computer devices don't affect the core nurse call functionality of the first plurality of computer devices.

Abstract: A method and apparatus are provided for determining the probability that one or more problems have occurred within a complex multi-host system. A probabilistic model representing the cause/effect relationships among potential system problems identifies the probability that a problem occurred in the system based at least on system measure states that are input into the probabilistic model. System measure states may be determined based on an aggregation of system measurement values taken periodically. Aggregating system measurement values may be performed over system measurement values that were taken during a recent time interval. A rolling count aggregation function may be used for this purpose. A rolling count function counts the number of system measurement values taken within the recent time interval that lie within a particular range of values. A system measure state may be determined based on whether the rolling count exceeds a threshold associated with the system measure.

Abstract: Methods and apparatus for collection, validation, analysis, and automated error correction of data regarding user interaction with content. In one embodiment, statistical methods are used to arrive at expected values for the collected data. The data is compared to the expected value and must meet one or more acceptance criteria (e.g., be within a prescribed range) to be considered valid. The prescribed range is determined by the network operator, or a computer program adapted to generate this value. The invention enables a network operator to assess a large volume of data without requiring significant amounts of manual monitoring and/or error correction. The ability to collect, validate and analyze data across multiple platforms is also provided. Still further, an automated system capable of learning evaluation and error correction patterns is disclosed.

Abstract: A semiconductor circuit for testing a logic circuit, the semiconductor circuit including: an exclusive OR circuit receiving an input testing signal to a circuit under testing and a output testing signal from the circuit under testing; a multiplexer receiving a result signal output from the exclusive OR circuit and a clock signal; and a flip-flop storing a logical value represented by a captured signal in synchronization with a multiplexed signal output from the multiplexer, the captured signal being selected from a entered signal(I) and a data signal that is output from another semiconductor circuit for testing.

Abstract: A system and method for testing a control module includes a microprocessor, where the microprocessor has a programming environment. The programming environment has a test data structure, a configuration data structure, and a monitor data structure each containing data. At least one test data instance is associated with the test data structure and at least one configuration data instance is associated with the configuration data structure. The configuration data instance is a diagnostic test that monitors a parameter of the microprocessor, and the monitor data structure creates the test data instance such that each test data instance corresponds to one of the configuration data instances. The program includes a first control logic for associating the test data structure, the configuration data structure and the monitor data structure as part of a core infrastructure portion of the programming environment, where the core infrastructure portion of the program is static.

Abstract: A method, system, and computer usable program product for energy-efficient soft error failure detection and masking are provided in the illustrative embodiments. A soft error is injected to occur during execution of a set of instructions. If an output of the execution of the set of instructions is incorrect, a record is made of the instruction that was affected by the injected soft error and led to the incorrect result. This identified instruction is designated as vulnerable to the soft error. Several soft errors are injected with different input data sets over several executions of the same set of instructions, and a probability of each instruction in the instruction set is computed, the probability of an instruction accounting for the vulnerability of the execution of the instruction sets to errors that affect the instruction. A report including several probabilities of instruction vulnerabilities is produced.

Abstract: The network fault manager described herein may include one or more processors configured to detect alarms. For example, the one or more processors may periodically sample rates at which similar events that relate to occurrences on a network arrive, compare the periodically sampled rates to a first threshold, and determine whether a preexisting alarm exists. In response to a number of the periodically sampled rates that exceeded the first threshold within a preceding time window exceeding a second threshold and the preexisting alarm not existing, the one or more processors may assert a first alarm. Otherwise, if the number of periodically sampled rates that exceeded the first threshold within the preceding time window exceeds the second threshold but the preexisting alarm does exist, the one or more processors may maintain the preexisting alarm for a predetermined time period.

Abstract: A system-on-chip (SoC) includes a core, a plurality of power domain blocks, and a power control circuit including a debug circuit. The power control circuit is configured to control power supplied to the core and each of the power domain blocks, and the debug circuit is configured to debug the power control circuit.