Abstract: A method of network testing relies on communication with an unaddressed test device. The method includes collection of network addresses from packets passing through the test device and a discovery procedure. The collected addresses are provided to a remote control device, and used for communication between the test device and the control device.

Abstract: A method and system for performing parallel tasks in a computer system includes invoking a single-threaded operating environment in a computer, invoking under the single-threaded operating environment a first task to be performed by a first processor, invoking under the single-threaded operating environment a second task to be performed by a second processor, while the first task is still being performed, and receiving results from the first and second tasks.

Abstract: A test module comprising a compression information storage section that stores a plurality of pieces of compression information that each associate a pattern sequence with a piece of pattern sequence identification information; a basic pattern storage section that stores, as a group of basic patterns, a plurality of pieces of pattern sequence data that each include the pattern sequence or the pattern sequence identification information in association with a command; an instruction information storage section that stores instruction information indicating a processing order for the basic patterns; a selecting section that selects, from among the pieces of compression information stored in the compression information storage section, compression information to be used for the basic pattern to be processed according to the processing order indicated by the instruction information; a basic pattern reading section that reads, from the basic pattern storage section, the pattern sequence data included in the basic p

Abstract: There is provided a test module comprising a random number generator that generates a pseudo random pattern and includes a controller that generates a register selection signal based on a control instruction stored on an instruction memory, a plurality of polynomial configuration registers one of which is selected by the register selection signal, each polynomial configuration register having polynomial data stored therein, a plurality of initial value configuration registers one of which is selected by the register selection signal, each initial value configuration register having an initial value stored therein, and a random number generation shift register that loads the initial value from the selected one of the plurality of initial value configuration registers and sequentially generates the pseudo random pattern based on the polynomial data stored in the selected one of the plurality of polynomial configuration registers.

Abstract: Mechanisms are provided for use with a microprocessor chip, for storing selected reliability information in an on-chip non-volatile storage device. An on-chip reliability controller coupled to one or more on-chip resources of the microprocessor chip, collects raw reliability information from the one or more on-chip resources of the microprocessor chip. The on-chip reliability controller analyzes the raw reliability information to identify selected reliability information for the one or more resources of the microprocessor chip. The on-chip reliability controller stores the selected reliability information in the on-chip non-volatile storage device. The on-chip non-volatile storage device stores the selected reliability information even in the event of an overall failure of the microprocessor chip in which the microprocessor chip loses power.

Abstract: Provided are a self-diagnosis system and a test circuit determination method that are capable of determining normality of a test circuit which diagnoses a test target circuit. A self-diagnosis system according to an aspect of the present invention includes a test circuit including first and second diagnosis controllers which determine normality of a test target circuit by using an execution result of a test pattern in the test target circuit; and a test circuit determination unit which determines normality of the test circuit by comparing a normality determination result of the test target circuit output from the first diagnosis controller with a normal determination result of the test target circuit output from the second diagnosis controller.

Abstract: A method performed by a primary server includes receiving integrity criteria and sending a health check request to a secondary server based on the received integrity criteria. The method also includes receiving integrity information from the secondary server and checking the integrity information against the integrity criteria. The method further includes initiating a non-compliance action if the integrity information does not comply with the integrity criteria.

Abstract: A system and method of employing a façade to intercept change action commands to be carried out on a target IT endpoint resource. The intercepted commands are compared to information on a corresponding change ticket and any differences, along with the information such as target history, are used to compute a risk assessment of the risk in allowing the intercepted change action commands to be executed. Where the risk exceeds a predetermined threshold, the intercepted change action commands may be modified or eventually aborted.

Abstract: The present invention relates to calibration of a computerized test system (20) for testing digital audio devices (30) through a data communication interface. The computerized test system comprises a sound card and a digital calibration generator (31) for calibrating at least a signal receipt channel (25) of the computerized test system (20).

Abstract: Disclosed are representative embodiments of methods, apparatus, and systems for partitioning-based Test Access Mechanisms (TAM). Test response data are captured by scan cells of a plurality scan chains in a circuit under test and are compared with test response data expected for a good CUT to generate check values. Based on the check values, partition pass/fail signals are generated by partitioning scheme generators. Each of the partitioning scheme generators is configured to generate one of the partition pass/fail signals for one of partitioning schemes. A partitioning scheme divides the scan cells into a set of non-overlapping partitions. Based on the partition pass/fail signals, a failure diagnosis process may be performed.

Abstract: Described herein is a method and apparatus to interface a processor with a heterogeneous dual in-line memory module (DIMM). The method comprises determining an identity of a DIMM having data lanes; mapping the data lanes based on the determining of the identity of the DIMM; training input-output (I/O) transceivers in response to the mapping of the data lanes; and transferring data to and from the DIMM after training the I/O transceivers.

Abstract: A method and apparatus of generating the soft value for a memory device is disclosed. Memory read-related parameters are set, and data are read out of the memory device according to the set parameters. The data reading is performed for pre-determined plural iterations, thereby obtaining the soft value according to the read-out data and the set parameters.

Abstract: A device for use in inspecting a CPU and a method thereof are provided. The device comprises a receiving interface and a processor. The receiving interface receives a first data stream from the CPU when the CPU executes a reference hardware inspection program in a first time interval, and receives a second data stream from the CPU when the CPU executes the reference hardware inspection program in a second time interval. The processor sets the first data stream as a good log, and sets the second data stream as an erroneous log. The processor compares the good log and the erroneous log to determine a segment of the erroneous log as an erroneous range, and determine a defect of the CPU according to the erroneous range.

Abstract: The determination of a reliability guideline of an electronic circuit having a nodal network of components including at least one reconvergence path between a correlation source and a sink, involves at the level of each component of the path, a computation of a conditional probability matrix whose conditioning is related to at least one node of the path situated upstream of the component.

Abstract: One embodiment of a system for analyzing reliability of a communication link comprises a link control component that controls the communication link, where the link control component couples to a processor and a diagnostic component. The diagnostic component is configured to determine whether transmission errors have occurred on the communication link exceeding or matching a first programmable threshold over a range of multiple periods of time that exceeds or matches a second programmable threshold.

Abstract: Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is accessible external to the IC, it is generally preferred to have selectivity on which Tap domain or Tap domains are accessed. Therefore Tap domain selection circuitry may be included in ICs and placed in the scan path along with the Tap domains. Ideally, the Tap domain selection circuitry should only be present in the scan path when it is necessary to modify which Tap domains are selected in the scan path. The present disclosure describes a novel method and apparatus which allows the Tap domain selection circuitry to be removed from the scan path after it has been used to select Tap domains and to be replaced back into the scan path when it is necessary to select different Tap domains.

Abstract: A mechanism for utilizing a virtual machine cloud for automated test system deployment is disclosed. A method of embodiments of the invention includes selecting a master image used to initialize one or more virtual machines (VMs), providing a list of repository definitions and test packages to the one or more VMs, and receiving test results from executing the test packages on a computer system of the VM defined by the master image, wherein the computer system includes an operating system and one or more software applications.

Abstract: A circuit operation verification system has: a computer; a programmable logic device in which a device under test is configured; and a test bench section configured to perform operation verification of the device under test. The test bench section has: a software section that is implemented by the computer executing software; and a hardware section configured in the programmable logic device together with the device under test. The hardware section has a hardware function that generates a test pattern and inputs the test pattern to the device under test to perform the operation verification. The hardware function is controllable by changing a control parameter, and the software section variably sets the control parameter.

Abstract: Disclosed are representative embodiments of methods, apparatus, and systems for power aware test applications involving deterministic clustering of test cubes with conflicts. Embodiments of the disclosed technology can be used to generate low toggling parent patterns to reduce power consumption during testing an integrated circuit. The power consumption may be further reduced by generating low toggling control patterns.

Abstract: Disclosed is a system for verifying a multimedia player. The system includes a multimedia player, a verification mechanism, a serial number generator, an audio and video data unit and a test mechanism. The multimedia player includes a communication interface and a storage unit. The verification mechanism includes a communication interface connected to the communication interface of the multimedia player. The serial number generator is connected to the communication interface of the verification mechanism. The audio and video data unit is connected to the communication interface of the verification mechanism. The test mechanism is connected to the communication interface of the multimedia player.

Abstract: The disclosure describes a novel method and apparatus for improving the operation of a TAP architecture in a device through the use of Command signal inputs to the TAP architecture. In response to a Command signal input, the TAP architecture can perform streamlined and uninterrupted Update, Capture and Shift operation cycles to a target circuit in the device or streamlined and uninterrupted capture and shift operation cycles to a target circuit in the device. The Command signals can be input to the TAP architecture via the devices dedicated TMS or TDI inputs or via a separate CMD input to the device.

Abstract: Disclosed is a control method of a non-volatile semiconductor device including cells, wherein a stress for rewriting information is applied to each of the cells, and each cell has a first time period as a period of time until a characteristic of the cell is stabilized to expectation value information after the stress for rewriting information is applied, a plurality of first sequences, in each of which writing is performed to a plurality of the cells continuously in time series, and a plurality of second sequences, in each of which verification of a plurality of the cells is performed continuously in time series, after the writing performed continuous in time series.

Abstract: A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).

Abstract: A Propagation Test instruction, a Decay Test instruction and a Cycle Test instruction provide testing of DC and AC interconnect circuits between circuits including JTAG boundary scan cells. A few additions to the Test Access Port circuitry, including gating producing a Capture Test Strobe (CTS) signal, and the boundary scan cells are required to implement the additional instructions. The instructions are extensions of the conventional JTAG operating structure.

Abstract: Provided are a generation device and the like for generating a new vector whose volume can be reduced rapidly when an output pattern derived from a decompressor of a logic circuit under test includes an unspecified bit in relation to the logic circuit under test. The output pattern includes unspecified bits. In step SS1, classification unit classifies the unspecified bits and determines if an unspecified bit is an implied bit or not. The implied bit is an unspecified bit if its value is a logic value determined as logic value 0 or 1 relating to logic bits in the initial vector and according to a predetermined condition (such as compressibility) among bits in the initial vector derived from the upstream logic circuit 1. In step SS1, the unspecified bits which are not implied bits are classified as free bits. The classification unit classifies free bit sets in step SS2, and further classifies free bits to identify compatible free bit sets.

Abstract: A scannable pulse dynamic logic gate may include an evaluation network that evaluates dynamic inputs in response to assertion of an evaluate pulse. The evaluate pulse may be generated from a clock signal such that it is shorter in duration than the clock signal. During a normal mode of operation, when the evaluate pulse is asserted, the evaluation network may discharge a dynamic node depending on the state of the dynamic inputs. The dynamic node may then drive output device(s). When the evaluate pulse is deasserted, the dynamic node may be precharged. The gate may also include scan input devices, which, during a scan mode of operation, may load scan input data onto the output node in response to assertion of a scan master clock. A storage element of the gate may receive and capture a value of the output node in response to assertion of a slave scan clock.

Abstract: The disclosure relates to a process for making an electric testing of electronic devices DUT, of the type comprising the steps of: connecting at least one electronic device DUT to an automatic testing apparatus or ATE apparatus suitable for making the testing of digital circuits; sending, through said ATE apparatus, control signals for the electric testing to said electronic device DUT. Advantageously, the process also comprises the steps of: making the electric testing of said electronic device DUT through at least one reconfigurable digital interface RDI connected to said ATE apparatus through a dedicated digital communication channel and comprising a limited number of communication or connection lines strictly appointed to the exchange of the testing information; and sending from said electronic device DUT to said ATE apparatus response messages, if any, containing measures, failure information and data in response to said control signals and through said digital communication channel.

Abstract: Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.

Abstract: Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed.

Abstract: Computer and internet applications are commonly hosted by a large number of servers, such as a data warehouse. One concern when hosting applications is execution reliability of the applications. Unfortunately, it may be the applications themselves that provide the point of failure (e.g., an executing service creates a memory leak that causes a server to fail). Because servers are often replicated, a failure of a single executing service may become a single point of failure for every server. Accordingly, one or more systems and techniques for balancing server loads are disclosed herein. A load balancer may be configured to delegate the execution of a service amongst a plurality of servers such that no server executes all services and no service executes on all servers. The distribution of service execution amongst the plurality of servers provides service execution diversity across servers that otherwise may be configured identically with services.

Abstract: An abnormality detection apparatus includes: a performance information obtaining unit to obtain load information of a computer; a response time obtaining unit to obtain a response time of the computer; a first abnormality determination unit to determine whether the computer is in abnormal operation state based on the load information; a second abnormality determination unit to determine whether the computer is in abnormal operation state based on the response time, when the first abnormality determination unit determines that the computer is in abnormal operation state; and an abnormality notification unit to perform notification of an abnormality, when the second abnormality determination unit determines that the computer is in abnormal operation state.

Abstract: Various apparatuses, methods and systems for dual JTAG controllers with shared pins disclosed herein. For example, some embodiments provide a boundary scan apparatus having a first boundary scan circuit with a first plurality of control inputs, a second boundary scan circuit with a second plurality of control inputs, and a plurality of boundary scan control signals connected to the first plurality of control inputs on the first boundary scan circuit and to the second plurality of control inputs on the second boundary scan circuit. At least two of the plurality of boundary scan control signals are connected between the first boundary scan circuit and the second boundary scan circuit in a crossover fashion.

Abstract: A semiconductor integrated circuit, includes a control flip-flop for inputting a scan control signal and a scan path chain formed of a plurality of scan storage elements serially connected to each other. The scan path chain performs a shift operation as a first mode when an output of the control flip-flop is a first status value, and performs a normal operation as a second mode when an output of the control flip-flop is a second status value. When the scan control signal is switched from the first status value to the second status value, the control flip-flop outputs the second status value to the plurality of scan storage elements in synchronization with a first clock pulse, after the switching, of a clock provided to the plurality of scan storage elements. When the scan control signal is switched from the second status value to the first status value, the control flip-flop outputs the first status value to the plurality of scan storage elements at a timing of the scan control signal switching.

Abstract: The present invention certifies control modules of engineered safety feature instruments for a power plant automatically. The control modules can be tested before storing or operating. The test is done with enhanced testing speed and saved cost. Thus, safety of the control modules is confirmed.

Abstract: Methods and apparatus are provided for soft data generation for memory devices based on a performance factor adjustment. At least one soft data value is generated for a memory device, by obtaining at least one read value; and generating the soft data value based on the obtained at least one read value and an adjustment based on one or more performance factors of the memory device. The read values may comprise, for example, data bits, voltage levels, current levels or resistance levels. The read values may be soft data or hard data. The possible performance factors include endurance, number of read cycles, retention time, temperature, process corner, inter-cell interference impact, location within the memory array and a pattern of aggressor cells. One or more pattern-dependent performance factors and/pr location-specific performance factors may also be considered.

Abstract: A hardened store-in cache system includes a store-in cache having lines of a first linesize stored with checkbits, wherein the checkbits include byte-parity bits, and an ancillary store-only cache (ASOC) that holds a copy of most recently stored-to lines of the store-in cache. The ASOC includes fewer lines than the store-in cache, each line of the ASOC having the first linesize stored with the checkbits.

Abstract: A device test architecture and a reduced device test interface are provided to enable efficient testing of embedded cores and other circuits within devices. The reduced device test interface is achieved using a double data rate (DDR) signaling technique between the tester and the device. The DDR test interface allows the tester to interface to test circuits within the device, such as IEEE 1500 and/or IEEE 1149.1 test circuits, to provide high test data bandwidth to the test circuits using a minimum of test interface signals. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester.

Abstract: An on-chip functional debugger includes one or more functional blocks each providing one or more functional outputs. A hierarchical selection tree is formed by one or more selectors having the output of one of the selectors as a final output and individual selector inputs coupled either to a functional output from the functional blocks or to an output of another selector. A selection signal coupled to the select input of each of the selectors to enable a selected one of its output. An output node coupled to the final output. A method of providing on-chip functional debugging is also provided. A desired functional output from one or more available functional outputs is selected and then the selected functional output is coupled to an output node.

Abstract: A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known art. The changes between the known art Scan-BIST architecture and the low power Scan-BIST architecture involve modification of the known scan path into scan path 502, to insert scan paths A 506, B 508 and C 510, and the insertion of an adaptor circuit 504 in the control path 114 between controller 110 and scan path 502.

Abstract: A test system for performing tests on devices under test (DUTs) includes a storage device storing test data for performing the tests on the DUTs, a shared processor for generating the test data, storing the test data in the storage device and generating a test control signal including one or more test instructions for executing the tests, and, for each DUT, a dedicated processor configured to receive a test control signal from the shared processor, and in response to the test control signal, transfer the test data for one of the test instructions to the DUT to execute that test instruction and verify the completion of that test instruction.

Abstract: A test framework architecture that separates the generation of random test actions from test execution and provides a way to record the state of the system under test at user controlled intervals. This saved state is used to bring the test system to the last known state before failure and then execute the much smaller set of actions to the point of failure, thus requiring shorter run time. Given the same time constraints, this enables the execution of this smaller set more frequently, providing better bug fix verification and shorter reproduction time.

Abstract: A test method for an ASIC uses an embedded processor in the ASIC to execute test routines from an embedded memory or an external memory. During ASIC production, the test routines can comprehensively test of the blocks of the ASIC without a complicated test pattern from test equipment. The test routines can also perform power-up tests in systems or end products containing the ASIC. Test selection, activation, and result output can be implement using a few terminals of the ASIC.

Abstract: System and method for generating test information for a physical circuit. A virtual circuit may be generated. First user input specifying one or more test conditions and/or instrument settings for the virtual circuit may be received. In response to the first user input, first test information may be generated. The first test information may be configured for use in performing one or more virtual tests on the virtual circuit. Second user input requesting that second test information be generated based on the first test information may be received. The second test information may be automatically generated based on the first test information in response to the second user input, without user input specifying the one or more test conditions and/or instrument settings. The second test information may be configured for use in performing one or more physical tests on a physical circuit corresponding to the virtual circuit.

Abstract: The present invention relates to pattern recognition and classification, more particularly, to a system and method for meta-recognition which can to predict success/failure for a variety of different recognition and classification applications. In the present invention, we define a new approach based on statistical extreme value theory and show its theoretical basis for predicting success/failure based on recognition or similarity scores. By fitting the tails of similarity or distance scores to an extreme value distribution, we are able to build a predictor that significantly outperforms random chance. The proposed system is effective for a variety of different recognition applications, including, but not limited to, face recognition, fingerprint recognition, object categorization and recognition, and content-based image retrieval system.

Abstract: The present invention provides a MIMO transmitter and a MIMO receiver, used in SC-FDMA system, which make interchanging for multiple paths of modulated symbol sequences in order to acquire diversity gain while ensure PAPR of single antenna. MIMO transmitter interchanges partial symbols of at least one error-correction codeword of at least one of the multipath modulated symbol sequences and partial symbols of at least one error-correction codeword of at least one of the other of the multipath modulated symbol sequences so as to obtain interchanged multipath modulated symbol sequences; MIMO receiver executes inverse-interchanging which is inverse to the interchanging in a MIMO transmitter for multipath interchanged signals received from multiple transmitting antennas. The present invention could reduce the BLER of the entire SC-FDMA system, and obtain diversity gain while ensure PAPR of single antenna.

Abstract: An apparatus comprising an initiator circuit and a target circuit. The initiator circuit may be configured to (i) communicate with a network through a first interface and (ii) generate testing sequences to be sent to the network. The target circuit may be configured to (i) receive the testing sequences from the network through a second network interface and (ii) respond to the testing sequences.

Abstract: Systems and methods for item-level restoration from and verification of an image level backup without fully extracting it. The method receives backup parameters and selection of an image level backup to restore or verify and initializes virtual storage. The method attaches the virtual storage to a hypervisor to launch a virtual machine (VM) to test and restore data objects. The method stores VM virtual disk data changes resulting from restoration and verification in a changes storage. The method optionally reconfigures VMs to use an isolated network. The method optionally uses a routing appliance to provide access to VMs running in the isolated network from a production network. The method determines if the VM operating system (OS) is able to start using restored copies of selected data objects and tests applications associated with selected data objects. The method displays restoration and test results in an interface and automatically delivers the results.

Abstract: A continuous parallel Viterbi decoder comprises input means for computing Trellis paths from an input bitstream encoded with a convolutional code; output means for backtracking the Trellis paths to generate an output signal; a shared memory for storing said Trellis paths; and coordination means for coordinating simultaneous read/write operations from and to the shared memory. (FIG.

Abstract: A network error detecting method checks if a network connection device has an Internet protocol (IP) address, if domain name mapping of web pages is correct, and if data communication between a web browser and a web server is correct. Accordingly, the network connection device informs the web browser of an IP address error, a domain name mapping error, or a data communication error. The web browser displays the network errors to users when the network errors are detected.

Abstract: A SRAM (Static Random Access Memory) macro test flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a master latch circuit and a slave latch circuit. The master latch circuit includes a master feed-back circuit including a master storage node and a master feed-forward circuit. The slave latch circuit includes a slave feed-back circuit including a slave storage node and a slave feed-forward circuit driven from the master latch. The scan control circuit includes a scan slave feed-forward circuit, a scan latch circuit, and a scan driver circuit driven by the scan feed-back circuit. The scan latch circuit includes a scan feed-back circuit comprising a scan storage node and a scan feed-forward circuit driven from the slave latch. The output buffer circuit includes a master driver driven from master latch circuit and a slave driver driven from slave latch circuit.