Abstract: A computer apparatus includes a first processor, a second processor, and a main memory. The computer apparatus further includes a memory-diagnostic unit, a diagnostic-program loading unit, and a defective-function identifying unit. The memory-diagnostic unit causes the second processor to execute a memory-diagnostic program to diagnose the main memory, and identifies a defective area in the main memory. The diagnostic-program loading unit loads a processor-diagnostic program for diagnosing a plurality of functions of the first processor into an area of the main memory other than the defective area identified by the memory-diagnostic unit. The defective-function identifying unit causes the second processor to execute the processor-diagnostic program loaded by the diagnostic-program loading unit, and identifies a defective function that is disabled from the functions of the first processor.

Abstract: A data processing method for loading data from a non volatile memory to a memory is disclosed. A template data and a data block corresponding thereto in the non volatile memory are loaded to a buffer. A reference value of the template data and a corresponding reference value of the data block are compared to determine whether the reference value and the corresponding reference value are matched. If not, a modification algorithm is performed to adjust the data format of the loaded data block based on the reference value of the template data. Then, system related information is generated and stored to the memory according to data in the template data and the adjusted data block in the buffer.

Abstract: To reduce pseudo errors. A stationary signal is propagated through the circuit to be checked. A combination is extracted in which different asynchronous transfers occur between a transmitting side register and a receiving side register. From the extracted combination of asynchronous transfers, a circuit to be checked is extracted, and a synchronization circuit of a plurality of signals is excluded from the circuit to be checked. A stationary signal is propagated through the circuit to be checked, for each combination among all combinations of logic values “1” and “0” of the stationary signal. It is checked whether or not there exists one asynchronous transmitting side register to which signal change can logically reach, in the combination of logic values of the stationary signal propagated. Based on the result, it is determined whether or not the circuit is appropriate as a synchronization circuit for a single-signal transfer, thereby reducing pseudo errors.

Abstract: A memory device is provided. The memory device includes a plurality of memory chips coupled in series, and a register serially coupled to the memory chips. The register includes an integrated delay-locked loop. The memory device may be included in a processing system. Moreover, a method for improving timing budgets in a registered dual in-line memory module (RDIMM) may be implemented using the memory device having a register with an integrated delay-locked loop.

Abstract: A contents delivery system and method, and a GSLB switch thereof are provided. When a client requests a web server to provide a page and embedded objects, the web server embeds the URL representing the position in which the page and embedded objects are stored in an HTTP 302 redirection message and transmits the HTTP 302 redirection message including the URL to the client. A GSLB switch corresponding to the URL transmits the IP address of a specific host server selected from at least one host server storing the page and the embedded objects to the client. Accordingly, load of the web server decreases and flexibility in change of a CDN solution is secured.

Abstract: Disclosed are a method, system and computer program product for determining hardware diagnostics during initial program loading (IPL). A space is allocated for a diagnostics hardware table storing hardware identifications corresponding to hardware to be tested. A hardware monitor function detects new and/or defective hardware. Hardware can be manually selected. A runtime diagnostics detects defective hardware. The hardware identifications corresponding to the new, failing, and/or selected hardware are added to the diagnostics hardware table. The hardware identification to be tested is acquired during the building of a system Hardware Objects Model (HOM). A diagnostics flag is set within HOM according to the diagnostics hardware table. Diagnostics are performed per HOM diagnostics flag indication. The diagnostics table is cleared, and the operating system is run. At system runtime, diagnostics code monitors for runtime error.

Abstract: In a random error signal generator, an M-sequence generation circuit outputs, in parallel, pieces of bit data stored in each register, a first generation circuit sequentially outputs first reference values C which are changed by a predetermined value in response to clocks, a second generation circuit outputs a second reference value D which is shifted from the first reference value C by a range value E which is determined depending on an error rate p. A comparison and determination unit outputs random error signals to be error bits when a numeric value A of the bit data output exists between the first and second reference values C, D. The random error signal has the error rate p, the number of times of error occurrences follows Poisson distribution, and a distribution of adjacent error occurrence intervals follows a geometric distribution.

Abstract: A method for dynamically broadcasting configuration information to controllers connected in a scan topology in a target system is provided in which a selection event followed by the configuration information is received from a signal line at each of the controllers, wherein the plurality of controllers are connected in parallel to the signal line and the configuration information is stored within each controller that matches a selection criteria following the selection event when the selection event initiates a selection sequence.

Abstract: A system and method for recovering from a single logical path failure. More specifically, although a host has not grouped its logical paths, the host knows which logical paths it has available. When a host detects a logical path failure, the host enters a path discovery mode of operation. If the host continues to detect a logical path failure while operating in the logical path discovery mode of operation, the host removes the logical path from a logical path mask, and the host does not use the removed logical path again. In the case of ungrouped logical paths, the host aborts its process because it does not have more paths available to continue its process. Additionally, in certain embodiments, a pseudo path group for ungrouped logical paths is created.

Abstract: Embodiments of the invention provide techniques for determining the correctness of similar job plan segments in a stream processing application. In one embodiment, a job manager may be configured to identify similar job plan segments based on data formats, functionality, and surrounding processing elements. The job manager plan may be further configured to determine whether the similar segments provide inconsistent results, and if so, to determine which of the inconsistent similar segments is invalid. The job manager may identify an invalid processing element included in the invalid segment. The job manager may also perform corrective actions to address the invalid processing element.

Abstract: A method and system for automated disaster recovery in an information technology computing system including computing resources, is provided. One implementation involves logging system events in a journaling log file, filtering the events of the log file for each resource and storing the filtered log file, reading the filtered log file, and restarting from a backup file by applying the filtered events to a backup file for recovery.

Abstract: A memory test circuit includes a counter circuit that outputs a set signal that is set to the first set value or the second set value alternately in a cycle of the clock signal, an OR circuit that calculates a logical sum of the set signal and the input signal each time when the set signal is output from the counter circuit and outputs a control signal indicating the logical sum of the set signal and the input signal, and a test pattern generation circuit that generates the test pattern for causing the memory to operate in each first cycle if a set value of the control signal is the first set value, or generates the test pattern for causing the memory to operate in each second cycle if the set value of the control signal is the second set value.

Abstract: A device is disclosed for testing the function of a display port. The device includes a display port transmitting part, a field programmable gate array, and a memory. The display port transmitting part transmits connecting signals to a display port timing controller mounted on a display panel. The field programmable gate array applies a test signal to the display port timing controller, and controls the connecting signals applied from the display port transmitting part to the display port timing controller. The memory has software that determines acceptance or rejection of the display port function based on data output from the display port timing controller in response to the connecting signals or the test signal.

Abstract: A network device for use in a communication system having a technical support center operated by a technical support staff, the technical support center being in communication with the network device through a packet switching network. The network device includes one or more hardware subsystems, one or more software subsystems and means for monitoring the status of the hardware and software subsystems so that when a problem occurs with respect to one or more of the hardware and software subsystems of the network device, the network device for transmitting a first message to the technical support center to notify the technical support center of the problem, wherein the technical support staff is able to diagnose the problem without interruption to the operation of the network device.

Abstract: A processing device, system, method, and design structure for providing a microprocessor interface with dynamic segment sparing and repair. The processing device includes drive-side switching logic including driver multiplexers to select driver data for transmitting on link segments of a bus, and receive-side switching logic including receiver multiplexers to select received data from the link segments of the bus. The bus includes multiple data link segments, a clock link segment, and at least two spare link segments selectable by the drive-side switching logic and the receive-side switching logic to replace one or more of the data link segments and the clock link segment.

Abstract: Systems, methods, and other embodiments associated with test execution of user SQL in server code are described. One example method includes producing a reproduced execution environment that reproduces a portion of an execution environment in which a user SQL runs. The example method may also include running the user SQL in the reproduced execution environment and capturing a statistic associated with performance of the user SQL while the user SQL runs in the reproduced execution environment. The method may conclude by storing, displaying, and/or providing a signal concerning the statistic.

Abstract: Provided is a test apparatus having a bad block memory for storing a plurality of pieces of fail information in association with blocks of a memory under test, each piece of fail information indicating whether there is a defect in the associated block. The test apparatus writes a test data sequence to a page under test of the memory under test, reads the test data sequence written to the page under test, and compares the read data sequence to the written data sequence. The test apparatus includes an allocation register that stores allocation information for setting which of the plurality of fail conditions for judging whether there is a defect in the page under test are allocated to the plurality of pieces of fail information.

Abstract: A fault prediction method predicts a plurality of faults in a target device, and includes the steps of collecting internal information of the target device output from the target device, generating one or more criteria for defining a deviation from a normal state based on the collected internal information of the target device, incorporating the one or more criteria into a device state discriminator, identifying a deviation from a normal state in the target device according to the one or more criteria using the device state discriminator, and outputting a fault prediction as a result of the identifying step to a user. One or more of the steps are performed by a processor.

Abstract: An apparatus for testing a communication circuit includes a detection module and a capture module. The detection module provides an enable signal in response to receiving at least one predetermined plurality of data from a communication device under test. The capture module captures at least one other predetermined plurality of data in response to the enable signal.

Abstract: A test and analysis system may use Xpath or other text based analysis descriptors to analyze test results that may be presented in XML. The text based analysis descriptors may be installed and used on an analysis system without exposing the analysis system to security vulnerabilities, and such descriptors may be frequently updated and distributed. A server device may have a test manager that may coordinate tests performed on other devices connected through a local area network, and may gather and store the test results for analysis. In some cases, the test results may be converted to XML for analysis.

Abstract: Provided are a method, apparatus, and computer program product for testing a virtualised storage system. Data defining one or more configuration features of the virtualised storage system is received. Also received is a set of one or more predetermined rules defining interpretation of the disk exercising commands, the interpretation being dependent on one or more of the configuration features. A first disk exercising command is received. The first disk exercising command is interpreted in accordance with one of the predetermined rules to produce a second disk exercising command. The second disk exercising command is sent to the virtualised storage system.

Abstract: A method and device for data processing in an integrated circuit having cells, the cells adapted for executing programs. A first program is run. In response to a waiting condition during which no program execution is able to take place, saving data from the cells to a memory. A second program, e.g., a test program, is run after the data is saved. The saved data is then reloaded into the cells after running the second program.

Abstract: Embodiments of the invention provide an interrupt handler configured to distinguish between critical and non-critical unrecoverable memory errors, yielding different actions for each. Doing so may allow a system to recover from certain memory errors without having to terminate a running process. In addition, when an operating system critical task experiences an unrecoverable error, such a task may be acting on behalf of a non-critical process (e.g., when swapping out a virtual memory page). When this occurs, an interrupt handler may respond to a memory error with the same response that would result had the process itself performed the memory operation. Further, firmware may be configured to perform diagnostics to identify potential memory errors and alert the operating system before a memory region state change occurs, such that the memory error would become critical.

Abstract: A method, system and computer program product for logging and identifying microcode errors in a computing environment is provided. Each of a plurality of errors in the microcode is logged using a plurality of error logging commands. Each of the plurality of errors is indexed to generate a plurality of indexed errors. A plurality of unique keys is associated to each of the plurality of indexed errors. A master index of the plurality of unique keys is created.

Abstract: Systems and methods to modify a set of connection records are described. A determination is made that an application failed to access a first database via a connection record, where the connection record includes data to access the first database. A determination is made that a second database is accessible, where the second database is a failover database to the first database. A set of connection records associated with the first database is modified to enable access to the second database.

Abstract: The present invention can include an automated solution for incorporating diagnostic data within an image of a screen capture image. When a screen capture event is detected, a screen capture image can be generated. The software applications contained within the screen capture image can be identified. Diagnostic data pertaining to the identified software applications can be automatically collected and incorporated into the screen capture image file.

Abstract: The present invention provides the ability to synchronize or rendezvous multiple virtual users across multiple distributed devices in a load testing tool with reduced network message exchange between devices.

Abstract: A verification support device that supports verification of a changed state by using changed state data and relating data. The verification support device includes a state with an abnormal condition generating unit adds the abnormal condition to the changed state thereby generating a changes state with an abnormal condition. The verification device also includes an abnormal condition inspection unit that inspects whether the abnormal data may reach the changed state based on the generated changed state with the abnormal condition and the relating data.

Abstract: A system for processing errors in a processor comprising, a first register having a unique identifier operative to store a first error data, a processor operative to retrieve the first error data from the first register, associate the first error data with the unique identifier, and generate a first uniform error packet including the first error data and the unique identifier and a storage medium operative to store the first uniform error packet.

Abstract: Diagnosing communications between computer systems includes sending a message from a sending node to a receiving node. The receiving node detects an error in the receiving node receiving the message and captures the data regarding the error on the receiving. A diagnostic log request is sent from the receiving node to the sending node, the diagnostic log request including a request for the sending node to log information. The sending node diagnoses the communications error in response to the diagnostic log response.

Abstract: A method, information system, and computer readable storage medium verify predefined connectivity for I/O devices. Current predefined logical connection data and actual physical connection data is gathered. The predefined logical connection data and the actual physical connection data are formatted into a plurality of sortable tables. At least a portion of the predefined logical connection data is formatted into a predefined channels table and at least a portion of the actual physical connection data is formatted into a node information table. The portion of the predefined logical connection data is compared with the portion of the actual physical connection data. The portion of the predefined logical connection data is determined to substantially match/not match the portion of the actual physical connection data. At least one predefined logical connection associated with the predefined logical connection data that fails to substantially match the actual physical connection data is displayed to a user.

Abstract: A test adaptor board connects to a personal computer (PC) motherboard that tests a memory module in a test socket. A standard memory module socket is removed from a target DRAM module slot on the component side and the test adaptor board connects to the target DRAM module slot on the reverse (solder) side of the motherboard. The target DRAM module slot is a middle slot, such as the second or third of four DRAM module slots. The first and fourth DRAM module slots are populated with known good memory modules storing the BIOS at a high address and an operating system image and a test program at a low address. The test program accesses a memory module in the test socket to locate defects. The motherboard does not crash since the BIOS, OS image, and test program are not stored in the memory module under test.

Abstract: A primary I/O adapter and a redundant I/O adapter of a data processing system are assigned to support access to a system resource. While the primary I/O adapter is in service and the redundant I/O adapter is not in service in providing access to the system resource, a fail over command is issued to remove the primary I/O adapter from service and place the redundant I/O adapter in service in supporting access to the system resource. While the redundant I/O adapter is in service and the primary I/O adapter is not in service in providing access to the system resource, diagnostic testing on the primary I/O adapter is performed. In response to the diagnostic testing revealing no fault in the primary I/O adapter, a fail back command is issued to restore the primary I/O adapter to service and to remove the redundant I/O adapter from service.

Abstract: A host fabric interface (HFI) enables debugging of global shared memory (GSM) operations received at a local node from a network fabric. The local node has a memory management unit (MMU), which provides an effective address to real address (EA-to-RA) translation table that is utilized by the HFI to evaluate when EAs of GSM operations/data from a received GSM packet is memory-mapped to RAs of the local memory. The HFI retrieves the EA associated with a GSM operation/data within a received GSM packet. The HFI forwards the EA to the MMU, which determines when the EA is mapped to RAs within the local memory for the local task. The HFI processing logic enables processing of the GSM packet only when the EA of the GSM operation/data within the GSM packet is an EA that has a local RA translation. Non-matching EAs result in an error condition that requires debugging.

Abstract: Full text index-ability, indexing, and container extraction status of files in a collection repository is displayed to a user in connection with content management in EDiscovery. Thus, the user knows which files failed to index and explode and which files that are not indexable. The user also knows which files have not been indexed yet, so they are not omitted from an analysis. Accordingly, users can start working on collected files without waiting for the maximum possible indexing period. Further, users can start working immediately on the collected content, thus avoiding slowing down the work during frequent updates to the content repository. Only indexing and extraction status information that is relevant to the search query is displayed, thus minimizing the time needed to analyze the files that are not indexed or not exploded manually.

Abstract: A method and apparatus to improve memory initialization in a memory of a computer system. Memory units in the memory comprise a plurality of ranks, each rank having a unique rank select. A parity generator outputs a parity bit corresponding to whether an encoded rank select has an even or odd number of “1”s. The parity bit is used by an Error Checking and Correcting (ECC) unit that generates ECC bits that are stored in a rank having an active rank select. During a first interval in a memory initialization period, ranks having an even number of “1”s in their encoded rank select are initialized in parallel. During a second interval in the memory initialization period, ranks having an odd number of “1”s in their encoded rank select are initialized in parallel.

Abstract: This disclosure describes software for supporting an application. In one aspect, software for supporting a business application receives error and dynamic context information from a remote business application in response to an incident. The dynamic context information at least partially identifies one or more business objects (BOs) associated with the incident. The software is further operable to clone at least one of the BOs associated with the incident. The software can then start a transaction simulating the incident. Conversely, the business application (or other supported software) can transmit error and dynamic context information to support software related to an incident within having a particular execution environment. In response to an automated request from the support software executing a simulated transaction simulating the incident, the supported software communicates a clone of one of the associated BOs to the support software.

Abstract: In a magnetic data processing device, an input part sequentially receives magnetic data output from a magnetic sensor. A storage part stores a plurality of the magnetic data as a data set of statistical population. An index derivation part derives a distribution index of the data set of the statistical population. A reliability determination part determines whether or not reliability of the data set of the statistical population is acceptable based on the distribution index and a decision criterion. A decision criterion setting part increases strictness of the decision criterion when the reliability determination part determines that the reliability of the data set of the statistical population is acceptable, and decreases the strictness of the decision criterion when the reliability determination part determines that the reliability of the data set of the statistical population is unacceptable.

Abstract: Fault injection in dynamic random access memory (‘DRAM’) modules for performing built-in self-tests (‘BISTs’) including establishing, in the mode registers of the DRAM modules by the memory controller through the shared address bus, an injection of a fault into one or more signal lines of a DRAM module, the fault characterized by a fault type; writing data by the memory controller through a data bus to the DRAM modules, the data identifying a particular DRAM module; and responsive to receiving the data, injecting, by the particular DRAM module, the fault characterized by the fault type into the one or more signal lines of the particular DRAM module.

Abstract: A storage management apparatus manages a plurality of storage apparatuses connected to each other over a network in a storage system that distributes data among the storage apparatuses and stores the data therein. The storage management apparatus has a patrol process executing unit configured to execute a patrol process to confirm whether a storage area of each storage apparatus operates normally and a patrol flow controlling unit configured to control a patrol flow indicating the speed of the patrol process executed by the patrol process executing unit.

Abstract: The present invention relates to providing monitoring agents in various elements of a switched digital media network. The monitoring agents may be placed in one or more of the following types of devices: customer premise equipment, access nodes, switching offices, hub offices, head end equipment, and the like. The monitoring agents may be located in any number of the types of devices at the same or different hierarchical levels in the switched digital media network. In different embodiments, the monitoring agents may be employed at different locations and provide various functionality, which may include capturing segments of streaming media, communicating with each other, providing and processing fault alarms, determining the location of fault alarms, or the like.

Abstract: Techniques for generating a system model for use by and availability management framework (AMF) are described. Inputs are received, processed and mapped into outputs which are further processed into a configuration file in an Information Model Management (IMM) Service external Markup Language (XML) format which can be used as a system model by an AMF.

Abstract: A virtual machine monitor (VMM) in a data processing system handles errors involving virtual machines (VMs) in the processing system. For instance, an error manager in the VMM may detect an uncorrectable error in involving a component associated with a first VM in the processing system. In response to detection of that error, the error manager may terminate the first VM, while allowing a second VM in the processing system to continue operating. In one embodiment, the error manager automatically determines which VM is affected by the uncorrectable error, in response to detecting the uncorrectable error. The error manager may also automatically spawn a new VM to replace the first VM, if the processing system has sufficient resources to support the new VM. Other embodiments are described and claimed.

Abstract: A data processing apparatus is provided with packing circuitry 130 arranged to receive said source data elements from said trace data receiver and applies a packing protocol to said source data elements to pack data of source data elements of a source trace stream into a packed trace data stream for supply to trace accepting circuitry in a format comprising acceptance data elements. The acceptance data elements have a bit-length that is not a factor of the source data element bit-length. In some arrangements the source data elements are non byte-sized data elements. In alternative arrangements, the packing circuitry packs a first positive integer number of source data elements into a data chunk comprising a second, different positive integer number of acceptance data elements.

Abstract: Embodiments of the invention provide techniques for troubleshooting of computer systems using a fault tree analysis. In one embodiment, data parameters describing a status of a system may be monitored to determine the existence of a fault. In the event of a fault, fault tree analysis metadata may be evaluated to attempt to determine a root cause of the fault. If a root cause can be automatically determined, it may be presented to a user in a troubleshooting console, or may be used to trigger an automated corrective action. Alternatively, if a root cause cannot be automatically determined, the user may be presented with additional fault tree analysis metadata and any relevant data parameters in the troubleshooting console, so that the user may determine the root cause of the fault event.

Abstract: There is provided a distributed system having a plurality of nodes connected by a network. Each of the nodes includes: a common-parameter-value determining unit for determining a common-parameter-value from values of a parameter (each value being possessed by a corresponding one of the nodes); a common-operation execution unit for executing a common-operation using, as its input, a value of the parameter or the common-parameter-value; a send/receive unit for exchanging, via the network, the parameter values used for the determination of the common-parameter-value and the results of the common-operation execution with the other nodes; and a fault identification unit that compares the common-operation execution results collected from all the nodes and determines that an error occurs if not all the results are the same.

Abstract: A method for determining a fault tolerance of an erasure code comprises deriving base erasure patterns from a generator matrix of an erasure code, determining which of the base erasure patterns are adjacent to one another and XORing the adjacent base erasure patterns with one another to produce child erasure patterns of the erasure code. The method further comprises combining the base erasure patterns and the child erasure patterns to form a minimal erasures list (MEL) for the erasure code, whereby the MEL corresponds to the fault tolerance of the erasure code. Also provided are methods for communicating and storing data by using the fault tolerance of erasure codes.

Abstract: The use of operational configuration parameters to predict digital system failures is described herein. At least some illustrative embodiments include a method that includes initializing a digital system (the initializing comprising determining an operational configuration of at least part of the digital system), saving the operational configuration to a database stored on the digital system, reading the operational configuration from the database and comparing the operational configuration to a reference configuration, and identifying the digital system as being at risk of a future failure if at least one parameter of the operational configuration differs from the at least one same parameter of the reference configuration by more than a tolerance value.

Abstract: An apparatus, system, and method are disclosed for determining the reliability of an estimate such as particulate accumulation on a diesel particulate filter, weighing the estimate according to a function of its reliability, weighing a prediction of particulate accumulation on the filter according to a function of the estimate's reliability, and combining the weighted estimate and weighted prediction to determine a combined particulate load estimate. The degree of reliability can be expressed as a trust factor, and a function of the trust factor can be used in a low-pass filter of the estimate. The trust factor value depends on filter air flow and particulate distribution in one embodiment. Regeneration of the particulate filter may be initiated depending on the value of the combined particulate load estimate.

Abstract: A serial advanced technology attachment (SATA) device is provided. The SATA device includes a digital block and an analog black. The digital block is configured to generate and output an out-of-band (OOB) control signal. The analog block is configured to receive the OOB control signal, which has been output from the digital block, to receive the OOB control signal again after outputting it, and then output the OOB control signal to the digital block.