Fullerenes (i.e., Graphene-based Structures, Such As Nanohorns, Nanococoons, Nanoscrolls, Etc.) Or Fullerene-like Structures (e.g., Ws2 Or Mos2 Chalcogenide Nanotubes, Planar C3n4, Etc.) Patents (Class 977/734)
  • Patent number: 8828256
    Abstract: A method for making a carbon nanotube film includes the steps of providing an array of carbon nanotubes, treating the array of carbon nanotubes by plasma, and pulling out a carbon nanotube film from the array of carbon nanotubes treated by the plasma.
    Type: Grant
    Filed: January 8, 2009
    Date of Patent: September 9, 2014
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Chen Feng, Kai Liu, Yong-Chao Zhai, Kai-Li Jiang, Shou-Shan Fan
  • Patent number: 8823044
    Abstract: A light emitting diode includes a substrate, graphene layer, a first semiconductor layer, an active layer, a second semiconductor layer, a first electrode and a second electrode. The first semiconductor layer is on the epitaxial growth layer of the substrate. The active layer is between the first semiconductor layer and the second semiconductor layer. The first electrode is electrically connected with the second semiconductor layer and the second electrode electrically is connected with the second part of the carbon nanotube layer. The graphene layer is located on at least one of the first semiconductor layer and the second semiconductor layer.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: September 2, 2014
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Yang Wei, Shou-Shan Fan
  • Patent number: 8823045
    Abstract: A light emitting diode includes a graphene layer, a first semiconductor layer, an active layer, a second semiconductor layer, a first electrode and a second electrode. The first semiconductor layer, the active layer, and the second semiconductor layer are stacked with each other in sequence. The first electrode is located on and electrically connected with the second semiconductor layer. The second electrode is located on and electrically connected with the first semiconductor layer. The graphene layer is located on at least one of the first semiconductor layer and the second semiconductor layer.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: September 2, 2014
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Yang Wei, Shou-Shan Fan
  • Publication number: 20140241974
    Abstract: This carbon nanofiber is produced by a vapor phase reaction of a carbon oxide-containing raw material gas using a friend oxide powder including a Co oxide as a catalyst, wherein at least one type selected from metal cobalt, carbon-containing cobalt metals, and cobalt-carbon compounds is contained (encapsulated) in the fiber in a wrapped state. This method for producing a carbon nanofiber includes: producing a carbon nanofiber by, a vapor phase reaction of a carbon oxide-containing raw material gas using a mixed powder of a Co oxide and a Mg oxide as a catalyst, wherein a mixed powder of CoO and MgO, which is obtained by hydrogen-reducing a mixed powder of Co3O4 and MgO using a reduction gas having a hydrogen concentration in which metal cobalt is not generated, is used as the catalyst.
    Type: Application
    Filed: September 28, 2012
    Publication date: August 28, 2014
    Inventors: Masahiro Hagiwara, Hiroyuki Imai
  • Patent number: 8816374
    Abstract: A light emitting diode includes a substrate, graphene layer, a first semiconductor layer, an active layer, a second semiconductor layer, a first electrode, a second electrode, and a reflection layer. The first semiconductor layer, the active layer, and the second semiconductor layer are stacked on the substrate in sequence. The first electrode is electrically connected with the second semiconductor layer and the second electrode electrically is connected with the second part of the carbon nanotube layer. The graphene layer is located on at least one of the first semiconductor layer and the second semiconductor layer. The reflection layer covers the second semiconductor layer.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: August 26, 2014
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Yang Wei, Shou-Shan Fan
  • Patent number: 8815124
    Abstract: Photovoltaic cells comprising an active layer comprising, as p-type material, conjugated polymers such as polythiophene and regioregular polythiophene, and as n-type material at least one fullerene derivative. The fullerene derivative can be C60, C70, or C84. The fullerene also can be functionalized with indene groups. Improved efficiency can be achieved.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: August 26, 2014
    Assignees: Solvay USA, Inc., Nano-C, Inc.
    Inventors: Darin W. Laird, Reza Stegamat, Henning Richter, Viktor Vejins, Larry Scott, Thomas A. Lada, Malika Daadi
  • Publication number: 20140231820
    Abstract: A graphene memory includes a source and a drain spaced apart from each other on a conductive semiconductor substrate, a graphene layer contacting the conductive semiconductor substrate and spaced apart from and between the source and the drain, and a gate electrode on the graphene layer. A Schottky barrier is formed between the conductive semiconductor substrate and the graphene layer such that the graphene layer is used as a charge-trap layer for storing charges.
    Type: Application
    Filed: August 6, 2013
    Publication date: August 21, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-ho LEE, Hyun-jong CHUNG, Seong-jun PARK, Kyung-eun BYUN, David SEO, Hyun-jae SONG, Jin-seong HEO
  • Publication number: 20140235123
    Abstract: An optically transparent and electrically conductive film composed of metal nanowires or carbon nanotubes combined with pristine graphene with a metal nanowire-to-graphene or carbon nanotube-to-graphene weight ratio from 1/99 to 99/1, wherein the pristine graphene is single-crystalline and contains no oxygen and no hydrogen, and the film exhibits an optical transparence no less than 80% and sheet resistance no higher than 300 ohm/square. This film can be used as a transparent conductive electrode in an electro-optic device, such as a photovoltaic or solar cell, light-emitting diode, photo-detector, touch screen, electro-wetting display, liquid crystal display, plasma display, LED display, a TV screen, a computer screen, or a mobile phone screen.
    Type: Application
    Filed: February 21, 2013
    Publication date: August 21, 2014
    Inventors: Yi-jun Lin, Aruna Zhamu, Bor Z. Jang
  • Patent number: 8809153
    Abstract: Graphene transistor devices and methods of their fabrication are disclosed. In accordance with one method, a resist is deposited to pattern a gate structure area over a graphene channel on a substrate. In addition, gate dielectric material and gate electrode material are deposited over the graphene channel and the resist. Further, the resist and the electrode and dielectric materials that are disposed above the resist are lifted-off to form a gate structure including a gate electrode and a gate dielectric spacer and to expose portions of the graphene channel that are adjacent to the gate structure. Additionally, source and drain electrodes are formed over the exposed portions of the graphene channel.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: August 19, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Phaedon Avouris, Damon B. Farmer, Yu-Ming Lin, Yu Zhu
  • Patent number: 8808580
    Abstract: The present invention relates to a composite of carbon nanotubes and of graphenes in agglomerated solid form comprising: a) carbon nanotubes, the content of which represents from 0.1% to 50% by weight, preferably from 10% to 40% by weight relative to the total weight of the composite; b) graphenes, the content of which represents from 0.1% to 20% by weight, preferably from 1% to 10% by weight relative to the total weight of the composite; and c) a polymer composition comprising at least one thermoplastic polymer and/or one elastomer. The present invention also relates to a process for preparing said composite, its use for the manufacture of a composite product, and also to the various applications of the composite product.
    Type: Grant
    Filed: April 19, 2011
    Date of Patent: August 19, 2014
    Assignee: Arkema France
    Inventors: Dominique Plee, Alexander Korzhenko
  • Publication number: 20140225150
    Abstract: The disclosure provides a light-emitting diode and a method for manufacturing the same. The light-emitting diode comprises a N-type metal electrode, a N-type semiconductor layer contacted with the N-type metal electrode, a P-type semiconductor layer, a light-emitting layer interposed between the N-type semiconductor layer and the P-type semiconductor layer, a low-contact-resistance material layer positioned on the P-type semiconductor layer, a transparent conductive layer covered the low-contact-resistance material layer and the P-type semiconductor layer, and a P-type metal electrode positioned on the transparent conductive layer.
    Type: Application
    Filed: October 15, 2013
    Publication date: August 14, 2014
    Applicant: Lextar Electronics Corporation
    Inventors: Chia-Lin HSIAO, Nai-Wei Hsu, Te-Chung Wang, Tsung-Yu Yang
  • Patent number: 8804101
    Abstract: A lightweight, low volume, inexpensive LADAR sensor incorporating 3-D focal plane arrays is adapted specifically for personal electronic appliances. The present invention generates, at high speed, 3-D image maps and object data at short to medium ranges. The techniques and structures described may be used to extend the range of long range systems as well, though the focus is on compact, short to medium range ladar sensors suitable for use in personal electronic devices. 3-D focal plane arrays are used in a variety of physical configurations to provide useful new capabilities to a variety of personal electronic appliances.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: August 12, 2014
    Assignee: Advanced Scientific Concepts, Inc.
    Inventors: Joseph Spagnolia, Howard Bailey, Patrick Gilliland, Barton Goldstein, Brad Short, Laurent Heughebaert, Roger Stettner
  • Patent number: 8803132
    Abstract: A method of fabricating a semiconducting device is disclosed. A graphene sheet is formed on a substrate. At least one slot is formed in the graphene sheet, wherein the at least one slot has a width that allows an etchant to pass through the graphene sheet. An etchant is applied to the substrate through the at least one slot formed in the graphene sheet to etch the substrate.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: August 12, 2014
    Assignee: International Business Machines Corporation
    Inventors: Damon B. Farmer, Aaron D. Franklin, Joshua T. Smith
  • Patent number: 8803130
    Abstract: Graphene transistor devices and methods of their fabrication are disclosed. One such graphene transistor device includes source and drain electrodes and a gate structure including a dielectric sidewall spacer that is disposed between the source and drain electrodes. The device further includes a graphene layer that is adjacent to at least one of the source and drain electrodes, where an interface between the source/drain electrode(s) and the graphene layer maintains a consistent degree of electrical conductivity throughout the interface.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: August 12, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Phaedon Avouris, Damon B. Farmer, Yu-Ming Lin, Yu Zhu
  • Patent number: 8803131
    Abstract: An integrated circuit includes a graphene layer, the graphene layer comprising a region of undoped graphene, the undoped graphene comprising a channel of a transistor, and a region of doped graphene, the doped graphene comprising a contact of the transistor; and a gate of the transistor, the gate comprising a carbon nanotube film. A method of fabricating an integrated circuit comprising graphene and carbon nanotubes, includes forming a graphene layer; doping a portion of the graphene layer, resulting in doped graphene and undoped graphene; forming a carbon nanotube film; and etching the carbon nanotube film to form a gate of a transistor, wherein the transistor further comprises a channel comprising the undoped graphene and a contact comprising the doped graphene. A transistor includes a gate, the gate comprising a carbon nanotube film; a channel, the channel comprising undoped graphene; and a contact, the contact comprising doped graphene.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: August 12, 2014
    Assignee: International Business Machines Corporation
    Inventors: Yu-Ming Lin, Jeng-Bang Yau
  • Patent number: 8796668
    Abstract: An integrated circuit includes a graphene layer, the graphene layer comprising a region of undoped graphene, the undoped graphene comprising a channel of a transistor, and a region of doped graphene, the doped graphene comprising a contact of the transistor; and a gate of the transistor, the gate comprising a carbon nanotube film. A method of fabricating an integrated circuit comprising graphene and carbon nanotubes, includes forming a graphene layer; doping a portion of the graphene layer, resulting in doped graphene and undoped graphene; forming a carbon nanotube film; and etching the carbon nanotube film to form a gate of a transistor, wherein the transistor further comprises a channel comprising the undoped graphene and a contact comprising the doped graphene. A transistor includes a gate, the gate comprising a carbon nanotube film; a channel, the channel comprising undoped graphene; and a contact, the contact comprising doped graphene.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: August 5, 2014
    Assignee: International Business Machines Corporation
    Inventors: Yu-Ming Lin, Jeng-Bang Yau
  • Patent number: 8796096
    Abstract: A method of fabricating a semiconducting device is disclosed. A graphene sheet is formed on a substrate. At least one slot is formed in the graphene sheet, wherein the at least one slot has a width that allows an etchant to pass through the graphene sheet. An etchant is applied to the substrate through the at least one slot formed in the graphene sheet to etch the substrate.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: August 5, 2014
    Assignee: International Business Machines Corporation
    Inventors: Damon B. Farmer, Aaron D. Franklin, Joshua T. Smith
  • Patent number: 8796664
    Abstract: A graphene-based composite structure is disclosed. The graphene-based composite structure includes a graphene layer, a transition metal layer, and a substrate. The graphene layer, transition metal layer, and substrate are stacked together in series to form a sandwich structure. The graphene layer and the transition metal layer are coupled by d-p orbitals hybridization. The transition metal layer and the substrate are also coupled by d-p orbitals hybridization. A method for making graphene-based composite structure is also disclosed.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: August 5, 2014
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Wen-Hui Duan, Yuan-Chang Li, Peng-Cheng Chen, Jian Wu, Bing-Lin Gu
  • Publication number: 20140212668
    Abstract: Provided are graphene nanoribbons (GNRs), methods of making GNRs, and uses of the GNRs. The methods can provide control over GNR parameters such as, for example, length, width, and edge composition (e.g., edge functional groups). The methods are based on a metal catalyzed cycloaddition reaction at the carbon-carbon triple bonds of a poly(phenylene ethynylene) polymer. The GNRs can be used in devices such a microelectronic devices.
    Type: Application
    Filed: April 27, 2012
    Publication date: July 31, 2014
    Applicant: CORNELL UNIVERSITY
    Inventors: William R. Dichtel, Hasan Arslan, Fernando J. Uribe-Romo
  • Publication number: 20140205796
    Abstract: A graphene nanomesh includes a graphene sheet having a plurality of pores formed therethrough. Each pore has a first diameter defined by an inner edge of the graphene sheet. A plurality of passivation elements are bonded to the inner edge of each pore. The plurality of passivation elements defines a second diameter that is less than the first diameter to decrease an overall diameter of at least one pore among the plurality of pores.
    Type: Application
    Filed: January 18, 2013
    Publication date: July 24, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ali Afzali-Ardakani, Ahmed A. Maarouf, Glenn J. Martyna
  • Patent number: 8785763
    Abstract: Nanostructures are joined using one or more of a variety of materials and approaches. As consistent with various example embodiments, two or more nanostructures are joined at a junction between the nanostructures. The nanostructures may touch or be nearly touching at the junction, and a joining material is deposited and nucleates at the junction to couple the nanostructures together. In various applications, the nucleated joining material facilitates conductivity (thermal and/or electric) between the nanostructures. In some embodiments, the joining material further enhances conductivity of the nanostructures themselves, such as by growing along the nanostructures and/or doping the nanostructures.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: July 22, 2014
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Melburne C. LeMieux, Ajay Virkar, Zhenan Bao
  • Patent number: 8785912
    Abstract: Graphene electronic devices may include a gate electrode on a substrate, a first gate insulating film covering the gate electrode, a plurality of graphene channel layers on the substrate, a second gate insulating film between the plurality of graphene channel layers, and a source electrode and a drain electrode connected to both edges of each of the plurality of graphene channel layers.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: July 22, 2014
    Assignees: Samsung Electronics Co., Ltd., SNU R&DB Foundation
    Inventors: Hyun-jong Chung, Jae-hong Lee, Jae-ho Lee, Hyung-cheol Shin, Sun-ae Seo, Sung-hoon Lee, Jin-seong Heo, Hee-jun Yang
  • Patent number: 8778701
    Abstract: A production method of the present disclosure includes: a first step of preparing a multi-layer graphene, and an iron oxide that is a ferromagnetic material contacting the graphene and containing Fe3O4; and a second step of applying a voltage or a current between the graphene and the iron oxide with an electric potential of the graphene being positive relative to that of the iron oxide, so as to oxidize a part of the graphene or oxidize a part of the graphene and a part of Fe3O4, and thus to form a barrier layer composed of oxidized graphene or of oxidized graphene and Fe2O3 between the graphene and the iron oxide, and thereby forming a spin injection electrode that includes the graphene, the iron oxide, and the barrier layer located at an interface between the graphene and the iron oxide, and that allows spins to be injected into the graphene from the iron oxide via the barrier layer.
    Type: Grant
    Filed: April 1, 2013
    Date of Patent: July 15, 2014
    Assignee: Panasonic Corporation
    Inventors: Akihiro Odagawa, Nozomu Matsukawa
  • Patent number: 8778197
    Abstract: The present invention relates to graphene windows and methods for making same. One method comprises selecting a high purity metal foil, growing a layer of graphene on a first face of the metal foil, patterning the second face of the graphene-modified foil with a polymer, wherein the second face of the graphene-modified foil has an exposed region and etching the second face of the graphene-modified foil in the exposed region until exposing the first layer of graphene.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: July 15, 2014
    Assignee: Clean Energy Labs, LLC
    Inventors: William Neil Everett, William Martin Lackowski, Joseph F. Pinkerton
  • Publication number: 20140193740
    Abstract: A fuel cell includes a proton-exchange membrane, and a cathode and anode fixed on its opposite sides. The anode delimits a flow conduit between a molecular-oxygen inlet area and a water outlet area. The cathode includes a support for catalyst material. The support has first and second materials to which catalyst is fixed, the first material being a graphitized material. The second material has a resistance to corrosion by oxygen that is greater than that of the first material. A quantity of the second material at the inlet area is greater than a quantity of the second material at the water outlet. The cathode comprises a first layer including the first material and a second layer including the second material. A thickness of the second layer decreases between the molecular-oxygen inlet area and the water outlet area.
    Type: Application
    Filed: March 29, 2012
    Publication date: July 10, 2014
    Applicant: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Remi Vincent, Sylvie Escribano, Alejandro Franco, Laure Guetaz, Guillaume Krosnicki
  • Patent number: 8771630
    Abstract: A method for the preparation of graphene is provided, which includes: (a) oxidizing a graphite material to form graphite oxide; (b) dispersing graphite oxide into water to form an aqueous suspension of graphite oxide; (c) adding a dispersing agent to the aqueous suspension of graphite oxide; and (d) adding an acidic reducing agent to the aqueous suspension of graphite oxide, wherein graphite oxide is reduced to graphene by the acidic reducing agent, and graphene is further bonded with the dispersing agent to form a graphene dispersion containing a surface-modified graphene. The present invention provides a method for the preparation of graphene using an acidic reducing agent. The obtained graphene can be homogeneously dispersed in water, an acidic solution, a basic solution, or an organic solution.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: July 8, 2014
    Assignee: Enerage, Inc.
    Inventors: Yi-Shuen Wu, Cheng-Yu Hsieh, Cheng-Shu Peng, Jing-Ru Chen, Jun-Meng Lin, Geng-Wei Lin
  • Publication number: 20140184249
    Abstract: A condition monitoring paint is formed of a base material, and conductive components for forming a conductive network. The conductive components may include nano-particles or nano-structures. The paint in used in a condition monitoring system for monitoring the integrity or condition of structures, such as bridges.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Applicant: UNIVERSITY OF STRATHCLYDE
    Inventors: Mohamed Saafi, David McGahon
  • Patent number: 8753772
    Abstract: Rechargeable lithium-sulfur batteries having a cathode that includes a graphene-sulfur nanocomposite can exhibit improved characteristics. The graphene-sulfur nanocomposite can be characterized by graphene sheets with particles of sulfur adsorbed to the graphene sheets. The sulfur particles have an average diameter less than 50 nm.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: June 17, 2014
    Assignee: Battelle Memorial Institute
    Inventors: Jun Liu, John P. Lemmon, Zhenguo Yang, Yuliang Cao, Xiaolin Li
  • Publication number: 20140158989
    Abstract: According to example embodiments, an electronic device includes: a semiconductor layer; a graphene directly contacting a desired (and/or alternatively predetermined) area of the semiconductor layer; and a metal layer on the graphene. The desired (and/or alternatively predetermined) area of the semiconductor layer include one of: a constant doping density, a doping density that is equal to or less than 1019 cm?3, and a depletion width of less than or equal to 3 nm.
    Type: Application
    Filed: December 11, 2013
    Publication date: June 12, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyung-eun BYUN, Seong-jun PARK, David SEO, Hyun-jae SONG, Jae-ho LEE, Hyun-jong CHUNG, Jin-seong HEO
  • Publication number: 20140160630
    Abstract: Disclosed is a free-standing hybrid nanomembrane capable of energy storage. The free-standing hybrid nanomembrane includes carbon nanotube sheets and a conducting polymer coated on the carbon nanotube sheets. The carbon nanotube sheets are densified sheets formed by evaporating an alcohol from carbon nanotube aerogel sheets. The conducting polymer is coated on the carbon nanotube sheets by vapor phase polymerization. Further disclosed is a method for fabricating the free-standing hybrid nanomembrane.
    Type: Application
    Filed: December 11, 2012
    Publication date: June 12, 2014
    Applicant: IUCF-HYU (Industry-University Cooperation Foundation Hanyang University)
    Inventor: IUCF-HYU (Industry-University Cooperation Foundation Hanyang University)
  • Publication number: 20140154941
    Abstract: A unitary graphene matrix composite comprising: (a) a unitary graphene matrix containing an oxygen content of 0.001% to 10% by weight, obtained from heat-treating a graphene oxide gel at a temperature higher than 100° C. and contains no discrete graphene platelets derived from the graphene oxide gel; (b) a carbon or graphite filler phase selected from carbon or graphite fiber, carbon or graphite nano-fiber, carbon nano-tube, carbon nano-rod, meso-phase carbon particle, meso-carbon micro-bead, exfoliated graphite flake with a thickness greater than 100 nm, exfoliated graphite or graphite worm, coke particle, needle coke, carbon black or acetylene black particle, activated carbon particle, or a combination thereof. The carbon or graphite filler phase is preferably in a particulate, filamentary, or rod-like form dispersed in and bonded by the unitary graphene matrix.
    Type: Application
    Filed: December 5, 2012
    Publication date: June 5, 2014
    Inventors: Aruna Zhamu, Mingchao Wang, Wei Xiong, Bor Z. Jang
  • Publication number: 20140151770
    Abstract: A method for depositing a material on a graphene layer includes arranging a graphene layer having an exposed substantially planar surface proximate to a magnetron assembly that is operative to emit a plasma plume substantially along a first line, wherein the exposed planar surface of the graphene layer is arranged at an angle that is non-orthogonal to the first line where the first line intersects the exposed planar surface; and emitting the plasma plume from the magnetron assembly such that a layer of deposition material is disposed on the graphene layer without appreciably damaging the graphene layer.
    Type: Application
    Filed: November 30, 2012
    Publication date: June 5, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ching-Tzu Chen, Marcin J. Gajek, Simone Raoux
  • Publication number: 20140151640
    Abstract: A method of fabricating a semiconducting device is disclosed. A graphene sheet is formed on a substrate. At least one slot is formed in the graphene sheet, wherein the at least one slot has a width that allows an etchant to pass through the graphene sheet. An etchant is applied to the substrate through the at least one slot formed in the graphene sheet to etch the substrate.
    Type: Application
    Filed: December 4, 2012
    Publication date: June 5, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Damon B. Farmer, Aaron D. Franklin, Joshua T. Smith
  • Publication number: 20140151643
    Abstract: A method of fabricating a semiconducting device is disclosed. A graphene sheet is formed on a substrate. At least one slot is formed in the graphene sheet, wherein the at least one slot has a width that allows an etchant to pass through the graphene sheet. An etchant is applied to the substrate through the at least one slot formed in the graphene sheet to etch the substrate.
    Type: Application
    Filed: August 20, 2013
    Publication date: June 5, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Damon B. Farmer, Aaron D. Franklin, Joshua T. Smith
  • Publication number: 20140151771
    Abstract: A method for depositing a material on a graphene layer includes arranging a graphene layer having an exposed substantially planar surface proximate to a magnetron assembly that is operative to emit a plasma plume substantially along a first line, wherein the exposed planar surface of the graphene layer is arranged at an angle that is non-orthogonal to the first line where the first line intersects the exposed planar surface; and emitting the plasma plume from the magnetron assembly such that a layer of deposition material is disposed on the graphene layer without appreciably damaging the graphene layer.
    Type: Application
    Filed: August 13, 2013
    Publication date: June 5, 2014
    Applicant: International Business Machines Corporation
    Inventors: Ching-Tzu Chen, Marcin J. Gajek, Simone Raoux
  • Patent number: 8742478
    Abstract: A graphene transistor includes: a gate electrode on a substrate; a gate insulating layer on the gate electrode; a graphene channel on the gate insulating layer; a source electrode and a drain electrode on the graphene channel, the source and drain electrode being separate from each other; and a cover that covers upper surfaces of the source electrode and the drain electrode and forms an air gap above the graphene channel between the source electrode and the drain electrode.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: June 3, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-jong Chung, U-in Chung, Ki-nam Kim
  • Patent number: 8742400
    Abstract: A graphene switching device includes a first electrode and an insulating layer in first and second regions of the semiconductor substrate, respectively, a plurality of metal particles on a surface of the semiconductor substrate between the first and second regions, a graphene layer on the plurality of metal particles and extending on the insulating layer, a second electrode on the graphene layer in the second region and configured to face the insulating layer, a gate insulating layer configured to cover the graphene layer, and a gate electrode on the gate insulating layer. The semiconductor substrate forms an energy barrier between the graphene layer and the first electrode.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: June 3, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: David Seo, Sang-wook Kim, Seong-jun Park, Young-jun Yun, Yung-hee Yvette Lee, Chang-seung Lee
  • Publication number: 20140147648
    Abstract: A unitary graphene layer or graphene single crystal containing closely packed and chemically bonded parallel graphene planes having an inter-graphene plane spacing of 0.335 to 0.40 nm and an oxygen content of 0.01% to 10% by weight, which unitary graphene layer or graphene single crystal is obtained from heat-treating a graphene oxide gel at a temperature higher than 100° C., wherein the average mis-orientation angle between two graphene planes is less than 10 degrees, more typically less than 5 degrees. The molecules in the graphene oxide gel, upon drying and heat-treating, are chemically interconnected and integrated into a unitary graphene entity containing no discrete graphite flake or graphene platelet. This graphene monolith exhibits a combination of exceptional thermal conductivity, electrical conductivity, mechanical strength, surface smoothness, surface hardness, and scratch resistance unmatched by any thin-film material of comparable thickness range.
    Type: Application
    Filed: November 26, 2012
    Publication date: May 29, 2014
    Inventors: Aruna Zhamu, Mingchao Wang, Wei Xiong, Bor Z. Jang
  • Publication number: 20140147675
    Abstract: An approach is provided for a structure and a method for a graphene-based apparatus. The method comprises acts of forming a graphene layer on a metal layer; forming a protective layer on the graphene layer that makes the graphene layer disposed between the metal layer and the protective layer; transferring the protective layer with the graphene layer and the metal layer onto a substrate; removing the metal layer off from the graphene layer; and forming a conducting layer on the graphene layer. Accordingly, the proposed structure of the graphene-based apparatus is able to prevent graphene damage during the transferring, and because of he use of the protective layer in the structure, the roller can be used to apply the stress which enables roll-to-roll type process and significantly improves the manufacturing throughput.
    Type: Application
    Filed: November 27, 2012
    Publication date: May 29, 2014
    Applicant: HCGT LTD.
    Inventors: Shu-Jen Han, Qing Cao
  • Publication number: 20140147180
    Abstract: There is disclosed a fuser member that includes a substrate layer and a surface layer disposed on the substrate layer. The surface layer includes a fluoropolymer having dispersed therein fluorinated graphene particles. A method of manufacturing a fuser member is also provided.
    Type: Application
    Filed: November 29, 2012
    Publication date: May 29, 2014
    Applicant: XEROX CORPORATION
    Inventors: Yu Qi, Nan-Xing Hu, Qi Zhang, Brynn M. Dooley
  • Patent number: 8734685
    Abstract: The present invention relates to design and development of carbon nanotubes (CNT) reinforced electrically conducting synthetic foams comprising resin matrix system, carbon nanotubes, hollow glass microspheres and optionally hardener or catalyst for electrical conductivity and related applications especially electromagnetic interference (EMI) shielding.
    Type: Grant
    Filed: February 9, 2009
    Date of Patent: May 27, 2014
    Assignee: Director General, Defence Reserch & Development Organization
    Inventors: Sundaram Sankaran, Samudra Dasgupta, Ravi Sekhar Kandala, Ravishankar Bare Narayana
  • Patent number: 8735536
    Abstract: Disclosed are new semiconducting polymers. The polymers disclosed herein can exhibit high carrier mobility and/or efficient light absorption/emission characteristics, and can possess certain processing advantages such as solution-processability and/or good stability at ambient conditions.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: May 27, 2014
    Assignee: Polyera Corporation
    Inventors: Jordan Quinn, Hualong Pan, Antonio Facchetti
  • Patent number: 8734684
    Abstract: A method for producing a metallic carbon nanotube, by which a dispersion with a high concentration can be obtained. Specifically disclosed is a method for producing a metallic carbon nanotube, which comprises a fullerene addition step wherein fullerenes are added into a carbon nanotube-containing solution in which metallic carbon nanotubes and semiconductive carbon nanotubes are mixed, and a taking-out step wherein carbon nanotubes dispersed by the added fullerenes are taken out.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: May 27, 2014
    Assignee: Kuraray Co., Ltd.
    Inventor: Takahiro Kitano
  • Patent number: 8735242
    Abstract: A method of forming a semiconductor device includes forming a field-effect transistor (FET), and forming a fuse which includes a graphene layer and is electrically connected to the FET.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: May 27, 2014
    Assignee: International Business Machines Corporation
    Inventor: Wenjuan Zhu
  • Patent number: 8734752
    Abstract: A method of synthesis of a fulleride of metal nano-cluster is provided. The method is characterized in mechanically alloying metal nano-clusters with fullerene-type clusters. Fullerene molecules in the fulleride of metal nano-cluster are preserved. The alloying is done by milling in a planetary mill. A material including a fulleride of a metal nano-cluster is also provided.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: May 27, 2014
    Assignee: Siemens Aktiengesellschaft
    Inventors: Vladimir Davidovich Blank, Gennadii Ivanovich Pivovarov, Mikhail Yurievich Popov
  • Patent number: 8729387
    Abstract: Disclosed is an organic photoelectric conversion element having high photoelectric conversion efficiency and high durability. Also disclosed are a solar cell and an optical sensor array, each using the organic photoelectric conversion element. The organic photoelectric conversion element comprises a bulk heterojunction layer wherein an n-type semiconductor material and a p-type semiconductor material are mixed. The organic photoelectric conversion element is characterized in that the n-type semiconductor material is a polymer compound and the p-type semiconductor material is a low-molecular-weight compound.
    Type: Grant
    Filed: August 21, 2009
    Date of Patent: May 20, 2014
    Assignee: Konica Minolta Holdings, Inc.
    Inventors: Yasushi Okubo, Takahiko Nojima, Hiroaki Itoh, Ayako Wachi
  • Patent number: 8728429
    Abstract: In certain implementations, a method of manufacturing electrically conductive nanodiamond particles involves providing at least one type of carbon-containing explosive material and at least one type of non-explosive material; wherein the non-explosive material contains at least one or more than one element or species other than nitrogen that serve as a nanodiamond dopant; mixing the carbon containing explosive material with the non-explosive material; detonating the mixture under conditions of negative oxygen balance in the presence of a cooling medium; purifying the product of detonation from incombustible impurities; and carrying out additional processing for activation or enhancement of electrical conductance. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: May 20, 2014
    Assignee: International Technology Center
    Inventor: Olga Shenderova
  • Publication number: 20140125322
    Abstract: A nanogap device which may include a first insulation layer having a nanopore formed therein, a first channel layer which may be on the first insulation layer, a first source electrode and a first drain electrode which may be respectively in contact with both ends of the first channel layer, a second insulation layer which may cover the first channel layer, the first source electrode, and the first drain electrode, and a first nanogap electrode which may be on the second insulation layer and may be divided into two parts with a nanogap, which faces the nanopore, interposed between the two parts.
    Type: Application
    Filed: April 3, 2013
    Publication date: May 8, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang-seung LEE, Yong-sung KIM, Jeo-young SHIM, Joo-ho LEE
  • Publication number: 20140127488
    Abstract: A graphene oxide-coated graphitic foil, composed of a graphitic substrate or core layer having two opposed primary surfaces and at least a graphene oxide coating layer deposited on at least one of the two primary surfaces, wherein the graphitic substrate layer has a thickness preferably from 0.34 nm to 1 mm, and the graphene oxide coating layer has a thickness preferably from 0.5 nm to 1 mm and an oxygen content of 0.01%-40% by weight based on the total graphene oxide weight. The graphitic substrate layer may be preferably selected from flexible graphite foil, graphene film, graphene paper, graphite particle paper, carbon-carbon composite film, carbon nano-fiber paper, or carbon nano-tube paper. This graphene oxide-coated laminate exhibits a combination of exceptional thermal conductivity, electrical conductivity, mechanical strength, surface smoothness, surface hardness, and scratch resistance unmatched by any thin-film material of comparable thickness range.
    Type: Application
    Filed: November 2, 2012
    Publication date: May 8, 2014
    Inventors: Aruna Zhamu, Mingchao Wang, Wei Xiong, Bor Z. Jang
  • Publication number: 20140124738
    Abstract: A small gap semiconductor system comprises: two parallel semiconductor sheets formed of atomically thin small gap semiconductor, one sheet containing electrons and the other containing holes; a dielectric insulating barrier arranged parallel to and separating the two semiconductor sheets; independent electrical contacts to each of the semiconductor sheets; two dielectric layers above and below the two semiconductor sheets respectively; and two conducting gates sandwiching the two semiconductor sheets and separated from the respective semiconductor sheets by the respective dielectric layers.
    Type: Application
    Filed: November 7, 2013
    Publication date: May 8, 2014
    Inventors: Alexander R. HAMILTON, Andrea PERALI, David NEILSON