Abstract: A method for manufacturing sidewall contacts for a chalcogenide memory device is disclosed. A first conductive layer is initially deposited on top of a first oxide layer. The first conductive layer is then patterned and etched using well-known processes. Next, a second oxide layer is deposited on top of the first conductive layer and the first oxide layer. An opening is then etched into at least the first oxide layer such that a portion of the first conductive layer is exposed within the opening. The exposed portion of the first conductive layer is then removed from the opening such that the first conductive layer is flush with an inner surface or sidewall of the opening. After depositing a chalcogenide layer on top of the second oxide layer, filling the opening with chalcogenide, a second conductive layer is deposited on top of the chalcogenide layer.

Abstract: A method and system for monitoring service quality in a restaurant are disclosed. Multiple sensor modules are installed at each table of a restaurant for detecting restaurant customer service related information. The detected restaurant customer service related information is transmitted, preferably, over-the-air to a central computer unit having a receiver for receiving the detected restaurant customer service related information transmitted by the sensor modules over-the-air. A display monitor, coupled to the central computer unit, can be utilized to display the detected restaurant customer service related information received by the receiver to a restaurant manager in a real-time basis regardless of whether the restaurant manager is present at the restaurant or at a remote location.

Abstract: An apparatus for reducing switching regulator noise from outputs of multiple switching regulators is disclosed. The apparatus includes an operational amplifier, an capacitor, a resistor and a pair of diodes. The switching regulators are connected in series to provide a positive output rail and a negative output rail. The output of the operational amplifier in connected to an inverting input of the operational amplifier and a positive sensing input of one of the switching regulators. The non-inverting input of the operation amplifier is connected to the positive output rail of one of the switching regulator via the capacitor. The resistor is connected between a positive voltage output of one of the switching regulators and the capacitors. The pair of diodes is connected between the positive voltage output of one of the switching regulators and the negative output rail of the switching regulators.

Abstract: A method and apparatus for controlling uplink transmission power in a satellite communication system is disclosed. The satellite communication system includes a satellite and one or more earth stations, one of which serving as a control station. The satellite can receive uplink signals from any one of the earth stations and retransmits the uplink signals as downlink signals, along with a beacon signal. The control station measures the power of the downlink signals and the beacon signal received from the satellite, and also measures the noise power near the beacon signal. From these measurements, the control station determines an appropriate gain value of the power for uplink transmissions for each of the earth stations.

Abstract: A method for manufacturing sidewall contacts for a chalcogenide memory device is disclosed. A first conductive layer is initially deposited on top of a first oxide layer. The first conductive layer is then patterned and etched using well-known processes. Next, a second oxide layer is deposited on top of the first conductive layer and the first oxide layer. An opening is then etched into at least the first oxide layer such that a portion of the first conductive layer is exposed within the opening. The exposed portion of the first conductive layer is then removed from the opening such that the first conductive layer is flush with an inner surface or sidewall of the opening. After depositing a chalcogenide layer on top of the second oxide layer, filling the opening with chalcogenide, a second conductive layer is deposited on top of the chalcogenide layer.

Abstract: A radiation hardened silicon-on-insulator transistor is disclosed. A dielectric layer is disposed on a substrate, and a transistor structure is disposed on the dielectric layer. The transistor structure includes a body region, a source region, a drain region, and a gate layer. The body region is formed on a first surface portion of the dielectric layer, the source region is formed on a second surface portion of the dielectric layer contiguous with the first surface portion, the drain region is formed on a third surface portion of the dielectric layer contiguous with the first surface portion, and the gate layer overlies the body region and being operative to induce a channel in that portion of the body region disposed between and adjoining the source region and the drain region. In addition, multiple diffusions are placed across two edges of the source region.

Abstract: A method for fabricating resistors within a semiconductor integrated circuit device is disclosed. A resistor is fabricated by first depositing a passivation layer on a semiconductor substrate having multiple transistors previously formed thereon. Next, a first contact window and a second contact window are formed through the first passivation layer at a first contact location and a second contact location, respectively. The first and second contact windows are then filled with metal, such as tungsten, and the metal at the first and second contact windows is planarized to form a first bottom contact and a second bottom contact, respectively. A resistive film, such as polysilicon, subsequently deposited over the first passivation layer. Next, a second passivation layer is formed over the resistive film. Finally, a first top contact and a second top contact are formed to respectively connect the first bottom contact and the second bottom contact to the resistive film.

Abstract: A single-event upset immune flip-flop circuit is disclosed. The single-event upset immune flip-flop circuit includes a first single-event upset immune latch and a second single-event upset immune latch. The first single-event upset immune latch has two inputs and two outputs. The second single-event upset immune latch also has two inputs and two outputs. The two inputs of the second single-event upset immune latch is connected to the two outputs of the first single-event upset immune latch. The state of the first single-event upset immune latch changes only when the signal polarities at both inputs of the first single-event upset immune latch are identical. Similarly, the state of the second single-event upset immune latch changes only when the signal polarities at both inputs of the second single-event upset immune latch are identical.

Abstract: A method for manufacturing a programmable chalcogenide fuse within a semiconductor device is disclosed. A resistor is initially formed on a substrate. Then, a chalcogenide fuse is formed on top of the resistor. Finally, a conductive layer is deposited on top of the chalcogenide fuse for providing electrical conduction to the chalcogenide fuse.

Abstract: A single-event upset immune frequency divider circuit is disclosed. The single-event upset immune frequency divider circuit includes a dual-path shift register, a dual-path multiplexor, and a summing circuit. The dual-path shift register has a clock input, one signal input pair and multiple signal output pairs. The dual-path multiplexor has multiple signal input pairs and one output pair. The signal input pairs of the dual-path multiplexor are respectively connected to the signal output pairs of the dual-input shift register. The dual-path multiplexor selects one of the signal output pairs of the dual-path shift register for feeding back into the signal input pair of the dual-path shift register. The summing circuit then sums the signal input pair of the dual-path shift register to generate an output clock signal that is a fraction of the frequency of an input clock signal at the clock input of the dual-path shift register.

Abstract: An apparatus for providing mechanical support to a column grid array package is disclosed. The column grid array package uses solder columns to provide electrical connections between a ceramic substrate and a printed circuit board. The ceramic substrate has two sides, with an integrated circuit chip mounted on one side and many input/output pads mounted on the other side. Solder columns are attached between the input/output pads and the printed circuit board. A corner post is located at each corner of the column grid array package to secure the position of the ceramic substrate in relation to the printed circuit board.

Abstract: A method and apparatus for evaluating a confidence level of a decoded barcode value is disclosed. A digit score is assigned to a digit within a barcode. When decoding the barcode, if a deduction is required to decode the digit, then the digit score for the digit is reduced accordingly. After all the digits within the barcode have been decoded, a total score of a decoded barcode value can be determined by adding all the digit scores for all the digits within the barcode. The total score of the decoded barcode value is reduced if a checksum is used to ascertain the value of any digit within the barcode. The decoded barcode value can be accepted only if the total score exceeds a predetermined value.

Abstract: An apparatus for providing mechanical support to a column grid array package is disclosed. The column grid array package uses solder columns to provide electrical connections between a ceramic substrate and a printed circuit board. The ceramic substrate has two sides, with an integrated circuit chip mounted on one side and many input/output pads mounted on the other side. Solder columns are attached between the input/output pads and the printed circuit board. A corner post is located at each corner of the column grid array package to secure the position of the ceramic substrate in relation to the printed circuit board.

Abstract: A method for manufacturing a thermoelectric cooling mechanism for an integrated circuit is disclosed. Initially, electric circuits are formed on one side of a wafer. Subsequently, thermoelectric cooling devices are formed on an opposite side of the same wafer. Specifically, the thermoelectric cooling devices are formed by depositing a first conductive layer, depositing a layer of Peltier material on top of the first conductive layer, building a set of N30 regions and P30 regions within the Peltier material layer, and depositing a second conductive layer on top of the Peltier material layer.

Abstract: A method for providing a fill pattern for integrated circuit designs is disclosed. A keepout file having keepout data is generated from a chip design layout file having chip design layout data. The keepout file includes a map of areas of an integrated circuit design where fill patterns cannot be placed. The map of areas from the keepout file is then overlaid with a fill pattern to yield a fill-pattern file. Fill patterns from the fill-pattern file is removed from locations that coincide with locations as defined by the keepout data to yield a final-fill file with crucial fill pattern data. The crucial fill pattern data from the final-fill file is overlaid on the design layout data in the chip design layout file to yield a complete design layout file. Finally, the design rule integrity and logical to physical correspondence of the complete design layout file is verified.

Abstract: A flexible lightweight rifle recoil pad is disclosed. The rifle recoil pad includes a flexible yoke, an energy-absorbing cushion, and a counter-weight. The flexible yoke, which includes a first end section and a second end section, is sized to fit over a shoulder of a user such that the yoke extends over the top of the shoulder with the first end section positioned on the front of the user's shoulder and the second end section positioned on the rear of the user's shoulder. The energy-absorbing cushion is positioned over the yoke adjacent the first end section. The counter-weight is positioned over the yoke adjacent the second end section.

Abstract: A smart table to be utilized is disclosed. The smart table includes a patron presence detector, a patron counter, a staff presence detector, and a transmitter. The patron presence detector detects information regarding the presence of patrons sitting at the table. The patron counter counts the number of patrons sitting at the table. The staff presence detector detects information regarding the presence of a staff member serving the table. The above-mentioned detected information are subsequently transmitted by the transmitter to a remotely located data processing system.

Abstract: An integrated circuit device having a built-in thermoelectric cooling mechanism is disclosed. The integrated circuit device includes a package and a substrate. Contained within the package, the substrate has a front side and a back side. Electric circuits are fabricated on the front side of the substrate, and multiple thermoelectric cooling devices are fabricated on the back side of the same substrate. The thermoelectric cooling devices are utilized to dissipate heat generated by the electric circuits to the package.

Abstract: A method for manufacturing contacts for a Chalcogenide memory device is disclosed. A via is initially formed within a first oxide layer on a substrate. A conductive layer is then deposited on top of the first oxide layer. A second oxide layer is deposited on the conductive layer. Subsequently, the second oxide layer and the conductive layer are then removed such that the remaining portion of conductive layer within the via flushes with a surface of the first oxide layer. A third oxide layer is deposited on the conductive layer, and the first and second oxide layers. A pattern is formed to remove third layer so that the pattern opens orthgonally across and exposes the conductive layer. Next, a nitride layer is deposited on the third oxide layer, the conductive layer, and the first and second oxide layers. The nitride layer conforms with the contour of the third oxide layer.

Abstract: A method for manufacturing an integrated circuit having high voltage transistors and low voltage transistors is disclosed. First, lightly doped drains are formed in both high voltage transistors and low voltage transistors within the integrated circuit. A thin layer of silicon nitrate film is then deposited on the first and second transistors. Afterwards, a layer of silicon oxide is deposited on the silicon nitride film. After forming oxide spacers on both high voltage transistors and low voltage transistors, the oxide spacers are removed from the low voltage transistors. Finally, diffusion implants are performed on the first and second transistors. As a result, the high voltage transistors possess lightly doped drained junctions.