Abstract: A method and system for enhancing cache memory utilization within a symmetric multiprocessor data-processing system are disclosed. The symmetric multiprocessor data-processing system includes several processing units. These processing units are typically coupled to a system memory via an interconnect. Each of the processing units includes at least one cache memory for storing a subset of data contained within the system memory. Each of the processing units also includes a cache controller for controlling its associated cache memory. Each cache controller includes a mode select to allow an associated cache memory to be selectively operated under a shared mode or a private mode.

Abstract: A method for demodulating digital frequency modulation (FM) signals is disclosed. A group of complex-valued discrete-time FM signal samples is initially received. A corresponding first complex product for each of the complex-valued discrete-time FM signal samples is computed, and a corresponding second complex product for each of the first complex values of the complex-valued discrete-time FM signal samples is computed. Subsequently, an inverse tangent of the second complex products are computed to yield an angle for each of the second complex values, wherein each of the angles represents a second-order difference of a phase of the complex-valued discrete-time FM signal samples. Finally, a digital integration is performed to obtain a first-order difference of the phase of the complex-valued discrete-time FM signal samples.

Abstract: A method for converting a multi-byte dataword in a first extended interchange code to a multi-byte dataword in a second extended interchange code is disclosed. In accordance with the method and system of the present invention, multiple offset arrays and a conversion matrix are provided. Each entry in each of the offset arrays contains an offset index for indexing to the conversion matrix. First, an index value is returned from a corresponding one of the offset arrays, for each byte of a multi-byte dataword in a first interchange code. Then, all of the returned index values are added together to obtain a multi-byte dataword in a second interchange code from the conversion matrix.

Abstract: An apparatus for improving I/O pin interfaces for serial data communications is disclosed. In accordance with a preferred embodiment of the present invention, an improved serial interface is provided, which comprises an oscillator input, a signal input, a counter, a register, and a data output. The counter is utilized to count the number of cycles of the oscillator input for which the signal input is asserted. The register is utilized to receive a value from the counter when the signal input is next de-asserted. The data output is at a first logical state when the signal input is asserted for fewer oscillation cycles than the value stored in the register and the data output is at a second logical state otherwise, such that only one I/O pin is required for serial communications.

Abstract: A method for rebuilding contents of a malfunctioned direct access storage device within a log-structured array is disclosed. In accordance with the method and system of the present invention, each direct access storage device within a log-structured array is divided into multiple segment-columns, and each corresponding segment-column from each direct access storage device within the log-structured array forms a segment. A segment is first located within the direct access storage devices. A determination is made as to whether or not the segment is empty. In response to a determination that the segment is empty, a pointer is moved within a segment-column mapping table from pointing to a segment-column in the malfunctioned direct access storage device to point to a segment-column in a spare direct access storage device of the segment.

Abstract: A method for providing audio sample rate conversion within a data-processing system is disclosed. An audio data stream is first received. If the input sample rate of the audio data stream is not equal to a target sample rate, several frequency multiplications or frequency divisions are selectively performed until the target sample rate is reached. Then, the audio data stream is passed through a lowpass filter having a cutoff frequency that is less than half of the target sample rate. Finally, the audio data stream is output.

Abstract: A method and apparatus for monitoring the performance of an echo canceler within a telephone communications network is disclosed. In accordance with the method and apparatus of the present invention, an embedded echo-cancellation performance monitoring circuit comprises three separate units, namely, a test data injection unit, an echo path simulator unit, and a test data extraction unit. The test data injection unit is utilized to inject test data into a serial data stream intended for an echo canceler. The echo path simulator unit is utilized to simulate an echo path by attenuating the test data in the serial data stream and to loop the test data in the serial data stream back to the echo canceler. The test data extraction unit is utilized to extract the test data from a send-out data stream exiting from the echo canceler.

Abstract: A multi-track density direct access storage device is disclosed. In accordance with a preferred embodiment of the present invention, a direct access storage device for data storage within a data processing system comprises a housing, a rotatable spindle, at least one disk, and several heads. The disk is fixedly mounted to the rotatable spindle, and the rotatable spindle is rotated by a motor within the housing. A first disk surface of the disk has a first track density and a second disk surface of the disk has a second track density; wherein the second track density is preferably greater than the first track density. Each of the several heads contains a transducer to read and write information from and to the disk during the disk rotation.

Abstract: An integrated-circuit design is provided which is represented by a hierarchial data structure. In accordance with the method and system of the present invention, an integrated-circuit design which includes at least one parent circuit represented by a set of parent circuit level data and at least one child circuit represented by a set of child circuit level data. For an open circuit connection within the child circuit, a determination is made as to whether or not the open circuit connection is permissible. In response to a determination that the open circuit connection is permissible, another determination is made as to whether or not the number of I/O pins within the child circuit is greater than the number of open circuit connections within the child circuit.

Abstract: A method for checking security of data received by a computer system within a network environment is disclosed. In accordance with a preferred embodiment of the present invention, an incoming packet from a client is first decrypted within a receiving communications adapter by utilizing a master decryption key. The decrypted incoming packet is then encrypted by utilizing an encryption key identical to an encryption key employed by the client. A determination is made as to whether or not a packet produced from the encryption is identical to the incoming packet. In response to a determination that a packet produced from the encryption is identical to the incoming packet, the decrypted incoming packet is forwarded to a system memory of the computer system. As such, any incoming packet that does not meet this criterion will be rejected as a security threat.

Abstract: A method and system for reducing power consumption of a non-blocking cache memory within a data processing system is disclosed. In accordance with a method and system of the present disclosure, a detection unit, having several index-matching bits, is associated with the cache memory within the data processing system. A determination is made as to whether or not there is a match in the cache memory, in response to an occurrence of a cache request while the cache memory is performing a linefill operation. In response to a determination that there is not a match for the cache request in the cache memory, another determination is made as to whether or not there is a match for the cache request with a block of information within the ongoing linefill operation.

Abstract: A high-speed carry-lookahead binary adder is disclosed. The binary adder includes multiple rows of carry-lookahead circuits, a half-sum module, and a sum/carry module. A first carry-lookahead circuit row includes multiple four-bit group generate circuits and multiple four-bit group propagate circuits. Each of the four-bit group generate circuits produces a generate signal for a corresponding bit location. Each of the four-bit group propagate circuits produces a propagate signal for a corresponding bit location. The half-sum module is utilized to generate a half-sum signal. By utilizing the half-sum signal, the generate signals, and the propagate signals, the sum/carry module generates sum signals and a carry signal.

Abstract: A method and apparatus for characterizing dimensions and parasitic capacitance between integrated-circuit interconnects are disclosed. The apparatus is a test structure including at least two substantially identical oscillators, at least two substantially identical counters, and a pulse generator. Each of the oscillators is connected to an integrated-circuit interconnect. Each of the counters is coupled to a respective oscillator. The pulse generator is utilized to inject a series of fixed-length clock pulses to each of the oscillators such that the parasitic capacitance of the integrated-circuit interconnects can be characterized by the ratio of oscillation periods of the oscillators to parasitic capacitances of the integrated-circuits.

Abstract: A method and system for front-end and back-end gathering of store instructions within a processor is disclosed. In accordance with the method and system of the present invention, the store queue includes a front-end queue and a back-end queue. In response to a determination that the data field of the first entry of the front-end queue is not filled completely, another determination is made as to whether or not an address for a store instruction in a subsequent second entry is equal to an address for the store instruction in the first entry plus a byte count in the first entry. If so, the store instruction in the subsequent second entry is collapsed into the store instruction in the first entry.

Abstract: A method and system for performing non-standard insitu burn-in testings is disclosed. In accordance with the method and system of the present invention, a transition counter is provided for each of the integrated-circuit (IC) devices under test. A set of scan strings is transmitted to the transition counter in each of the IC devices while the IC devices are operating under a high-temperature /high-voltage environment. A determination is then made as to whether or not a value from the transition counter in each of the IC devices operating under the high-temperature environment is within a predefined range in response to the transmitted scan strings. An indicator associated with each of the IC devices operating under the high-temperature/high-voltage environment is set in response to the transition counter value that occurred outside the predefined range. The IC devices that do not have the indicator set are subsequently tested again with the IC devices operating in room temperature and nominal voltage.

Abstract: A method and system for front-end gathering of store instructions within a processor is disclosed. In accordance with the method and system of the present invention, a store queue within a data-processing system includes a front-end queue and a back-end queue. Multiple entries are provided in the back-end queue, and each entry includes an address field, a byte-count field, and a data field. A determination is first made as to whether or not a data field of a first entry of the front-end queue is filled completely. In response to a determination that the data field of the first entry of the front-end queue is not filled completely, another determination is made as to whether or not an address for a store instruction in a subsequent second entry is equal to an address for the store instruction in the first entry plus a byte count in the first entry.

Abstract: A cache memory having a selectable cache-line replacement scheme is described. In accordance with a preferred embodiment of the present invention, the cache memory has a number of cache lines, a number of token registers, a token, and a selection circuit. The token registers are connected to each other in a ring configuration. There is an equal number of token registers and cache lines, and each of the token registers is associated with one of the cache lines. The token is utilized to indicate one of the cache lines as a candidate for replacement by the associated token register in which the token settles. The selection circuit is associated with all of the token registers. This selection circuit provides at least two methods of controlling the movement of the token within the ring of the token registers, to be selectable during runtime. Each method of token movement represents a cache-line replacement scheme.

Abstract: A method and system for performing perspective divide operations on three-dimensional graphics data within a computer system is disclosed. In accordance with the method and system of the present invention, a 3-D graphical image is represented by three-dimensional graphical object data via a number of vertices. In a first iteration, the following steps are performed concurrently: computing a set of clip coordinates for a vertex N, wherein the set of clip coordinates is a four-component vector ?x', y', z', w'!; refining an estimate value of 1/w' for a vertex N-1, wherein vertex N-1 is a vertex calculated one iteration previous to vertex N; and, generating a clip code for the vertex N-1 .

Abstract: A method and system for speculatively sourcing data among cache memories within a multiprocessor data-processing system is disclosed. In accordance with the method and system of the present invention, the data-processing system has multiple processing units, each of the processing units including at least one cache memory. In response to a request for data by a first processing unit within the data-processing system, an intervention response is issued from a second processing unit within the data-processing system that contains the requested data. The requested data is then sourced from a secondary cache memory within the second processing unit onto a system data bus concurrently with invalidating a copy of the requested data from a primary cache within the second processing unit. During this time, the second processing unit is also pending for a combined response to return from all the processing units.

Abstract: A method and system for optimizing Java bytecodes before bytecode interpretation within a computer system is disclosed. In accordance with the method and system of the present invention, a first bytecode and a second bytecode are first obtained from a file. Both the first bytecode and the second bytecode are results of a compilation of a high-level computer program. A set of instructions native to a processor within the computer system can be formed by compiling these first bytecode and second bytecode. An optimizable bytecode table is provided, and the optimizable bytecode table includes a multiple of bytecode-pair entries and a corresponding optimized bytecode. A determination is made as to whether or not the first bytecode and the second bytecode are optimizable by comparing the first bytecode and the second bytecode with all the bytecode-pair entries within the optimizable bytecode table.