Abstract: A method for providing a regulated core voltage to a processor within a computer system is disclosed. In accordance with a method and system of the present invention, a power supply is provided for a processor that includes multiple core transistors and multiple I/O transistors. An input voltage is supplied to a first power input of the processor for powering the I/O transistors within the processor. This input voltage is also supplied to a second power input of the processor for powering the core transistors within the processor via a voltage regulator and a resistor, with the voltage regulator and the resistor connected in parallel, such that the voltage drop across said voltage regulator can be reduced.

Abstract: A method for executing a non-native mode-sensitive instruction within a computer system is disclosed. In accordance with the method and system of the present invention, a computer system as described, capable of executing a non-native mode-sensitive instruction, includes a system memory, an instruction set convertor, and a processor. The system memory is utilized to store the non-native mode-sensitive instruction. The instruction set convertor, having a Semantics Table, is utilized for converting the non-native mode-sensitive instruction to a group of native instructions by preemptively testing whether or not the mode-sensitive instruction is preceded by a mode-altering instruction within a single block, and for accessing the Semantics Table for the non-native instruction with an address according to the preemptive testing. The processor is then utilized to process the group of native instructions from the instruction set convertor.

Abstract: A method and system for executing a context-altering instruction within a processor are disclosed. The processor has a superscalar architecture that includes multiple pipelines, buffers, registers, and execution units. The processor also includes a machine state register for identifying a context of the processor, and a shadow machine state register in conjunction with the machine state register. During operation, a first state of the machine state register is copied to the shadow machine state register. Instructions are executed in accordance with a context identified by the first state of the machine state register. The first state of the shadow machine state register is subsequently altered to a second state in response to decoding a context-altering instruction. The context-altering instruction and subsequent instructions are then executed in accordance with the second state of the shadow machine state register.

Abstract: A hot-plug circuit for receiving a high-current load is disclosed. In accordance with a preferred embodiment of the present invention, the hot-plug circuit comprises a transistor, a capacitor, a resistor, and a control circuit module. The transistor is coupled between a power supply and an input that is adapted to receive the high-power adaptor card. The capacitor is coupled between a first terminal and a second terminal of the transistor. The resistor is coupled to the first terminal of the transistor. Finally, the control circuit module is for applying a first bias voltage to the second terminal of the transistor via the resistor in order to turn the transistor off during an absence of the high-current load, and for applying a second bias voltage to the second terminal of the transistor via the resistor in order to turn the transistor on under a linear conduction mode upon an initial contact of said high-current load to the input.

Abstract: A method and system for translating peer-to-peer access across multiple Peripheral Component Interconnect (PCI) host bridges within a data-processing system are disclosed. In accordance with the method and system of the present invention, a processor and a system memory are connected to a system bus. A first and at least a second PCI local buses are also connected to the system bus via a first PCI host bridge and a second PCI host bridge, respectively. The two PCI local buses have bus transaction protocols that are different from those of the system bus. At least one PCI device is connected to each of the two PCI local buses, and shares data with the processor and the system memory. In addition, each PCI device shares data with the other PCI device as peer-to-peer devices across multiple PCI host bridges.

Abstract: A method and system for executing a non-native stack-based instruction within a computer system is disclosed. In accordance with the method and system of the present invention, a computer system capable of executing a set of non-native stack-access instructions is provided which includes a system memory, an instruction set convertor, and a processor. The system memory is utilized to store the non-native stack-access instructions, and part of the system memory is utilized as a stack. The instruction set convertor is utilized to convert the non-native stack-access instructions to a set of native instructions. When encountering a block of non-native stack-access instructions which include paired push and pop stack operations, the instruction set convertor produces a set of native instructions that ignores paired push and pop stack operations and retains all relevant number values in general purpose registers.

Abstract: A method and system for speculatively sourcing cache memory data within a multiprocessor data-processing system is disclosed. In accordance with the method and system of the present invention, the data-processing system has multiple processing units, each of the processing units including at least one cache memory. In response to a request for data by a first processing unit within the data-processing system, an intervention response is issued from a second processing unit within the data-processing system that contains the requested data. The requested data is then read from a cache memory within the second processing unit before a combined response from all the processing units returns to the second processing unit.

Abstract: A method and system for back-end gathering of store instructions within a processor is disclosed. In accordance with the method and system of the present invention, a store queue within a data-processing system includes a front-end queue and a back-end queue. A multiple of entries is provided in the back-end queue, and each entry includes an address field, a byte-count field, and a data field. A determination is first made as to whether or not a data field of a last entry of the back-end queue is completely filled. In response to a determination that the data field of the last entry of the back-end queue is not completely filled, another determination is made as to whether or not an address for a store instruction in a subsequent entry is equal to an address for a store instruction in the last entry plus a byte count in the last entry.

Abstract: A method and system for allocating data among cache memories within a symmetric multiprocessor data-processing system are disclosed. The symmetric multiprocessor data-processing system includes a system memory and multiple processing units, wherein each of the processing units has a cache memory. The system memory is divided into a number of segments, wherein the number of segments is equal to the total number of cache memories. Each of these segments is represented by one of the cache memories such that a cache memory is responsible to cache data from its associated segment within the system memory.

Abstract: A method for dynamically translating bus address within a computer system is disclosed. In accordance with the method and system of the present invention, a computer system has a multiple of buses connected in a hierarchial manner. Information concerning a bus and a device attached to a bus are stored in a Hardware Namespace. In response to a request for an access to a device attached to one of the buses for the first time, a determination is made from the Hardware Namespace as to whether or not there is resource available for the device in a parent bus of the device. If there is resource available in the parent bus for the device, another determination is made from the Hardware Namespace as to whether or not the resource is exclusively allocated in the parent bus for the device. If the resource is exclusively allocated in the parent bus for the device, the device is configured according to the available resource.

Abstract: An apparatus for performing ADD and ROTATE as a single instruction within a processor is disclosed. In accordance with a preferred embodiment of the present invention, the apparatus comprises an adder and a rotator. The adder is utilized for adding a first number to a second number in a multiple stages to yield a carry-out and a sum output. During each of these stages, the adder produces a group generate value and a group propagate value. The rotator is utilized for rotating the group propagate value and the group generate value at each of the stages before the yielding of the carry-out and the sum output. As such, both ADD and ROTATE instructions can be completed within a single processor cycle.

Abstract: A method for encoding an input data stream of source symbols to produce an output sequence of pointers is disclosed. An initial part of the input data stream is encoded as a LITERAL.sub.-- POINTER by a compressor. A LITERAL.sub.-- POINTER includes at least one data byte from the data stream. A subsequent part of the input data stream is encoded as a COPY.sub.-- POINTER. The COPY.sub.-- POINTER includes a count and a displacement pointing to a history-buffer within the compressor. All succeeding data bytes from the input data stream are encoded as LITERAL.sub.-- POINTERs and COPY.sub.-- POINTERs in an alternating fashion, such that an encoded output sequence output by the compressor includes a string of pointers alternating between LITERAL.sub.-- POINTERs and COPY.sub.-- POINTERs.

Abstract: A method for encoding an input data stream of source symbols to produce an output sequence of pointers is disclosed. A LITERAL string in an input data stream is first loaded into a history-buffer. A value of a history-buffer pointer is copied to a register to indicate a starting position of the LITERAL string within the history-buffer. A counter is incremented for each subsequent LITERAL symbol from the input data stream. Then, the LITERAL string and each subsequent LITERAL symbol from the input data stream is encoded utilizing a value within the register and a value within the counter as a LITERAL.sub.-- POINTER. Finally, the LITERAL.sub.-- POINTER is outputted from a data compressor.

Abstract: A method for providing improved data compression efficiency to a data compressor unit is disclosed. Before sending the uncompressed data stream to the data compressor unit, an incoming data byte from the uncompressed data stream is first compared with a preceding data byte from the uncompressed data stream. A first counter value is incremented in response to a match between the incoming data byte and the preceding data byte. A second counter value is then incremented in response to subsequent matches between an incoming data byte and its preceding data byte after the first counter value has reached a preset value. The second counter value is finally sent to the data compressor unit at the completion of a run of the incoming data byte in substitution of a portion of the run, such that the data compressor unit can quickly resume its optimal compression ratio after an occurrence of the run within the uncompressed data stream.

Abstract: A method for graphically displaying audio data within a computer system is disclosed. A frame size is first selected for an audio data file and the audio data file is divided into a multiple number of frames. Except for the last frame, each frame contains a substantially equal number of audio data samples. Then a multiple of variables is initialized. For each frame, a first data value, a high data value, a low data value, and a last data value are selected. Each of these four data values is stored in the appropriate variable. The data selection process continues until the last frame of the data file is reached. Finally, a line connecting all the selected data value points for each frame is displayed on a graphic display.

Abstract: A method for applying solder paste on tape carrier package component sites of a printed circuit board is disclosed. In accordance with a method and system of the present invention, a stencil having multiple openings for each device pad on the printed circuit board is provided. Each of the openings is approximately 0.012".times.0.0053" in size. The stencil is then secured in a fixed position directly above a printed circuit board. Finally, solder paste is selectively applied to the printed circuit board through the stencil with an applicator.

Abstract: A phase-locked loop circuit for providing external clock signals to a processor is disclosed. The phase-locked loop circuit includes a phase/frequency detector, a voltage-control oscillator, and two charge pumps. The phase/frequency detector receives an input reference signal and provides a first differential output and a second differential output. The voltage-controlled oscillator has a feed-forward current input and is utilized to generate an output clock signal, wherein the output clock signal is also utilized as a feedback signal for the phase/frequency detector. The first charge-pump, coupled between the phase/frequency detector and the voltage-controlled oscillator, receives the first and second differential outputs from the phase/frequency detector and provides a differential voltage control signal for the voltage-controlled oscillator. The second charge pump is utilized to produce a stable system response by increasing the loop dumping.

Abstract: A scalable symmetric multiprocessor data-processing system is disclosed. The symmetric multiprocessor data-processing system includes multiple processing units and a system memory. Each of the processing units includes a cache memory for storing a subset of data contained within the system memory. A cache controller is included within each one of the processing units for controlling an associated cache memory. The cache controller contains a mode select to allow an associated cache memory to be selectively operated under either a first mode or a second mode. Furthermore, the symmetric multiprocessor data-processing system also includes a multiple of partial system memories, wherein each of the partial system memories is associated with one of the processing units such that an aggregate of contents within all of the partial system memories forms the system memory.

Abstract: A method and system for providing a multiple property search capability within an object-oriented distributed computing network are disclosed. In accordance with the method and system of the present invention, a permanent index which includes multiple property names is initially built. Next, a search expression, which includes at least one property name, is traversed in order to form a property name list. The property name list includes all of the property names which are specified within the search expression. After comparing the property name list with the permanent index, any of the specified property names which also exist in the permanent index is removed from the property name list. Thereafter, a determination is made as to whether or not there is any property name still remaining on the property name list.

Abstract: A method and system for providing parasitic capacitance estimation on interconnect data for an integrated circuit is disclosed. An integrated circuit typically includes a substrate layer and several metal layers. In accordance with the method and system of the present invention, a center wire within one of the several metal layers is first identified. Then, a first capacitance value between a first wire and the center wire as well as a second capacitance value between a second wire and the center wire are determined. The first wire, the second wire, and the center wire are in the same metal layer. Next, a third capacitance value between a third wire and the center wire is determined. This third wire is in a metal layer located directly beneath the center wire. Finally, a fourth capacitance value between a fourth wire and the center wire is determined. The fourth wire is in a metal layer located directly above the center wire.