Abstract: A method and apparatus are disclosed that allow rapid positioning of a cursor within a data processing system graphical user interface. The method involves establishing a preferred order of the cursor movement between at least a subset of windows with all windows active on the data processing system and then repositioning the cursor based upon the preferred order of the cursor movement between the windows when an input stimulus is activated. Next, the window is then activated based on the cursor being repositioned and then giving the activated window the focus within the graphical user interface, which then leads to the activated window being prepared for date manipulation. The apparatus comprises a keyboard coupled to the data processing system, a pointer device, also coupled to the data processing system, and means for establishing a user definable window application order preference queue.

Abstract: A method and system of implementing an early data dependency resolution mechanism for a high-performance data processing system that utilizes out-of-order instruction issue is disclosed. In accordance with the present disclosure, an instruction cache and a register-dependency cache are provided. The instruction cache has multiple cache lines, and each of these cache lines is capable of storing multiple instructions. The register-dependency cache contains an identical number of cache lines as in the instruction cache, and each of the cache lines within the register-dependency cache is capable of storing an identical number of register-dependency units as instructions in each of the cache lines within the instruction cache. In a single processor cycle, a group of register-dependency units are fetched from the register-dependency cache. All register-dependency units that have no forward data dependency within the group of register-dependency units are identified utilizing an Instruction Dispatch Unit.

Abstract: A cache memory having a mechanism for managing offset and aliasing conditions is disclosed. In accordance with a preferred embodiment of the invention, the cache memory comprises a first directory circuit, a second directory circuit, a multiple number of most recently used bits, and a multiple number of set/reset circuits. The first directory circuit, having multiple caches lines, is utilized to receive partial effective addresses. The second directory circuit is utilized to receive an output from the first directory circuit. A most recently used bit is associated with each cache line within the first directory circuit. The set/reset circuit, coupled to each of the most recently used bits, is utilized to set one of the most recently used bits to a first state while concurrently resetting the rest of the most recently used bits to a second state within a single cycle during an occurrence of an offset or aliasing conditions such that offset or aliasing conditions can be more efficiently managed.

Abstract: A method and system for preventing information corruption in a cache memory due to a bus error which occurs during a cache linefill operation is disclosed. The cache memory includes multiple cache lines, and a tag is associated with each cache line. In accordance with the present disclosure, a tag associated with a cache line is validated before a linefill operation is performed on the cache line. In response to an occurrence of a bus error during the linefill operation, the tag associated with the cache line for which a linefill operation is performed, is invalidated such that the information within the cache line remains valid during a linefill operation unless a bus error occurs.

Abstract: A method and system of implementing a cache coherency mechanism for supporting a non-inclusive cache memory hierarchy within a data processing system is disclosed. In accordance with the method and system of the invention, the memory hierarchy includes a primary cache memory, a secondary cache memory, and a main memory. The primary cache memory and the secondary cache memory are non-inclusive. Further, a first state bit and a second state bit are provided within the primary cache, in association with each cache line of the primary cache. As a preferred embodiment, the first state bit is set only if a corresponding cache line in the primary cache memory has been modified under a write-through mode, while the second state bit is set only if a corresponding cache line also exists in the secondary cache memory. As such, the cache coherency between the primary cache memory and the secondary cache memory can be maintained by utilizing the first state bit and the second state bit in the primary cache memory.

Abstract: A method for record searching in a database within a computer system are disclosed. The computer system includes a main processor, a main memory, and a peripheral storage device having a secondary processor. In accordance with the method of the present invention, a command block specifying a search string for record searching in at least one database table of the database is prepared. Subsequently, the command block is issued from the main processor to the secondary processor within the peripheral storage device of the computer system. The secondary processor within the peripheral storage device is then utilized to read the database table(s) into a memory within the peripheral storage device, in response to a receipt of the command block. The search string in the command block is compared to each record of the database table(s) within the memory of the peripheral storage device to identify all the records therein which contain the search string.

Abstract: A method and system for reclaiming stacked volumes within a peripheral data storage subsystem is disclosed. In accordance with the method and system of the present invention, a database is interrogated to determine whether or not an opportunistic reclaim threshold of a stacked volume has been reached after a service request from a host computer has been performed on a stacked volume and while the stacked volume is still mounted. If the opportunistic reclaim threshold of the stacked volume has not been reached, the stacked volume is released and dismounted. However, if the reclaim threshold of the stacked volume has been reached, another determination is made as to whether or not a service request for the host computer is pending. If the host computer requires service, the stacked volume is again released and dismounted. Otherwise, if the host computer does not require service, at least one data set from the mounted stacked volume is opportunistically reclaimed while the stacked volume is still mounted.

Abstract: An improved package structure for integrated-circuit chips is disclosed. In accordance with a preferred embodiment of the present invention, the integrated-circuit packaged structure comprises a wiring substrate, an integrated-circuit chip, and a heat spreader. The integrated-circuit chip has a first surface and a second surface, wherein the first surface is electrically and mechanically connected to the wiring substrate via a first set of solder joints. The heat spreader is connected to the second surface of the integrated-circuit chip via a second set of solder joints. The heat spreader includes an adhesion-promotion layer on top of a silicon layer, such that heat generated from the integrated-circuit chip can be efficiently transmitted to and subsequently dissipated by the heat spreader.

Abstract: A method for cancelling optical servo crosstalk within an optical disk drive is disclosed. In accordance with the method and system of the present invention, the optical disk drive system includes a focus control module, a tracking control module, a variable frequency notch filter, and a lookup table. The focus control module is utilized for moving an objective lens in response to a focus error signal in order to maintain a laser beam in an in-focus condition on an optical disk. The tracking control module is utilized for moving a moving optical element in response to a tracking error signal to direct the laser beam onto a desired track position of the optical disk. The lookup table within the focus control module is utilized for storing several sets of tap coefficients for the variable frequency notch filter.

Abstract: A method for compressing a set of compiled microcode to be utilized within a data processing system is disclosed. In accordance with the method and system of the present invention, all branch instructions within a set of compiled microcode are first identified. Then, the set of compiled microcode is parsed into a number of microcode segments such that each microcode segment begins at an instruction following each identified branch instruction or at a target address of each identified branch instruction. Subsequently, each of these microcode segments is individually translated to its compressed form by utilizing a data-compression routine. Finally, all the compressed microcode segments are concatenated together and linked by inserting branch instructions with modified target address, to yield a set of compressed executable microcode. By doing so, the required memory for storing the compressed executable microcode is reduced.

Abstract: A method for implementing a four-way least recently used cache line replacement scheme in a four-way cache memory is disclosed. The cache memory includes multiple cache lines, and each cache line includes four congruence sets. In accordance with the present disclosure, a 5-bit Least Recently Used (LRU) field is associated with each of the cache lines within the cache memory. For a particular cache line, a set number of a least recently used set among the four congruence sets is stored in any two bits of the LRU field associated with that cache line. Next, a set number of the second least recently used set among the four congruence sets is stored in another two bits of the same LRU field associated with the same cache line. Finally, a last bit of the 5-bit LRU field is set to a specific state in response to a determination of which one of the remaining two sets is the second most recently used set.

Abstract: A method for rebuilding contents of a malfunctioned direct access storage device within a log-structured array is disclosed. In accordance with the method and system of the present invention, each direct access storage device within a log-structured array is divided into multiple segment-columns, and each corresponding segment-column from each direct access storage device within the log-structured array forms a segment. A segment is first located within the direct access storage devices. A determination is made as to whether or not the segment is empty. In response to a determination that the segment is empty, a pointer is moved within a segment-column mapping table from pointing to a segment-column in the malfunctioned direct access storage device to point to a segment-column in a spare direct access storage device of the segment.

Abstract: In a component-based system such as OpenDoc, only one component can be "active," such that only the active component has control of the menubar and the pop-up menus. An active component may contain both intrinsic contents and embedded components. The active component allows the user to "select" some or all of its embedded components such that the user can act on the selected embedded components. When the selection is an intrinsic content, it is straightforward for the active component to present menu options that allows the user to interact with the selection. However, when the selection is an embedded component, there is no standard method for presenting menu options that allows the user to interact with selected embedded component; especially when multiple embedded components are selected within a compound document. This invention provides a method for sharing a menu by multiple embedded components in a component-based computer system.

Abstract: A method for preventing peer-to-peer access across separate Peripheral Component Interconnect (PCI) host bridges within a data-processing system is described. In accordance with the method and system of the present invention, during an access request from a PCI device, a first determination is made as to whether or not the access request is for a system memory attached to a system bus. In response to a determination that the access request is not for a system memory attached to the system bus, another determination is made as to whether or not the access request is for a PCI device under the same PCI host bridge as the requesting PCI device. In response to a determination that the access request is not for a PCI device under the same PCI host bridge as the requesting PCI device, denying the access request such that a PCI peer-to-peer access across separate PCI host bridges within a data processing system is prevented.

Abstract: A method for supporting peer-to-peer access across separate Peripheral Component Interconnect (PCI) host bridges within a data-processing system is described. In accordance with the method and system of the present invention, during an access request from a PCI device, a first determination is made as to whether or not the access request is for a system memory attached to a system bus. In response to a determination that the access request is not for a system memory attached to the system bus, another determination is made as to whether or not the access request is for a PCI device under the same PCI host bridge as the requesting PCI device. In response to a determination that the access request is not for a PCI device under the same PCI host bridge as the requesting PCI device, executing added protocols for the support of PCI peer-to-peer access request across separate PCI host bridges within the data-processing system.

Abstract: A method for compressing a set of microcode to be utilized within a data processing system is disclosed. In accordance with the method and system of the present invention, a set of compiled microcode is parsed into multiple microcode segments, wherein each of these microcode segments is of equal length. Each of the microcode segments is then individually compressed by utilizing a data-compression routine. Next, all of these compressed microcode segments are concatenated to yield a set of compressed executable microcode. Finally, the starting address for each of the compressed microcode segments is stored in an indexer. By so doing, the required memory for storing the compressed executable microcode is reduced.