Abstract: A computer system having an optimized display controller is disclosed. The computer system has a central processing unit connected to a system bus. Within the computer system, both a system memory and a video memory are connected in parallel to the system bus. In addition, the computer system also includes a display controller that is connected only between the system bus and a video display.

Abstract: A container for storing disc-like storage media is disclosed. The container for storing disc-like storage media includes a back cover and a turntable. The back cover has a front opening. The turntable has a substantially planar front side and a fan-shaped back side. The fan-shaped back side includes multiple storage grooves radially distributed around the fan-shaped back side. Each of the storage grooves is capable of receiving a substantially planar storage medium. The turntable is rotatable from a concealed position in which the fan-shaped back side is concealed within the back cover to an exposed position in which the fan-shaped back side is at least partially extends outside of the back cover.

Abstract: A single event effect immune oscillator circuit is disclosed. The single event upset immune oscillator circuit includes an odd number of logic circuit blocks connecting in series to provide a continuous pulse signal at an output of the oscillator circuit. Each logic circuit block has a first input, a second input, and an output. For a series of logic circuit blocks i, where i=1 to n (n is an odd number), the output of a logic circuit block i is connected to a first input of a logic circuit block i+1. The output of the logic circuit block i is also connected to a first input of a logic circuit block i+x, wherein x is an odd number greater than one and less than or equal to n.

Abstract: A method for manufacturing a programmable chalcogenide fuse within a semiconductor device is disclosed. A resistor is initially formed on a substrate. Then, a chalcogenide fuse is formed on top of the resistor. Finally, a conductive layer is deposited on top of the chalcogenide fuse for providing electrical conduction to the chalcogenide fuse.

Abstract: A radiation hardened silicon-on-insulator transistor is disclosed. A dielectric layer is disposed on a substrate, and a transistor structure is disposed on the dielectric layer. The transistor structure includes a body region, a source region, a drain region, and a gate layer. The body region is formed on a first surface portion of the dielectric layer, the source region is formed on a second surface portion of the dielectric layer contiguous with the first surface portion, the drain region is formed on a third surface portion of the dielectric layer contiguous with the first surface portion, and the gate layer overlies the body region and being operative to induce a channel in that portion of the body region disposed between and adjoining the source region and the drain region. In addition, multiple diffusions are placed across two edges of the source region.

Abstract: A circuit for filtering single event effect (SEE) induced glitches is disclosed. The circuit for filtering SEE induced glitches comprises an SEE immune latch circuit and a delay element. The SEE immune latch circuit includes a first input, a second input, and an output. The SEE immune latch changes from one state to another state only upon having incoming input signals of identical polarity being applied contemporaneously at both the first input and the second input. The first input of the SEE immune latch circuit is directly connected to a signal input, and the second input of the SEE immune latch circuit is connected to the signal input via the delay element. The delay element provides a signal delay time equal to or greater than a pulse width of an SEE induced glitch but less than a pre-determined pulse width of an incoming signal at the signal input under normal operation.

Abstract: A method for manufacturing microscopic canals within a semiconductor is disclosed. A shallow trench is initially formed on a substrate using a patterned photoresist. After the patterned photoresist has been removed from the substrate, a separation layer, such as a Titanium layer, is deposited on the substrate. Subsequently, a cap layer, such as a Titanium nitride layer, is deposited on the separation layer. Both the separation layer and the cap layer are then polished off from the surface of the substrate. Finally, a Tungsten layer is deposited on the substrate and in the trench such that a microcanal will be formed within the trench as a result.

Abstract: A single event upset hardened latch circuit is disclosed. The single event hardened latch circuit includes a first dual-port inverter and a second dual-port inverter. An input is coupled to the first dual-port inverter via a first set of pass gates. The first dual-port inverter is coupled to the second dual-port inverter via a second set of pass gates. The output is connected to the first and second dual-port inverters.

Abstract: A single event upset hardened memory cell to be utilized in static random access memories is disclosed. The single event upset hardened memory cell includes a first set of cross-coupled transistors, a second set of cross-coupled transistors, and a set of isolation transistors. The set of isolation transistors is coupled to the first set of cross-coupled transistors such that two inversion paths are formed between the cross-coupled transistors and the isolation transistors.

Abstract: A multiplexor having a single event upset (SEU) hardened data keeper circuit is disclosed. The multiplexor includes a precharge transistor, an isolation transistor, an invertor, and an SEU immune storage cell. Both the gate of the precharge transistor and the gate of the isolation transistor are connected to a clock signal. The SEU immune storage cell has a first access node and a second access node. The first access node is complementary to the second access node. The first access node is connected to the precharge transistor and the second access node is connected to the isolation transistor. The invertor is coupled between the precharge transistor and the isolation transistor.

Abstract: A single event effect hardening technique for removing glitches in digital logic circuits is disclosed. The noise immune latch circuit includes a first input, a second input, and an output. The noise immune latch circuit includes a first set of two cross-coupled transistors, a second set of two cross-coupled transistors, a first set of isolation transistors, and a second set of isolation transistors. The cross-coupling is accomplished by connecting a gate of each transistor to a drain of another transistor in a same set. The first and second sets of isolation transistors are respectively connected to the first and second sets of cross-coupled transistors such that two inversion paths are formed including the two sets of cross-coupled transistors and the two sets of isolation transistors. The noise immune latch circuit changes from one state to another state only upon having incoming input signals of identical polarity being applied contemporaneously at both the first input and the second input.

Abstract: A method and system for shape processing within an integrated circuit layout for parasitic capacitance estimation is disclosed. In accordance with the method and system of the present invention, a set of coordinates of an overlapping region formed by at least one interconnect is first identified. Subsequently, each metal layer present within the overlapping region is classified. Each interconnect edge present on each side of the overlapping region is then determined. Finally, a neighbor in a direction perpendicular to each side of the overlapping region is determined. By so doing, the parasitic capacitance between the overlapping region and its determined neighbors can be evaluated.

Abstract: A method and apparatus for assisting garbage collection process within a Java virtual machine are disclosed. A virtual object heap and a physical object heap are provided within the Java virtual machine, with the virtual object heap considerably larger than the physical object heap. Objects from Java applications are allocated within the virtual object heap. Each address of the allocated objects within the virtual object heap is translated into an address of a location within the physical object heap. Garbage collection is performed in the virtual object heap only when a total number of objects within the virtual object heap has reached a predetermined threshold.

Abstract: A highly efficient current controlled thermoelectric cooling system is disclosed. The highly efficient current controlled thermoelectric cooling system includes a first thermal sink, a second thermal sink, a thermoelectric element, and a variable current source. The first thermal sink has a temperature higher than an ambient temperature while the second thermal sink has a temperature lower than the ambient temperature. The first thermal sink is continuously coupled to the thermoelectric element while the second thermal sink is selectively coupled to the thermoelectric element via a mass. A variable current source provides a controlled current pulse to the thermoelectric element such that heat transfer can be effectively achieved between the thermoelectric element and both thermal sinks.

Abstract: A method for a short-term prediction of future ship motion in open water to furnish visual cueing information that can be remotely presented to a pilot during an aircraft landing is described. Two sets of samples of the sea surface geometry along a radial azimuth line from a ship as a function of elevation of a sensor are first acquired. These are compensated to remove the components due to the ship's motion. Two wave traces are then separately derived in Cartesian format from the two sets of acquired samples. These wave traces are subjected to a Fast Fourier Transform to detect the amplitudes and phases of the individual wavelength components. The direction of the wavelength components is determined using a measure of their phase change in the scan direction during the time interval between the two scans together with their measured wavelength.

Abstract: An apparatus for generating an end-around carry to an end-around carry adder in a floating-point pipeline within a computer system is disclosed. The apparatus for generating an end-around carry includes a shift-comparison logic circuit, a sign-comparison circuit, and a logic gate. The shift-comparison logic circuit produces a shift-count signal and the sign-comparison logic circuit produces an effective operation signal. Coupled to the shift-comparison logic circuit and the sign-comparison logic circuit, the logic gate combines the shift-count signal and the effective operation signal with a carry-out signal generated by an end-around carry adder to provide an end-around carry signal for the end-around carry adder.

Abstract: A method and system for handling detected faults in a processor to improve reliability of a computer system is disclosed. A fault-tolerant computer system is provided which includes a first processor, a second processor, and a comparator. Coupled to a system bus, a first processor is utilized to produce a first output. The second processor, also coupled to the system bus, is utilized to produce a second output. During the operation of the computer system, the second processor operates at the same clock speed as the first processor and lags behind the first processor. The comparator is utilized to compare the first and second output such that an operation will be retried if the first output is not the same as the second output.

Abstract: A method and system for speculatively sourcing data from a cache memory within a multiprocessor data-processing system is disclosed. In accordance with the method and system of the present invention, the data-processing system has multiple processing units, each of the processing units including at least one cache memory. In response to a request for data by a first processing unit within the data-processing system, an intervention response is issued from a second processing unit within the data-processing system that contains the requested data. The requested data is then sourced from a cache memory within the second processing unit by driving the requested data onto a system data bus before a combined response from all the processing units returns to the second processing unit.

Abstract: A domino logic circuit having a clocked precharge is disclosed. The domino logic circuit includes a precharge transistor, a discharge transistor, multiple input transistors, and a supplemental precharge transistor. Connected to a power supply, the precharge transistor receives a clock input. The discharge transistor is connected to ground and also receives the clock input. The input transistors, which are coupled between the precharge transistor and the discharge transistor, each receives a signal input. The supplemental precharge transistor is connected to the power supply and to a body of each of the input transistors. The supplemental precharge transistor also receives the same clock input as the precharge transistor.